NXP Semiconductors
Data Sheet: Technical Data
i.MX RT1060 Crossover
Processors for Consumer
Products
Document Number: IMXRT1060CEC
Rev. 3, 03/2022
MIMXRT1061DVL6A
MIMXRT1061DVJ6A
MIMXRT1062DVL6A
MIMXRT1062DVJ6A
MIMXRT106ADVL6A
MIMXRT106FDVL6A
MIMXRT106PDVL6A
MIMXRT106SDVL6B
MIMXRT1061DVL6B
MIMXRT1061DVJ6B
MIMXRT1062DVL6B
MIMXRT1062DVJ6B
MIMXRT106ADVL6B
MIMXRT106FDVL6B
MIMXRT106PDVL6B
Package Information
Plastic Package
196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch
196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 6
1
i.MX RT1060 Introduction
The i.MX RT1060 is a new processor family featuring
NXP’s advanced implementation of the Arm
Cortex®-M7 core, which operates at speeds up to 600
MHz to provide high CPU performance and best
real-time response.
The i.MX RT1060 processor has 1 MB on-chip RAM.
512 KB can be flexibly configured as TCM or general
purpose on-chip RAM, while the other 512 KB is
general-purpose on-chip RAM. The i.MX RT1060
integrates advanced power management module with
DCDC and LDO that reduces complexity of external
power supply and simplifies power sequencing. The
i.MX RT1060 also provides various memory interfaces,
including SDRAM, RAW NAND FLASH, NOR
FLASH, SD/eMMC, Quad SPI, and a wide range of
other interfaces for connecting peripherals, such as
WLAN, Bluetooth™, GPS, displays, and camera
sensors. The i.MX RT1060 has rich audio and video
features, including LCD display, basic 2D graphics,
camera interface, SPDIF, and I2S audio interface. The
i.MX RT1060 has analog interfaces, such as ADC,
ACMP, and TSC.
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
1. i.MX RT1060 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Special signal considerations . . . . . . . . . . . . . . . 19
3.2. Recommended connections for unused analog
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1. Chip-Level conditions . . . . . . . . . . . . . . . . . . . . . 22
4.2. System power and clocks . . . . . . . . . . . . . . . . . . 29
4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.5. External memory interface . . . . . . . . . . . . . . . . . 46
4.6. Display and graphics . . . . . . . . . . . . . . . . . . . . . . 56
4.7. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.8. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.9. Communication interfaces . . . . . . . . . . . . . . . . . . 69
4.10. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 84
5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 84
5.2. Boot device interface allocation . . . . . . . . . . . . . . 84
6. Package information and contact assignments . . . . . . . 89
6.1. 10 x 10 mm package information . . . . . . . . . . . . 89
6.2. 12 x 12 mm package information . . . . . . . . . . . 101
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8. Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
i.MX RT1060 Introduction
The i.MX RT1060 is specifically useful for applications such as:
• Industrial Human Machine Interfaces (HMI)
• Motor Control
• Home Appliance
1.1
Features
The i.MX RT1060 processors are based on Arm Cortex-M7 Core Platform, which has the following
features:
• Supports single Arm Cortex-M7 Core with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
— Support the Armv7-M Thumb instruction set
• Integrated MPU, up to 16 individual protection regions
• Tightly coupled GPIOs, operating at the same frequency as Arm Core
• Up to 512 KB I-TCM and D-TCM in total
• Frequency of 600 MHz
• Cortex M7 CoreSight™ components integration for debug
• Frequency of the core, as per Table 10, "Operating ranges," on page 24.
The SoC-level memory system consists of the following additional components:
— Boot ROM (128 KB)
— On-chip RAM (1 MB)
– 512 KB OCRAM shared between ITCM/DTCM and OCRAM
– Dedicate 512 KB OCRAM
• External memory interfaces:
— 8/16-bit SDRAM, up to SDRAM-133/SDRAM-166
— 8/16-bit SLC NAND FLASH, with ECC handled in software
— SD/eMMC
— SPI NOR/NAND FLASH
— Parallel NOR FLASH with XIP support
— Two single/dual channel Quad SPI FLASH with XIP support
• Timers and PWMs:
— Two General Programmable Timers (GPT)
– 4-channel generic 32-bit resolution timer for each
– Each support standard capture and compare operation
— Four Periodical Interrupt Timers (PIT)
– Generic 32-bit resolution timer
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NXP Semiconductors
i.MX RT1060 Introduction
– Periodical interrupt generation
— Four Quad Timers (QTimer)
– 4-channel generic 16-bit resolution timer for each
– Each support standard capture and compare operation
– Quadrature decoder integrated
— Four FlexPWMs
– Up to 8 individual PWM channels per each
– 16-bit resolution PWM suitable for Motor Control applications
— Four Quadrature Encoder/Decoders
Each i.MX RT1060 processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Display Interface:
— Parallel RGB LCD interface
– Support 8/16/24 bit interface
– Support up to WXGA resolution
– Support Index color with 256 entry x 24 bit color LUT
– Smart LCD display with 8/16-bit MPU/8080 interface
• Audio:
— S/PDIF input and output
— Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces
— MQS interface for medium quality audio via GPIO pads
• Generic 2D graphics engine:
— BitBlit
— Flexible image composition options—alpha, chroma key
— Porter-duff blending
— Image rotation (90, 180, 270)
— Image size
— Color space conversion
— Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)
— Standard 2D-DMA operation
• Camera sensors:
— Support 24-bit, 16-bit, and 8-bit CSI input
• Connectivity:
— Two USB 2.0 OTG controllers with integrated PHY interfaces
— Two Ultra Secure Digital Host Controller (uSDHC) interfaces
– MMC 4.5 compliance with HS200 support up to 200 MB/sec
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3
i.MX RT1060 Introduction
•
– SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec
– Support for SDXC (extended capacity)
— Two 10/100M Ethernet controller with support for IEEE1588
— Eight universal asynchronous receiver/transmitter (UARTs) modules
— Four I2C modules
— Four SPI modules
— Two FlexCAN modules
— One FlexCAN (with Flexible Data-Rate supported)
— Three FlexIO modules
GPIO and Pin Multiplexing:
— General-purpose input/output (GPIO) modules with interrupt capability
— Input/output multiplexing controller (IOMUXC) to provide centralized pad control
The i.MX RT1060 processors integrate advanced power management unit and controllers:
• Full PMIC integration, including on-chip DCDC and LDO
• Temperature sensor with programmable trim points
• GPC hardware power management controller
The i.MX RT1060 processors support the following system debug:
• Arm CoreSight debug and trace architecture
• Trace Port Interface Unit (TPIU) to support off-chip real-time trace
• Cross Triggering Interface (CTI)
• Support for 5-pin (JTAG) and SWD debug interfaces
The i.MX RT1060 processors support the following analog interfaces:
• Two Analog-Digital-Converters (ADC), 16-channel for each, 20-channel in total
• Four Analog Comparators (ACMP)
Security functions are enabled and accelerated by the following hardware:
• High Assurance Boot (HAB)
• Data Co-Processor (DCP):
— AES-128, ECB, and CBC mode
— SHA-1 and SHA-256
— CRC-32
• Bus Encryption Engine (BEE)
— AES-128, ECB, and CTR mode
— On-the-fly QSPI Flash decryption
• True random number generation (TRNG)
• Secure Non-Volatile Storage (SNVS)
— Secure real-time clock (RTC)
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i.MX RT1060 Introduction
•
— Zero Master Key (ZMK)
Secure JTAG Controller (SJC)
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions such as display and camera interfaces, connectivity interfaces,
and security features are not offered on all derivatives.
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5
i.MX RT1060 Introduction
1.2
Ordering information
Table 1 provides examples of orderable part numbers covered by this Data Sheet.
Table 1. Ordering information
Part Number
MIMXRT1061DVJ6A
MIMXRT1061DVJ6B
MIMXRT1061DVL6A
MIMXRT1061DVL6B
Features
• 600 MHz, commercial
grade for general purpose,
with MPU/FPU
• eDMA
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• PWM x4
• ENC x4
• WDOG x4
• No LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
• eMMC 4.5/SD 3.0 x2
•
•
•
•
•
•
• 600 MHz, commercial
grade for general purpose,
with MPU/FPU
• eDMA
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• PWM x4
• ENC x4
• WDOG x4
• No LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
• eMMC 4.5/SD 3.0 x2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Junction
Temperature
Tj (C)
Package
Ethernet x2
UART x8
I2C x4
FlexSPI x2
CAN x2
FlexCAN (with Flexible
Data-Rate supported)
FlexIO x3
127 GPIOs (124 tightly
coupled)
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management controller
12 x 12 mm, 0.8 mm
pitch, 196-pin MAPBGA
0 to +95
Ethernet x2
UART x8
I2C x4
FlexSPI x2
CAN x2
FlexCAN (with Flexible
Data-Rate supported)
FlexIO x3
127 GPIOs (124 tightly
coupled)
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management controller
10 x 10 mm, 0.65 mm
pitch, 196-pin MAPBGA
0 to +95
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NXP Semiconductors
i.MX RT1060 Introduction
Table 1. Ordering information
Part Number
MIMXRT1062DVJ6A
MIMXRT1062DVJ6B
MIMXRT1062DVL6A
MIMXRT1062DVL6B
Features
• 600 MHz, commercial
grade for general purpose,
with MPU/FPU
• eDMA
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• PWM x4
• ENC x4
• WDOG x4
• LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
• eMMC 4.5/SD 3.0 x2
•
•
•
•
•
•
• 600 MHz, commercial
grade for general purpose,
with MPU/FPU
• eDMA
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• PWM x4
• ENC x4
• WDOG x4
• LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
• eMMC 4.5/SD 3.0 x2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Package
Junction
Temperature
Tj (C)
Ethernet x2
UART x8
I2C x4
FlexSPI x2
CAN x2
FlexCAN (with Flexible
Data-Rate supported)
FlexIO x3
127 GPIOs (124 tightly
coupled)
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management controller
12 x 12 mm, 0.8 mm
pitch, 196-pin MAPBGA
0 to +95
Ethernet x2
UART x8
I2C x4
FlexSPI x2
CAN x2
FlexCAN (with Flexible
Data-Rate supported)
FlexIO x3
127 GPIOs (124 tightly
coupled)
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management controller
10 x 10 mm, 0.65 mm
pitch, 196-pin MAPBGA
0 to +95
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7
i.MX RT1060 Introduction
Table 1. Ordering information
Part Number
MIMXRT106ADVL6A
MIMXRT106ADVL6B
MIMXRT106FDVL6A
MIMXRT106FDVL6B
Features
• 600 MHz, commercial
grade for general purpose,
with MPU/FPU
• Turnkey solution with NXP
VoiceSeeker AFE and
VoiceSpot Wake Word for
Alexa for IoT
• eDMA
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• PWM x4
• ENC x4
• WDOG x4
• LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
•
•
•
•
•
•
•
• 600 MHz, commercial
grade for general purpose,
with MPU/FPU
• Turnkey solution for face
and emotion recognition,
see www.
nxp.com/mcu-vision2
• eDMA
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• PWM x4
• ENC x4
• WDOG x4
• LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Junction
Temperature
Tj (C)
Package
eMMC 4.5/SD 3.0 x2
Ethernet x2
UART x8
I2C x4
FlexSPI x2
CAN x2
FlexCAN (with Flexible
Data-Rate supported)
FlexIO x3
127 GPIOs (124 tightly
coupled)
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management controller
10 x 10 mm, 0.65 mm
pitch, 196-pin MAPBGA
0 to +95
eMMC 4.5/SD 3.0 x2
Ethernet x2
UART x8
I2C x4
FlexSPI x2
CAN x2
FlexCAN (with Flexible
Data-Rate supported)
FlexIO x3
127 GPIOs (124 tightly
coupled)
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management controller
10 x 10 mm, 0.65 mm
pitch, 196-pin MAPBGA
0 to +95
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NXP Semiconductors
i.MX RT1060 Introduction
Table 1. Ordering information
Part Number
MIMXRT106PDVL6A
MIMXRT106PDVL6B
MIMXRT106SDVL6B
Features
• 600 MHz, commercial
grade for general purpose,
with MPU/FPU
• TurnKey solution with NXP
VoiceSeeker AFE and
VoiceSpot Wake
• eDMA
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• PWM x4
• ENC x4
• WDOG x4
• LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
•
•
•
•
•
•
•
•
• 600 MHz, commercial
grade for general purpose,
with MPU/FPU
• Turnkey solution for local
voice (phoneme based)
recognition, see
www.nxp.com/mcu-local2
• eDMA
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• PWM x4
• ENC x4
• WDOG x4
• LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Package
Junction
Temperature
Tj (C)
USB OTG x2
eMMC 4.5/SD 3.0 x2
Ethernet x2
UART x8
I2C x4
FlexSPI x2
CAN x2
FlexCAN (with Flexible
Data-Rate supported)
FlexIO x3
127 GPIOs (124 tightly
coupled)
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management controller
10 x 10 mm, 0.65 mm
pitch, 196-pin MAPBGA
0 to +95
eMMC 4.5/SD 3.0 x2
Ethernet x2
UART x8
I2C x4
FlexSPI x2
CAN x2
FlexCAN (with Flexible
Data-Rate supported)
FlexIO x3
127 GPIOs (124 tightly
coupled)
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management controller
10 x 10 mm, 0.65 mm
pitch, 196-pin MAPBGA
0 to +95
Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be
identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The
primary characteristic which describes which data sheet applies to a specific part is the temperature grade
(junction) field.
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9
i.MX RT1060 Introduction
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMXRT or
contact an NXP representative for details.
M
IMX
XX
@
##
%
+
VV
$
A
Qualification Level
M
Silicon Rev
A
Prototype Samples
P
A0
A
Mass Production
M
A1
B
Special
S
Core Frequency
$
400 MHz
4
500 MHz
5
600 MHz
6
Part # series
XX
i.MX RT
RT
Family
@
First Generation RT family
1
Reserved
Package Type
2-8
VV
225MAPBGA, 13 x 13 mm, 0.8 mm pitch
VN
Sub-Family
##
196MAPBGA, 12 x 12 mm, 0.8 mm pitch
VJ
RT101x
01
196MAPBGA, 10 x 10 mm, 0.65 mm pitch
VL
RT102x
02
169MAPBGA, 11 x 11 mm, 0.8 mm pitch
JM
RT104x
04
169MAPBGA, 9 x 9 mm, 0.65 mm pitch
FP
144LQFP, 20 x 20 mm, 0.5 mm pitch
AG
RT105x
05
RT106x
06
Tie
%
Standard Feature
1
Full Feature
2
4MB Flash SIP
4
100LQFP, 14 x 14 mm, 0.5 mm pitch
AF
80LQFP, 12 x 12 mm, 0.5 mm pitch
AE
Enhanced Feature
5
Temperature (Tj)
+
Far Field AFE
A
Consumer: 0 to + 95 °C
D
Facial Recognition
F
Industrial: -40 to +105 °C
C
Extended Industrial: -40 to +125 eC
X
$OH[DIRU,R7
Local Voice Control (text input models)
3
S
Figure 1. Part number nomenclature—i.MX RT10XX family
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NXP Semiconductors
Architectural Overview
2
Architectural Overview
The following subsections provide an architectural overview of the i.MX RT1060 processor system.
2.1
Block diagram
Figure 2 shows the functional modules in the i.MX RT1060 processor system1.
System Control
CPU Platform
Connectivity
Secure JTAG
eMMC 4.5 / SD 3.0 x2
Arm Cortex-M7
PLL / OSC
32 KB D-cache
32 KB I-cache
UART x8
RTC and Reset
FPU
NVIC
MPU
8 x 8 Keypad
Enhanced DMA
Up to 512 KB TCM
IOMUX
GP Timer x6
High-speed GPIO
GPIO 6/7/8/9
I2C x4
FLEXIO3
SPI x4
Quadrature ENC x4
QuadTimer
(4-Channel) x4
FlexPWM
(8-Channel) x4
Watch Dog x4
Internal Memory
Multimedia
GPIO
8 / 16 / 24-bit Parallel CSI
I2S / SAI x3
24-bit Parallel LCD
PXP
2D Graphics Acceleration
Resize, CSC, Overlay, Rotation
512 KB OCRAM
shared with TCM
96 KB ROM
S/PDIF Tx / Rx
FlexCAN x2
USB 2.0 OTG with PHY x2
External Memory
FlexSPI x2 (dual-channel QuadSPI
NAND and NOR, Octal Flash, and RAM)
10 / 100 ENET
with IEEE 1588 x1
Power Management
DCDC
LDO
Temp Monitor
External Memory Controller
8-bit / 16-bit SDRAM
Parallel NOR FLASH
NAND FLASH
PSRAM
ADC
ADC x2 (20-Channel)
ACMP x4
Security
Ciphers and RNG
Secure RTC
eFuse
HAB
.
Figure 2. i.MX RT1060 system block diagram
1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.
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Modules List
3
Modules List
The i.MX RT1060 processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX RT1060 modules list
Block Mnemonic
Block Name
Subsystem
Brief Description
ACMP1
ACMP2
ACMP3
ACMP4
Analog Comparator
Analog
The comparator (CMP) provides a circuit for comparing
two analog input voltages. The comparator circuit is
designed to operate across the full range of the supply
voltage (rail-to-rail operation).
ADC1
ADC2
Analog to Digital
Converter
Analog
The ADC is a 12-bit general purpose analog to digital
converter.
AOI
And-Or-Inverter
Cross Trigger
The AOI provides a universal boolean function
generator using a four team sum of products expression
with each product term containing true or complement
values of the four selected inputs (A, B, C, D).
Arm
Arm Platform
Arm
The Arm Core Platform includes one Cortex-M7 core. It
includes associated sub-blocks, such as Nested
Vectored Interrupt Controller (NVIC), Floating-Point
Unit (FPU), Memory Protection Unit (MPU), and
CoreSight debug modules.
BEE
Bus Encryption Engine
Security
CCM
GPC
SRC
On-The-Fly FlexSPI Flash Decryption
Clock Control Module, Clocks, Resets, and These modules are responsible for clock and reset
General Power
Power Control
distribution in the system, and also for the system
Controller, System Reset
power management.
Controller
CSI
Parallel CSI
Multimedia
Peripherals
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
CSU
Central Security Unit
Security
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
RT1060 platform.
DAP
Debug Access Port
System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-M7
Core Platform.
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Modules List
Table 2. i.MX RT1060 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
DCDC
DCDC Converter
Analog
The DCDC module is used for generating power supply
for core logic. Main features are:
• Adjustable high efficiency regulator
• Supports 3.3 V input voltage
• Supports nominal run and low power standby modes
• Supports at 0.9 ~ 1.3 V output in run mode
• Supports at 0.9 ~ 1.0 V output in standby mode
• Over current and over voltage detection
eDMA
enhanced Direct Memory
Access
System Control
Peripherals
There is an enhanced DMA (eDMA) engine and two
DMA_MUX.
• The eDMA is a 32 channel DMA engine, which is
capable of performing complex data transfers with
minimal intervention from a host processor.
• The DMA_MUX is capable of multiplexing up to 128
DMA request sources to the 32 DMA channels of
eDMA.
ENC
Quadrature
Encoder/Decoder
Timer Peripherals
The enhanced quadrature encoder/decoder module
provides interfacing capability to position/speed
sensors. There are five input signals: PHASEA,
PHASEB, INDEX, TRIGGER, and HOME. This module
is used to decode shaft position, revolution count, and
speed.
ENET
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
EWM
External Watchdog
Monitor
Timer Peripherals
The EWM modules is designed to monitor external
circuits, as well as the software flow. This provides a
back-up mechanism to the internal WDOG that can
reset the system. The EWM differs from the internal
WDOG in that it does not reset the system. The EWM,
if allowed to time-out, provides an independent trigger
pin that when asserted resets or places an external
circuit into a safe mode.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
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Modules List
Table 2. i.MX RT1060 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
FLEXCAN (FD)
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN with Flexible Data-Rate protocol and the CAN
2.0 version B protocol supports both standard and
extended message frames, both of them have long
payloads up to 64 bytes transferred at faster rates up to
8 Mbps.
FlexIO1
FlexIO2
Flexible Input/output
Connectivity and
Communications
The FlexIO is capable of supporting a wide range of
protocols including, but not limited to: UART, I2C, SPI,
I2S, camera interface, display interface, PWM
waveform generation, etc. The module can remain
functional when the chip is in a low power mode
provided the clock it is using remain active.
FlexPWM1
FlexPWM2
FlexPWM3
FlexPWM4
Pulse Width Modulation
Timer Peripherals
The pulse-width modulator (PWM) contains four PWM
sub-modules, each of which is set up to control a single
half-bridge power stage. Fault channel support is
provided. The PWM module can generate various
switching patterns, including highly sophisticated
waveforms.
FlexRAM
RAM
Memories
The i.MX RT1060 has 1 MB of on-chip RAM which
could be flexible allocated to I-TCM, D-TCM, and
on-chip RAM (OCRAM) in a 32 KB granularity. The
FlexRAM is the manager of the on-chip RAM array.
Major functions of this blocks are: interfacing to I-TCM
and D-TCM of Arm core and OCRAM controller;
dynamic RAM arrays allocation for I-TCM, D-TCM, and
OCRAM.
FlexSPI1
FlexSPI2
Quad Serial Peripheral
Interface
Connectivity and
Communications
FlexSPI acts as an interface to one or two external
serial flash devices, each with up to four bidirectional
data lines.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
GPT1
GPT2
General Purpose Timer
Timer Peripherals
Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
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Modules List
Table 2. i.MX RT1060 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
KPP
Keypad Port
Human Machine
Interfaces
LCDIF
LCD interface
Multimedia
Peripherals
The LCDIF is a general purpose display controller used
to drive a wide range of display devices varying in size
and capabilities. The LCDIF is designed to support
dumb (synchronous 24-bit Parallel RGB interface) and
smart (asynchronous parallel MPU interface) LCD
devices.
LPI2C1
LPI2C2
LPI2C3
LPI2C4
Low Power
Inter-integrated Circuit
Connectivity and
Communications
The LPI2C is a low power Inter-Integrated Circuit (I2C)
module that supports an efficient interface to an I2C bus
as a master.
The I2C provides a method of communication between
a number of external devices. More detailed
information, see Section 4.9.2, LPI2C module timing
parameters.
LPSPI1
LPSPI2
LPSPI3
LPSPI4
Low Power Serial
Peripheral Interface
Connectivity and
Communications
The LPSPI is a low power Serial Peripheral Interface
(SPI) module that support an efficient interface to an
SPI bus as a master and/or a slave.
• It can continue operating while the chip is in stop
modes, if an appropriate clock is available
• Designed for low CPU overhead, with DMA off
loading of FIFO register access
LPUART1
LPUART2
LPUART3
LPUART4
LPUART5
LPUART6
LPUART7
LPUART8
UART Interface
Connectivity
Peripherals
Each of the UART modules support the following serial
data transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 20 Mbps.
MQS
Medium Quality Sound
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
PXP
Pixel Processing Pipeline
Multimedia
Peripherals
A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending, and
rotation. The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications.
The KPP is a 16-bit peripheral that can be used as a
keypad matrix interface or as general purpose
input/output (I/O). It supports 8 x 8 external key pad
matrix. Main features are:
• Multiple-key detection
• Long key-press detection
• Standby key-press detection
• Supports a 2-point and 3-point contact key matrix
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Modules List
Table 2. i.MX RT1060 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
QuadTimer1
QuadTimer2
QuadTimer3
QuadTimer4
QuadTimer
Timer Peripherals
The quad-timer provides four time channels with a
variety of controls affecting both individual and
multi-channel features.Specific features include
up/down count, cascading of counters, programmable
module, count once/repeated, counter preload,
compare registers with preload, shared use of input
signals, prescaler controls, independent
capture/compare, fault input control, programmable
input filters, and multi-channel synchronization.
ROMCP
ROM Controller with
Patch
Memories and
The ROMCP acts as an interface between the Arm
Memory Controllers advanced high-performance bus and the ROM. The
on-chip ROM is only used by the Cortex-M7 core during
boot up. Size of the ROM is 96 KB.
RTC OSC
Real Time Clock
Oscillator
Clock Sources and The RTC OSC provides the clock source for the
Control
Real-Time Clock module. The RTC OSC module, in
conjunction with an external crystal, generates a 32.768
kHz reference clock for the RTC.
RTWDOG
Watch Dog
Timer Peripherals
The RTWDG module is a high reliability independent
timer that is available for system to use. It provides a
safety feature to ensure software is executing as
planned and the CPU is not stuck in an infinite loop or
executing unintended code. If the WDOG module is not
serviced (refreshed) within a certain period, it resets the
MCU. Windowed refresh mode is supported as well.
SAI1
SAI2
SAI3
Synchronous Audio
Interface
Multimedia
Peripherals
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
SA-TRNG
Standalone True Random
Number Generator
Security
The SA-TRNG is hardware accelerator that generates
a 512-bit entropy as needed by an entropy consuming
module or by other post processing functions.
SEMC
Smart External Memory
Controller
Memory and
Memory Controller
The SEMC is a multi-standard memory controller
optimized for both high-performance and low pin-count.
It can support multiple external memories in the same
application with shared address and data pins. The
interface supported includes SDRAM, NOR Flash,
SRAM, and NAND Flash, as well as 8080 display
interface.
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Modules List
Table 2. i.MX RT1060 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SJC
System JTAG Controller
System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX
RT1060 processors use JTAG port for production,
testing, and system debugging. In addition, the SJC
provides BSR (Boundary Scan Register) standard
support, which complies with IEEE 1149.1 and IEEE
1149.6 standards.
The JTAG port is accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX RT1060 SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS
Secure Non-Volatile
Storage
Security
SPDIF
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
Temp Monitor
Temperature Monitor
Analog
TSC
Touch Screen
Human Machine
Interfaces
USBO2
Universal Serial Bus 2.0
Connectivity
Peripherals
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, Violation, and reporting.
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
The temperature sensor implements a temperature
sensor/conversion function based on a
temperature-dependent voltage to time conversion.
With touch controller to support 4-wire and 5-wire
resistive touch panel.
USBO2 (USB OTG1 and USB OTG2) contains:
• Two high-speed OTG 2.0 modules with integrated
HS USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
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NXP Semiconductors
17
Modules List
Table 2. i.MX RT1060 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
Peripherals
i.MX RT1060 specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia
Card System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC
MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
WDOG1
WDOG2
Watch Dog
Timer Peripherals
The watchdog (WDOG) Timer supports two comparison
points during each counting period. Each of the
comparison points is configurable to evoke an interrupt
to the Arm core, and a second point evokes an external
event on the WDOG line.
XBAR
Cross BAR
Cross Trigger
Each crossbar switch is an array of muxes with shared
inputs. Each mux output provides one output of the
crossbar. The number of inputs and the number of
muxes/outputs are user configurable and registers are
provided to select which of the shared inputs are routed
to each output.
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NXP Semiconductors
Modules List
3.1
Special signal considerations
Table 3 lists special signal considerations for the i.MX RT1060 processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, Package information and contact
assignments.” Signal descriptions are provided in the i.MX RT1060 Reference Manual
(IMXRT1060RM).
Table 3. Special signal considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
One general purpose differential high speed clock Input/output (LVDS I/O) is provided.
It can be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals.
See the i.MX RT1060 Reference Manual (IMXRT1060RM) for details on the respective clock trees.
Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding
CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of
the CLK1_N/P pairs may remain unconnected.
DCDC_PSWITCH
PAD is in DCDC_IN domain and connected the ground to bypass DCDC.
To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must
remain unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be
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