NXP Semiconductors
Data sheet: Technical data
Document Number: MM912_637D1
Rev. 6.0, 6/2021
Intelligent integrated precision
battery sensor
MM912_637
The MM912I637 (96 kB) and MM912J637 (128 kB) are fully integrated LIN
Battery monitoring devices, based on NXP SMARTMOS and S12 MCU
Technology.
Battery Monitoring System
The device supports precise current measurement via an external shunt resistor,
and precise battery voltage measurement via a series resistor directly at the
battery plus pole. The integrated temperature sensor combined in the close
proximity to the battery, allows battery temperature measurement.
The integrated LIN 2.1 interface makes the sensor feedback available on the LIN
Bus.
Features
• Battery voltage measurement
• Battery current measurement in up to 8 ranges
• On chip temperature measurement
• Normal and two low-power modes
• Current threshold detection and current averaging in standby => wake-up
from low-power mode
• Triggered wake-up from LIN and periodic wake-up
• Signal low pass filtering (current, voltage)
• PGA (programmable low-noise gain amplifier) with automatic gain control
• Accurate internal oscillator (an external quartz oscillator may be used for
extended accuracy)
• Communication via a LIN 2.1, LIN2.0 bus interface
• S12 microcontroller with 128 kByte flash, 6.0 kByte RAM, 4.0 kByte data flash
• Background debug module
• External temperature sensor option (TSUP, VTEMP)
• Optional 2nd external voltage sense input (VOPT)
• 4 x 5.0 V GPIO including one wake-up capable high voltage input (PTB3/L0)
• 8 x MCU general purpose I/O including SPI functionality
• Industry standard EMC compliance
EP SUFFIX (WF-TYPE)
SOT619-16
48-PIN QFN
EP SUFFIX (WF-TYPE)
SOT619-25(D)
48-PIN QFN
Applications
• 12 V Lead-acid battery monitoring
MM912_637
VDDA
ADC Supply
2.5 V Supply
5.0 V Supply
Digital Ground
Reset
5.0 V Digital I/O
Debug and External
Oscillator
MCU Test
LIN
AGND
ADCGND
VDDL
VDDH
VDDD2D
VDDX
VDDRX
DGND
VSSD2D
VSSRX
RESET
RESET_A
PA0/MISO
PA1/MOSI
PA2/SCK
PA3/SS
PA4
PA5
PA6
PA7
BKGD/MODC
PE0/EXTAL
PE1/XTAL
TEST
(optional)
LGND
Internal
Temp
Sense
Module
TSUP
VTEMP
Battery
Positive Pole
+
VOPT
VSENSE
VSUP
Battery
Negative Pole
_
ISENSEL
Shunt
ISENSEH
Voltage sense Module
Power Supply
Current Sense Module
-5.0 V GPI/O shared
with TIMER, SCI and LIN
-PTB3 high voltage
WAKE capable
PTB1
PTB2
PTB3/L0
4
TCLK
TEST_A
Figure 1. Simplified application diagram
© NXP B.V. 2021. All rights reserved.
Optional Temp Sense
Input and Supply
Chassis
Ground
PTB0
GNDSUB
LIN Interface
Analog Test
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table of Contents
1
2
3
4
5
6
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 MM912_637 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Recommended external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Pin structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Thermal protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.8 Electromagnetic compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 MM912_637 - analog die overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3 Analog die - power, clock and resets - PCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.4 Interrupt module - IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Current measurement - ISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.6 Voltage measurement - VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.7 Temperature measurement - TSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.8 Channel acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.9 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.10 Basic timer module - TIM (TIM16B4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.11 General purpose I/O - GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.12 LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.13 Serial communication interface (S08SCIV4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.14 Life time counter (LTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
4.15 Die to die interface - target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
4.16 Embedded microcontroller - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
4.17 MCU - port integration module (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
4.18 MCU - interrupt module (S12S9S12I128PIMV1V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
4.19 Memory map control (S12PMMCV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
4.20 MCU - debug module (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
4.21 MCU - security (S12XS9S12I128PIMV1V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
4.22 Background debug module (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
4.23 S12 clock, reset, and power management unit (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
4.24 MCU - serial peripheral interface (S129S12I128PIMV1V5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
4.25 128 kByte flash module (S12FTMRC128K1V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
4.26 MCU - die-to-die initiator (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
MM912_637 - trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.2 IFR trimming content and location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.3 Memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
6.1 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
MM912_637D1
Data sheet: Technical data
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 6/2021
© NXP B.V. 2021. All rights reserved.
2/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
1
Ordering information
Table 1. Ordering information
Package
Type number
Name
MM912I637TM2EP
MM912J637TM2EP
MM912I637TV1EP
MM912J637TV1EP
HVQFN48
MM912I637AM2EP
MM912J637AM2EP
MM912I637AV1EP
MM912J637AV1EP
1
Description
Version
plastic, thermal enhanced, very thin quad flatpack, no leads, 48 terminals,
0.5 mm pitch, 0.15 dimple, wettable flank, 7 mm x 7 mm x 0.9 mm body
SOT619-25(D)
plastic, thermal enhanced, very thin quad flatpack, no leads, 48 terminals,
0.5 mm pitch, 0.1 dimple, wettable flank, 7 mm x 7 mm x 0.85 mm body
SOT619-25(D)
plastic, thermal enhanced, very thin quad flatpack, no leads, 48 terminals,
0.5 mm pitch, 0.15 dimple, wettable flank, 7 mm x 7 mm x 0.9 mm body
SOT619-161
plastic, thermal enhanced, very thin quad flatpack, no leads, 48 terminals,
0.5 mm pitch, 0.1 dimple, wettable flank, 7 mm x 7 mm x 0.85 mm body
SOT619-161
Not recommended for new design
Table 2. Ordering options
Device (1)
Temperature range (TA)
Flash (kB)
MM912I637TM2EP
Maximum input
voltage
Analog option
96
MM912J637TM2EP
128
–40 °C to 125 °C
MM912I637AM2EP(2)
2
96
MM912J637AM2EP(2)
128
MM912I637TV1EP
96
MM912J637TV1EP
42 V
128
–40 °C to 105 °C
MM912I637AV1EP(2)
1
96
MM912J637AV1EP(2)
128
Notes
1. To order parts in tape & reel, add the R2 suffix to the part number.
2. Not recommended for new design.
Table 3. Analog options
Feature
Analog option 1
Analog option 2
Not Characterized or Tested
Fully Characterized and Tested
External Wake-up (PTB3/L0)
No
Yes
External Temperature Sensor Option (VTEMP)
No
Yes
Optional 2nd External Voltage Sense Input (VOPT)
No
Yes
Cranking Mode
MM912_637D1
Data sheet: Technical data
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 6/2021
© NXP B.V. 2021. All rights reserved.
3/396
MM912_637D1
Data sheet: Technical data
Rev. 6.0 — 6/2021
ALU
All information provided in this document is subject to legal disclaimers.
MISO
MOSI
SCK
SS
RAM 6k Byte
SPI
Dataflash 4k Bytes with ECC
Flash 128k Bytes with ECC
CPU
Register
M68HCS12 CPU
Reset Generation and
Test Entry
VREG
1.8V Core
2.7V Flash
Internal Bus
PA0
PA1
PA2
PA3
PA4
PA5
Amplitude Controlled
Low Power Pierce Osc.
BKGD/MODC
PLL with Freq. Modulation option
OSC Clock Monitor
PTE
[1:0]
RESET
TEST
PTE1 / XTAL
PTE0 / EXTAL
D2DI
PC1
PD0
PD4
PD1
PD5
PD2
PD6
PD3
PD7
PC0
MCU Die
Debug Module
include 64 byte Trace Buffer RAM
Interrupt Module
Periodic Interrupt
COP Watchdog
Single-Wire Background Debug
Module
D2DCLK
D2DINT
D2DDAT0
D2DDAT4
D2DDAT1
D2DDAT5
D2DDAT2
D2DDAT6
D2DDAT3
D2DDAT7
Test
Interface
TEST_A
Analog Die
RESET_A
BIAS
Cascaded
Voltage Regulators
VDDH = 2.5V
(D2D Buffer)
VDDL = 2.5V
(Internal Digital)
VDDX = 5V
(MCU Core)
Die To Die
Interface
Interrupt
Control Module
Trimming /
Calibration
Reset
Control Module
TCLK
PTA
DDRA
PA6
16 Bit
ΣΔ - ADC
16 Bit
ΣΔ - ADC
LIN
Physical
Layer
SCI
4 Channel Timer
Wake Up Control Module
(with Current Threshold and
Current Averaging)
Internal Chip Temp Sense
with optional external input
Current Sense Module
(PGA with auto Gain Control)
Low Pass Filter
And
Control
VBAT / VOPT Sense Module
Temp Sense Supply
GPIO
16 Bit
ΣΔ - ADC
ADC
Regulator
PTB0
PTB1
PTB2
PTB3 (L0)
VTEMP
ISENSEL
ISENSEH
ADCGND
AGND
VDDA
VSENSE
VOPT
TSUP
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
GNDSUB
GNDSUB
GNDSUB
GNDSUB
LGND
LIN
Internal Bus
VSUP
DGND
VDDL
VDDX
VDDH
VDDD2D
VSSD2D
VDDRX
VSSRX
PA7
Figure 2. Sample block diagram
© NXP B.V. 2021. All rights reserved.
4/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
BKGD/MODC
RESET
RESET_A
DGND
TEST_A
VDDL
GNDSUB
TCLK
PTB0
PTB1
PTB2
Pin assignment
PA7
2
48
47
46
45
44
43
42
41
40
39
38
37
PA6
1
36
PTB3 / L0
PTE0/EXTAL
2
35
VOPT
PTE1/XTAL
3
34
VSENSE
TEST
4
33
ADCGND
PA5
5
32
ISENSEH
PA4
6
31
ISENSEL
EP
PA3/SS
7
30
GNDSUB
PA2/SCK
8
29
TSUP
PA1/MOSI
9
28
VTEMP
PA0/MISO
10
27
AGND
VSSRX
11
26
VDDA
VDDRX
12
25
NC
13
14
15
16
17
18
19
20
21
22
23
24
VSSD2D
VDDD2D
NC
GNDSUB
VDDX
DGND
VDDH
GNDSUB
VSUP
LIN
LGND
NC (VFUSE)
Figure 3. MM912_637 pin connections
2.1
MM912_637 pin description
The following table gives a brief description of all available pins on the MM912_637 device. Refer to the highlighted chapter for detailed
information
Table 4. MM912_637 pin description (continued)
Pin #
Pin Name
1
PA6
2
PE0/EXTAL
3
PE1/XTAL
4
TEST
MM912_637D1
Data sheet: Technical data
Formal Name
Description
MCU PA6
General purpose port A input or output pin 6. See Section 4.17, “MCU - port integration
module (9S12I128PIMV1)".
MCU Oscillator
EXTAL in one of the optional crystal/resonator drivers and external clock pins, and the PE0
port may be used as a general purpose I/O. On reset, all the device clocks are derived from
the internal reference clock. See Section 4.23, “S12 clock, reset, and power management
unit (9S12I128PIMV1)".
MCU Oscillator
XTAL is one of the optional crystal/resonator drivers and external clock pins, and the PE1
port may be used as a general purpose I/O. On reset all the device clocks are derived from
the internal reference clock. See Section 4.23, “S12 clock, reset, and power management
unit (9S12I128PIMV1)".
MCU Test
This input only pin is reserved for test. This pin has a pull-down device. The TEST pin must
be tied to VSSRX in user mode.
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 6/2021
© NXP B.V. 2021. All rights reserved.
5/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 4. MM912_637 pin description (continued)
Pin #
Pin Name
5
PA5
MCU PA5
General purpose port A input or output pin 5. See Section 4.17, “MCU - port integration
module (9S12I128PIMV1)".
6
PA4
MCU PA4
General purpose port A input or output pin 4. See Section 4.17, “MCU - port integration
module (9S12I128PIMV1)".
7
PA3
MCU PA3 / SS
General purpose port A input or output pin 3, shared with the SS signal of the integrated
SPI interface. See Section 4.17, “MCU - port integration module (9S12I128PIMV1)".
8
PA2
MCU PA2 / SCK
General purpose port A input or output pin 2, shared with the SCLK signal of the integrated
SPI interface. See Section 4.17, “MCU - port integration module (9S12I128PIMV1)".
9
PA1
MCU PA1 / MOSI
General purpose port A input or output pin 1, shared with the MOSI signal of the integrated
SPI interface. See Section 4.17, “MCU - port integration module (9S12I128PIMV1)".
10
PA0
MCU PA0 / MISO
General purpose port A input or output pin 0, shared with the MISO signal of the integrated
SPI interface. See Section 4.17, “MCU - port integration module (9S12I128PIMV1)".
11
VSSRX
MCU 5.0 V Ground
External ground for the MCU - VDDRX return path.
12
VDDRX
MCU 5.0 V Supply
5.0 V MCU power supply. MCU core- (internal 1.8 V regulator) and flash (internal 2.7 V
regulator) supply. This pin must be connected to VDDX.
13
VSSD2D
MCU 2.5 V Ground
External ground for the MCU - VDDD2D return path.
14
VDDD2D
MCU 2.5 V Supply
2.5 V MCU power supply. Die to die buffer supply. This pin must be connected to VDDH.
15
NC
Not connected
This pin must be grounded in the application.
16
GNDSUB
Substrate Ground
Substrate ground connection to improve EMC behavior.
17
VDDX
Voltage Regulator Output
5.0 V
5.0 V main voltage regulator output pin. An external capacitor (CVDDX) is needed. See
Section 4.3, “Analog die - power, clock and resets - PCR".
18
DGND
Digital Ground
This pin is the device digital ground connection. See Section 4.3, “Analog die - power, clock
and resets - PCR".
19
VDDH
Voltage Regulator Output
2.5 V
2.5 V high power main voltage regulator output pin to be connected with the VDDD2D MCU
pin. An external capacitor (CVDDH) is needed. See Section 4.3, “Analog die - power, clock
and resets - PCR".
20
GNDSUB
Substrate Ground
Substrate ground connection to improve EMC behavior.
21
VSUP
Power Supply
This pin is the device power supply pin. A reverse battery protection diode is required. See
Section 4.3, “Analog die - power, clock and resets - PCR".
22
LIN
LIN Bus I/O
This pin represents the single-wire bus transmitter and receiver. See Section 4.12, “LIN".
23
LGND
LIN Ground Pin
This pin is the device LIN ground connection. See Section 4.3, “Analog die - power, clock
and resets - PCR".
24
NC
Not connected (reserved)
This pin must be grounded in the application.
25
NC
Not connected
This pin must be grounded in the application.
26
VDDA
Analog Voltage Regulator
Output
Low power analog voltage regulator output pin, permanently supplies the analog front end.
An external capacitor (CVDDA) is needed. See Section 4.3, “Analog die - power, clock and
resets - PCR".
27
AGND
Analog Ground
This pin is the device analog voltage regulator and LP oscillator ground connection. See
Section 4.3, “Analog die - power, clock and resets - PCR".
28
VTEMP
Temperature Sensor Input
External temperature sensor input. See Section 4.7, “Temperature measurement TSENSE".
29
TSUP
Temperature Sensor Supply
Output
Supply for the external temperature sensor. TSUP frequency compensation option to allow
capacitor CTSUP. See Section 4.7, “Temperature measurement - TSENSE".
30
GNDSUB
Substrate Ground
Substrate ground connection to improve EMC behavior.
31
ISENSEL
Current Sense L
Current sense input “Low”. This pin is used in combination with ISENSEH to measure the
voltage drop across a shunt resistor. See Section 4.5, “Current measurement - ISENSE".
MM912_637D1
Data sheet: Technical data
Formal Name
Description
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Table 4. MM912_637 pin description (continued)
Pin #
Pin Name
32
ISENSEH
Current Sense H
Current sense input “high”. This pin is used in combination with ISENSEL to measure the
voltage drop across a shunt resistor. See Section 4.5, “Current measurement - ISENSE".
33
ADCGND
Analog Digital Converter
Ground
Analog digital converter ground connection. See Section 4.3, “Analog die - power, clock
and resets - PCR".
Voltage Sense
Precision battery voltage measurement input. This pin can be connected directly to the
battery line for voltage measurements. The voltage preset at this input is scaled down by
an internal voltage divider. The pin is self protected against reverse battery connections.
An external resistor (RVSENSE) is needed for protection. See Section 4.6, “Voltage
measurement - VSENSE".
Optional Voltage Sense
Optional voltage measurement input. See Section 4.6, “Voltage measurement - VSENSE".
General Purpose Input 3 High Voltage Input 0
This is the high voltage general purpose input pin 3, based on VDDX with the following
shared functions:
• Internal clamping structure to operate as a high voltage input (L0). When used as high
voltage input, a series resistor (RL0) and capacitor to GND (CL0) must be used to protect
against automotive transients, when used to connect outside the PCB.
• 5.0 V (VDDX) digital port input
• Selectable internal pull-down resistor
• Selectable wake-up input during low power mode.
• Selectable timer channel input
• Selectable connection to the LIN / SCI (Input only)
See Section 4.11, “General purpose I/O - GPIO".
General Purpose I/O 2
This is the general purpose I/O pin 2 based on VDDX with the following shared functions:
• Bidirectional 5.0 V (VDDX) digital port I/O
• Selectable internal pull-up resistor
• Selectable timer channel input/output
• Selectable connection to the LIN / SCI
See Section 4.11, “General purpose I/O - GPIO".
General Purpose I/O 1
This is the general purpose I/O pin 1, based on VDDX with the following shared functions:
• Bidirectional 5.0 V (VDDX) digital port I/O
• Selectable internal pull-up resistor
• Selectable timer channel input/output
• Selectable connection to the LIN / SCI
See Section 4.11, “General purpose I/O - GPIO".
34
VSENSE
35
VOPT
36
37
38
PTB3 / L0
PTB2
PTB1
Formal Name
Description
39
PTB0
General Purpose I/O 0
This is the general purpose I/O pin 0 based on VDDX with the following shared functions:
• Bidirectional 5.0 V (VDDX) digital port I/O
• Selectable internal pull-up resistor
• Selectable timer channel input/output
• Selectable connection to the LIN / SCI
See Section 4.11, “General purpose I/O - GPIO".
40
TCLK
Test Clock Input
Test mode clock input pin for Test mode only. This pin must be grounded in user mode.
41
GNDSUB
Substrate Ground
Substrate ground connection to improve EMC behavior.
42
VDDL
Low Power Voltage
Regulator Output
2.5 V low power voltage regulator output pin. See Section 4.3, “Analog die - power, clock
and resets - PCR".
43
TEST_A
Test Mode
Analog die Test mode pin for Test mode only. This pin must be grounded in user mode.
44
DGND
Digital Ground
This pin is the device digital ground connection. See Section 4.3, “Analog die - power, clock
and resets - PCR".
45
RESET_A
Reset I/O
Reset output pin of the analog die in Normal mode. Bidirectional reset I/O of the analog die
in Stop mode. Active low signal with internal pull-up to VDDX. This pin must be connected
to RESET. See Section 4.3, “Analog die - power, clock and resets - PCR".
MM912_637D1
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Table 4. MM912_637 pin description (continued)
Pin #
Pin Name
46
RESET
MCU Reset
Bidirectional reset I/O pin of the MCU die. Active low signal with internal pull-up to VDDRX.
This pin must be connected to RESETA. See Section 4.3, “Analog die - power, clock and
resets - PCR".
47
BKGD
MCU Background Debug
and Mode
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. It is used as an MCU operating mode select pin during reset. The state of
this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pull-up
device. See Section 4.20, “MCU - debug module (9S12I128PIMV1)".
48
PA7
MCU PA7
General purpose port A input or output pin 7. See Section 4.17, “MCU - port integration
module (9S12I128PIMV1)".
2.2
Formal Name
Description
Recommended external components
Figure 4 and Table 5 list the required / recommended / optional external components for the application.
Battery
Plus Pole
D1
RVOPT
RISENSEL
VSUP
VDDL
VDDD2D
VDDH
VDDRX
ISENSEL
CISENSEL
RSHUNT
CVBAT
VSENSE
VOPT
Battery
Minus Pole
RVSENSE
VDDX
CISENSEHL
RISENSEH
CVDDX
DGND
ISENSEH
RESET
Chassis
Ground
CVDDH
VSSD2D
CISENSEH
VSSRX
RESETA
VTEMP
GNDSUB
PTB3 / L0
GNDSUB
LGND
GNDSUB
CLIN
GNDSUB
LIN
Exposed Pad (EP)
RVTEMP
LIN
TSUP
VDDA
CVDDA
CTSUP
AGND
ADCGND
RL0
CL0
Note: Module GND connected to Battery Minus or Chassis Ground – based on configuration.
Figure 4. Required/recommended external components
Table 5. Required/recommended external components
Name
Description
Value
Connection
D1
Reverse Battery Diode
n.a.
VSUP-VBAT
CVBAT
Battery Blocking Capacitor
4.7 µF/100 nF
VSUP-GND
RVSENSE
VSENSE Current Limitation
2.2 k
VSENSE-VBAT
RVOPT
VOPT Current Limitation
2.2 k
VOPT-signal
RSHUNT
Current Shunt Resistor
100 µ
ISENSEH-ISENSEL
MM912_637D1
Data sheet: Technical data
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Comment
Ceramic
optional(3)
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Table 5. Required/recommended external components
Name
Description
Value
Connection
Comment
RISENSEL
EMC Resistor
500 max
select for best EMC performance
RISENSEH
EMC Resistor
500 max
select for best EMC performance
CISENSEL
EMC Capacitor
TBD
select for best EMC performance
CISENSEHL
EMC Capacitor
TBD
select for best EMC performance
CISENSEH
EMC Capacitor
TBD
select for best EMC performance
CVDDH
Blocking Capacitor
1.0 µF
VDDH-GND
CVDDX
Blocking Capacitor
220 nF
VDDX-GND
CVDDA
Blocking Capacitor
47 nF
VDDA-GND
CVDDL
Blocking Capacitor
n.a.
VDDL-GND
not required
CLIN
LIN Bus Filter
n.a.
LIN-LGND
not required
RL0
PTB3 / L0 Current Limitation
47 k
L0
CL0
PTB3 / L0 ESD Protection
47 nF
L0-GND
CTSUP
Blocking Capacitor
220 pF
TSUP-GND
not required(4)
RVTEMP
VTEMP Current Limitation
20 k
VTEMP-signal
optional(3)
Notes
3. Required if extended EMC protection is needed
4. If an external temperature sensor is used, EMC compliance may require the addition of CTSUP. In this case the ECAP bit must be set to ensure the
stability of the TSUP power supply circuit. See Section 4.7.1.2, “Block diagram".
2.3
Pin structure
Table 6 documents the individual pin characteristic.
Table 6. Pin type/structure
Pin #
Pin name
Alternative pin
function
Power supply
Structure
1
PA6
n.a.
VDDRX
n.a.
2
PE0
EXTAL
VDDRX
PUPEE / OSCPINS_EN
3
PE1
XTAL
VDDRX
PUPEE / OSCPINS_EN
4
TEST
n.a.
n.a.
n.a.
5
PA5
n.a.
VDDRX
n.a.
6
PA4
n.a.
VDDRX
n.a.
7
PA3
SS
VDDRX
n.a.
8
PA2
SCK
VDDRX
n.a.
9
PA1
MOSI
VDDRX
n.a.
10
PA0
MISO
VDDRX
n.a.
11
VSSRX
n.a.
12
VDDRX
n.a.
13
VSSD2D
n.a.
14
VDDD2D
n.a.
MM912_637D1
Data sheet: Technical data
GND
GND
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Table 6. Pin type/structure
Pin #
Pin name
Alternative pin
function
15
NC
n.a.
16
GNDSUB
n.a.
17
VDDX
n.a.
VDDX
18
DGND
n.a.
GND
B2B-Diode to GNDSUB
19
VDDH
n.a.
VDDH
Negative Clamp Diode, Dynamic ESD (transient protection)
20
GNDSUB
n.a.
GND
GNDSUB
21
VSUP
n.a.
VSUP
Negative Clamp Diode, >42 V ESD
22
LIN
n.a.
VSUP
No Negative Clamping Diode (-40 V), >42 V ESD
23
LGND
n.a.
GND
B2B-Diode to GNDSUB
24
NC
n.a.
n.a.
Negative Clamp Diode, >15 V ESD
25
NC
n.a.
n.a.
n.a.
26
VDDA
n.a.
VDDA
Negative Clamp Diode, Dynamic ESD (transient protection)
27
AGND
n.a.
GND
B2B-Diode to GNDSUB
28
VTEMP
VDDA
Negative Clamp Diode, >6.0 V ESD
29
TSUP
TSUP
Negative Clamp Diode, Dynamic ESD (transient protection)
30
GNDSUB
GND
GND
31
ISENSEL
n.a.
Negative Clamp Diode, 2nd Clamp Diode to VDDA
32
ISENSEH
n.a.
Negative Clamp Diode, 2nd Clamp Diode to VDDA
33
ADCGND
GND
B2B-Diode to GNDSUB
34
VSENSE
n.a.
No Negative Clamping Diode (-40 V), >42 V ESD
35
VOPT
n.a.
No Negative Clamping Diode (-40 V), >42 V ESD
36
PTB3 / L0
VDDRX
Negative Clamp Diode, >6.0 V ESD
37
PTB2
VDDRX
Negative Clamp, Dynamic 5.5 V ESD
38
PTB1
VDDRX
Negative Clamp, Dynamic 5.5 V ESD
39
PTB0
VDDRX
Negative Clamp, Dynamic 5.5 V ESD
40
TCLK
VDDRX
Negative Clamp, Dynamic 5.5 V ESD
41
GNDSUB
GND
GND
42
VDDL
VDDL
Negative Clamp Diode, Dynamic ESD (transient protection)
43
TEST_A
VDDRX
Negative Clamp, positive 10 V Clamp
44
DGND
GND
B2B-Diode to GNDSUB
45
RESET_A
VDDRX
Negative Clamp, positive 10 V Clamp
46
RESET
VDDRX
Pull-up
47
BKGD
VDDRX
BKPUE
48
PA7
VDDRX
n.a.
MM912_637D1
Data sheet: Technical data
MODC
Power supply
Structure
GND
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3
Electrical characteristics
3.1
General
This section contains electrical information for the microcontroller, as well as the MM912_637 analog die.
3.2
Absolute maximum ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside these maximums is not guaranteed. Stress
beyond these limits may affect the reliability, or cause permanent damage of the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that normal
precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate voltage level. All voltages are with respect to ground, unless otherwise
noted.
Table 7. Absolute maximum electrical ratings - analog die
Ratings
Symbol
Value
Unit
VVSUP
-0.3 to 42
V
VVSENSE
-16 to 42
V
VOPT pin voltage with 2.2 k serial resistor
VVOPT
-16 to 42
V
VTEMP pin voltage
VVTEMP
-0.3 to VDDA+0.25
V
ISENSEH and ISENSEL pin voltage
VISENSE
-0.5 to VDDA+0.25
V
ISENSEH and ISENSEL pin current
IISENSE
-1 to 1
mA
VBUS
-33 to 42
V
LIN pin current (internally limited)
IBUSLIM
on page 16
mA
L0 pin voltage with RPTB3
VPTB3
-0.3 to 42 max.
V
Input / Output pins PTB[0:2] voltage
VPTB0-2
-0.3 to VDDX+0.5
V
Pin voltage at VDDX
VDDX
-0.3 to 5.75
V
Pin voltage at VDDH
VDDH
-0.3 to 2.75
V
VDDH output current
IVDDH
internally limited
A
VDDX output current
IVDDX
internally limited
A
TCLK pin voltage
VTCLK
-0.3 to VDDX+0.5
V
VIN
-0.3 to VDDX+0.5
V
Symbol
Value
Unit
5.0 V supply voltage
VDDRX
-0.3 to 6.0
V
2.5 V supply voltage
VDDD2D
-0.3 to 3.6
V
VIN
-0.3 to 6.0
V
VIN
-0.3 to 2.16
V
I
-25 to 25
mA
VSUP pin voltage
VSENSE pin voltage with 2.2 k serial resistor
(5)
LIN pin voltage
RESET_A pin voltage
Notes
5. It has to be assured by the application circuit that these limits will not be exceeded, e.g. by ISO pulse 1.
Table 8. Maximum electrical ratings - MCU die (continued)
Ratings
Digital I/O input voltage (PTA0...7)
EXTAL, XTAL
Instantaneous maximum current single pin limit for all digital I/O
MM912_637D1
Data sheet: Technical data
pins(6)
D
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Table 8. Maximum electrical ratings - MCU die (continued)
Ratings
Symbol
Value
Unit
-25 to 25
mA
Symbol
Value
Unit
Storage temperature
TSTG
-55 to 150
C
Package thermal resistance (7)
RJA
25 typ.
C/W
Instantaneous maximum current single pin limit for EXTAL, XTAL
I
DL
Notes
6. All digital I/O pins are internally clamped to VSSRX and VDDRX.
Table 9. Maximum thermal ratings
Ratings
Notes
7. RJA value is derived using a JEDEC 2s2p test board
3.3
Operating conditions
This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted.
Table 10. Operating conditions (8)
Ratings
Symbol
Value
Unit
Functional operating supply voltage - Device is fully functional. All features are
operating.
VSUP
3.5 to 28
V
Extended range for RAM Content is guaranteed. Other device functionary is
limited. With cranking mode enabled (seeSection 4.3.3.4, “Low-voltage
operation - cranking mode device option").
VSUPL
2.5 to 3.5
V
VSENSE
0 to 28
V
Functional operating VOPT voltage
VOPT
0 to 28
V
External temperature sense input - VTEMP
VTEMP
0 to 1.25
V
VVSUP_LIN
7.0 to 18
V
VISENSE
-0.3 to 0.3
V
MCU 5.0 V supply voltage
VDDRX
3.13 to 5.5
V
MCU 2.5 V supply voltage
VDDD2D
2.25 to 3.6
V
MCU oscillator
fOSC
4.0 to 16
MHz
MCU bus frequency
fBUS
max. 32.768
MHz
TA
-40 to 125
C
Operating junction temperature - analog die
TJ_A
-40 to 150
C
Operating junction temperature - MCU die
TJ_M
-40 to 150
C
Functional operating VSENSE voltage (9)
LIN output voltage range
ISENSEH / ISENSEL terminal voltage
Operating ambient temperature
Notes
8. The parametric data are guaranteed while the pins are within Operating Conditions. Other conditions are presented at the top of the parametric tables
or noted into parameters.
9. Values VSENSE > 28 V are flagged in the VSENSE
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3.4
Supply currents
This section describes the current consumption characteristics of the device, as well as the conditions for the measurements.
3.4.1
Measurement conditions
All measurements are without output loads. The currents are measured in MCU special single chip mode, and the CPU code is executed
from RAM, unless otherwise noted.
For Run and Wait current measurements, PLL is on and the reference clock is the IRC1M, trimmed to 1.024 MHz. The bus frequency is
32.768 MHz and the CPU frequency is 65.536 MHz. Table 11 and Table 12 show the configuration of the CPMU module for Run, Wait,
and Stop current measurements. Table 13 shows the configuration of the peripherals for run current measurements
Table 11. CPUM configuration for run/wait and full stop current measurement
CPMU register
Bit settings/conditions
CPMUSYNR
VCOFRQ[1:0]=01,SYNDIV[5:0] = 32.768 MHz
CPMUPOSTDIV
POSTDIV[4:0]=0,
CPMUCLKS
PLLSEL=1
CPMUOSC
OSCE=0, Reference clock for PLL is fREF=fIRC1M trimmed to 1.024 MHz
Table 12. CPMU configuration for pseudo stop current measurements
CPMU register
Bit settings/conditions
CPMUCLKS
PLLSEL=0, PSTP=1, PRE=PCE=RTIOSCSEL=COPOSCSEL=1
CPMUOSC
OSCE=1, External square wave on EXTAL fEXTAL=16 MHz, VIH= 1.8 V, VIL=0 V
CPMURTI
RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111;
CPMUCOP
WCOP=1, CR[2:0]=111
Table 13. MCU peripheral configurations for run supply current measurements
Peripheral
Configuration
SPI
configured to master mode, continuously transmit data (0x55 or 0xAA) at 4.0 Mbit/s
D2DI
continuously read data
COP
COP Watchdog Rate 224
RTI
enabled, RTI Control Register (RTICTL) set to $FF
DBG
The module is disabled.
Table 14. Analog die configurations for normal mode supply current measurements
Peripheral
Configuration
D2D
maximum frequency (32.768 MHz)
LIN
enabled, 50% dominant, 50% recessive
TIMER
enabled, all channels active in output compare mode with minimum timeout
LTC
enabled, maximum timeout
SCI
continuously transmitting data (0x55 or 0xAA) with 19.2 kBit/s
Acquisition Channels
current/voltage: highest sampling rate (8.0 kHz), LPF enabled, chopper and compensation enabled, automatic gain
adjustment enabled temperature: internal temperature measurement enabled, 1.0 kHz sampling rate
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Table 15. Supply currents(10)
Ratings
Symbol
Min.
Typ.(12)
Max.
Unit
25
mA
MM912_637 combined consumption
Normal mode current both dice
IRUN
Stop Mode current measured at VSUP
Continuous base current (12)
-40 °C iSTOP_S
85 °C (11)
125 °C
Pseudo Stop Current, RTI and COP enabled (12)
-40 °C iSTOP_S
85 °C (11)
125 °C
Stop Current during Cranking Mode
-40 °C iSTOP_S
85 °C (11)
125 °C
Current adder during current trigger event - (typ. 10 ms duration(14), temperature
measurement = OFF)
ISTOP
Sleep Mode measured at VSUP
-40 °C iSTOP_S
85 °C (11)
125 °C
Current adder during current trigger event - (typ. 10 ms duration (14), temperature
measurement = OFF)
ISLEEP
–
–
–
100
105
106
120
190
230
–
–
–
410
450
520
490
520
590
–
–
–
–
105
125
185
1500
130
230
270
1750
–
–
–
–
60
60
80
1500
80
130
140
1750
µA
µA
Analog die contribution - excluding MCU and external load current, (3.5 V VSUP 28 V; -40 °C TA 125 °C)
INORMAL
1.5
4.0
mA
Run Current, TA 125 °C
IRUN
13.5
18.8
mA
Wait current, TA 125 °C
IWAIT
7.0
8.8
mA
Normal mode current measured at VSUP
MCU die contribution, VDDRX = 5.5 V
Notes
10. See Table 11, Table 12, Table 13, and Table 14 for conditions. Currents measured in Test mode with external loads (100 pF) and the external clock
at 64 MHz.
11. Not tested in production, guaranteed by characterization
12. Typical values noted reflect the approximate parameter mean at TA = 25 °C.
13. From VSUP 6.0 to 28 V
14. Duration based on channel configuration. 10ms typical for Decimation Factor = 512, Chopper = ON.
MM912_637D1
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3.5
Static electrical characteristics
All characteristics noted under conditions 3.5 V VSUP28 V, -40 C TA125 C, unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
3.5.1
Static electrical characteristics analog die
Table 16. Static electrical characteristics - power supply
Ratings
Symbol
Min.
Typ.
Max.
Unit
1.75
1.9
2.1
1.85
2.1
2.35
1.0
1.3
1.7
LVRAL
1.9
2.05
2.2
V
Low Voltage Reset L (POR) Assert (measured on VDDL)
Cranking Mode Disabled
V
Low Voltage Reset L (POR) Deassert (measured on VDDL)
Cranking Mode Disabled
V
Low Voltage Reset L (POR) Assert (measured on VDDL)
Cranking Mode Enabled(15)
VPORCL
Low Voltage Reset A (LVRA) Assert (measured on VDDA)
V
Low Voltage Reset A (LVRA) Deassert (measured on VDDA)
V
LVRAH
2.0
2.15
2.3
V
Low Voltage Reset X (LVRX) Assert (measured on VDDX)
VLVRXL
2.5
2.75
3.0
V
Low Voltage Reset X (LVRX) Deassert (measured on VDDX)
V
2.7
2.95
3.25
V
Low Voltage Reset H (LVRH) Assert (measured on VDDH)
V
1.9
2.075
2.2
V
Low Voltage Reset H (LVRH) Deassert (measured on VDDH)
VLVRHH
2.05
2.175
2.3
V
UVIL
4.55
5.2
6.1
V
PORL
PORH
LVRXH
LVRHL
V
V
V
Undervoltage Interrupt (UVI) Assert (measured on VSUP), Cranking Mode
Disabled
V
Undervoltage Interrupt (UVI) Deassert (measured on VSUP), Cranking Mode
Disabled
V
UVIH
4.7
5.4
6.2
V
Undervoltage Cranking Interrupt (UVI) Assert (measured on VSUP) Cranking
Mode Enabled
VUVCIL
3.4
3.6
4.0
V
Undervoltage Cranking Interrupt (UVI) Deassert (measured on VSUP) Cranking
Mode Enabled
V
3.5
3.8
4.1
V
VSENSE/VOPT High Voltage Warning Threshold Assert(16)
UVCIH
V
28
TH
V
Notes
15. Deassert with Cranking off = VPORH
16. 5.0 V < VSUP < 28 V, Digital Threshold at the end of channel chain (incl. compensation)
Table 17. Static electrical characteristics - resets
Ratings
Symbol
Min.
VOL
Low-state Output Voltage IOUT = 2.0 mA
RRPU
Pull-up Resistor
25
Low-state Input Voltage
VIL
High-state Input Voltage
VIH
0.7VDDX
Reset Release Voltage (VDDX)
VRSTRV
0
RESET_A pin Current Limitation
ILIMRST
MM912_637D1
Data sheet: Technical data
Typ.
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Rev. 6.0 — 6/2021
Max.
Unit
0.8
V
50
k
0.3VDDX
V
V
0.02
1.0
V
10
mA
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Table 18. Static electrical characteristics - voltage regulator outputs
Ratings
Symbol
Min.
Typ.
Max.
Unit
Output Voltage 1.0 mA IVDDA 1.5 mA
VDDA
2.25
2.5
2.75
V
Output Current Limitation
IVDDA
10
mA
Analog Voltage Regulator - VDDA(17)
Low Power Digital Voltage Regulator - VDDL(17)
VDDL
2.25
2.5
2.75
V
Output Voltage 1.0 mA IVDDH 30 mA
VDDH
2.4
2.5
2.75
V
Output Current Limitation
IVDDH
65
mA
Output Voltage
High Power Digital Voltage Regulator - VDDH
(18)
5.0 V Voltage Regulator - VDDX(18)
Output Voltage 1.0 mA IVDDX 30 mA
VDDX
3.15
5.0
5.9
V
Output Current Limitation
IVDDX
45
60
80
mA
Notes
17. No additional current must be taken from those outputs.
18. The specified current ranges does include the current for the MCU die. No external loads recommended.
Table 19. Static electrical characteristics - LIN physical layer interface - LIN
Ratings
Current Limitation for Driver dominant state. VBUS = 18 V
Symbol
Min.
Typ.
Max.
Unit
IBUSLIM
40
120
200
mA
Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE;
Driver OFF; VBUS = 0 V; VBAT = 12 V
IBUS_PAS_DOM
Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE;
Driver OFF; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS VBAT
IBUS_PAS_REC
Input Leakage Current; GND Disconnected; GNDDEVICE = VSUP;
0 < VBUS < 18 V; VBAT = 12 V
IBUS_NO_GND
Input Leakage Current; VBAT disconnected; VSUP_DEVICE = GND; 0 <
VBUS < 18 V
IBUS_NO_BAT
-1.0
-1.0
Receiver Input Voltage; Receiver Dominant State
VBUSDOM
Receiver Input Voltage; Receiver Recessive State
VBUSREC
0.6
Receiver Threshold Center (VTH_DOM + VTH_REC)/2
VBUS_CNT
0.475
Receiver Threshold Hysteresis (VTH_REC - VTH_DOM)
VBUS_HYS
Voltage Drop at the serial Diode
DSER_INT
0.3
RSLAVE
20
LIN Pull-up Resistor
mA
20
µA
1.0
mA
100
µA
0.4
VSUP
VSUP
0.5
0.525
VSUP
0.175
VSUP
0.7
1.0
V
30
60
k
0.3
VSUP
Low Level Output Voltage, IBUS=40 mA
VDOM
High Level Output Voltage, IBUS=-10 µA, RL=33 k
VREC
VSUP-1
J2602 Detection Deassert Threshold for VSUP level
VJ2602H
5.9
6.3
6.7
V
J2602 Detection Assert Threshold for VSUP level
VJ2602L
5.8
6.2
6.6
V
VJ2602HYS
70
190
250
mV
VLINWUP
4.0
5.25
6.0
V
J2602 Detection Hysteresis
BUS Wake-up Threshold
MM912_637D1
Data sheet: Technical data
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Rev. 6.0 — 6/2021
V
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Table 20. Static electrical characteristics - high voltage input - PTB3 / L0
Ratings
Symbol
Min.
Typ.
Max.
Unit
VWTHR
1.3
2.6
3.4
V
Input High Voltage (digital Input)
VIH
0.7VDDX
VDDX+0.3
V
Input Low Voltage (digital Input)
VIL
VSS-0.3
0.35VDDX
V
VHYS
50
140
200
mV
VL0CLMP
4.9
6.0
7.0
V
1.1
mA
Wake-up Threshold - Rising Edge
Input Hysteresis
Internal Clamp Voltage
IIN
Input Current PTB3 / L0 (VIN = 42 V; RL0=47 k)
Internal pull-down resistance
(19)
PTB3 / L0 Series Resistor
PTB3 / L0 Capacitor
RPD
50
100
200
k
RPTB3
42.3
47
51.7
k
CL0
42.3
47
51.7
nF
Max.
Unit
Notes
19. Disabled by default.
Table 21. Static electrical characteristics - general purpose I/O - PTB[0...2]
Ratings
Symbol
Min.
Input High Voltage
VIH
0.7VDDX
VDDX+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.35VDDX
V
VHYS
50
200
mV
1.0
µA
Input Hysteresis
IIN
Input Leakage Current (pins in high-impedance input mode)
(VIN = VDDX or VSSX)
Output High Voltage (pins in output mode) Full drive IOH = –5.0 mA
VOH
Output Low Voltage (pins in output mode) Full drive IOL = 5.0 mA
VOL
Internal Pull-up Resistance (VIH min. > Input voltage > VIL max)
(20)
RPUL
Maximum Current All PTB Combined(21)
IBMAX
Output Drive strength at 10 MHz
COUT
140
-1.0
VDDX-0.8
25
CIN
Input Capacitance
Typ.
V
37.5
0.8
V
50
k
6.0
-17
pF
17
mA
100
pF
Notes
20. Disabled by default.
21. Overall VDDR Regulator capability to be considered.
Table 22. Static electrical characteristics - current sense module(22) (continued)
Ratings
Symbol
Gain Error
with temperature based gain compensation adjustment(23), (24)
Offset Error(25),(26)
IGAINERR
IRES
ISENSEH, ISENSEL
terminal voltage
differential signal voltage range
VINC
VIND
Differential Leakage Current: differential voltage between ISENSEH/
ISENSEL, 200 mV
MM912_637D1
Data sheet: Technical data
Typ.
Max.
Unit
-0.5
+/-0.1
0.5
%
0.5
µV
IOFFSETERR
Resolution
Wake-up Current Threshold Resolution
Min.
ISENSE_DLC
IRESWAKE
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0.1
µV
-300
-200
300
200
mV
-2.0
2.0
nA
0.2
µV
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Table 22. Static electrical characteristics - current sense module(22) (continued)
Ratings
Resistor Threshold for OPEN Detection
Symbol
Min.
Typ.
Max.
Unit
ROPEN
0.8
1.25
1.8
M
Notes
22. 3.5 V VSUP 28 V, after applying default trimming values - see Section 5, “MM912_637 - trimming".
23. Gain Compensation adjustment on calibration request interrupt with TCALSTEP
24. 0.65%, including lifetime drift for gain 256 and 512
25. Chopper Mode = ON, Gain with automatic gain control enabled
26. Parameter not tested. Guaranteed by design and characterization
Table 23. Static electrical characteristics - voltage sense module(27)
Ratings
(28)
Symbol
Min.
Typ.
Max.
-0.5
-0.25
-0.15
0.1
0.1
0.1
0.5
0.25
0.15
Unit
VGAINERR
Gain Error
18 V VIN 28 V
3.5 V VIN 5.0 V(29)
5.0 V VIN 18 V(29),(31)
Offset Error(30),(32)
VOFFSETERR
Resolution with RVSENSE = 2.2 k
-1.5
VRES
%
1.5
mV
0.5
mV
Max.
Unit
Notes
27. 3.5 V VSUP 28 V, after applying default trimming values - see Section 5, “MM912_637 - trimming".
28. Including resistor mismatch drift
29. Gain Compensation adjustment on calibration request interrupt with TCALSTEP
30. Chopper Mode = ON.
31. 0.2%, including lifetime drift
32. Parameter not tested. Guaranteed by design and characterization.
Table 24. Static electrical characteristics - temperature sense module(33)
Ratings
Measurement Range
Symbol
Min.
Typ.
TRANGE
-40
150
°C
-2.0
-3.0
2.0
3.0
K
Accuracy
-40 °C TA 60 °C(34)
-40 °C TA 50 °C
TACC
Resolution
TRES
TSUP Voltage Output, 10 µA ITSUP 100 µA
VTSUP
1.1875
1.25
1.3125
V
TSUP Capacitor with ECAP = 1
CTSUP
209
220
231
pF
TCALSTEP
-25
25
K
Max Calibration Request Interrupt Temperature Step
8.0
mK
Notes
33. 3.5 V VSUP 28 V, after applying default trimming values - see Section 5, “MM912_637 - trimming".
34. Temperature not tested in production. Guaranteed by design and characterization.
MM912_637D1
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3.5.2
Static electrical characteristics MCU die
Table 25. Static electrical characteristics - MCU
Ratings
Symbol
Min.
Typ.
Max.
Unit
0.6
0.9
-
V
-
0.95
1.6
V
Power On Reset Assert (measured on VDDRX)
V
Power On Reset Deassert (measured on VDDRX)
VPORD
Low Voltage Reset Assert (measured on VDDRX)
V
LVRA
2.97
3.06
-
V
Low Voltage Reset Deassert (measured on VDDRX)
V
LVRD
-
3.09
3.3
V
Low Voltage Interrupt Assert (measured on VDDRX)
VLVIA
4.06
4.21
4.36
V
Low Voltage Interrupt Deassert (measured on VDDRX)
V
4.19
4.34
4.49
V
PORA
LVID
Table 26. Static electrical characteristics - oscillator (OSCLCP)
Ratings
Symbol
Min.
Startup Current
iOSC
100
Input Capacitance (EXTAL, XTAL pins)
CIN
EXTAL Pin Input Hysteresis
EXTAL Pin oscillation amplitude (loop controlled Pierce)
Typ.
Max.
Unit
A
7.0
pF
VHYS,EXTAL
—
180
—
mV
VPP,EXTAL
—
0.9
—
V
Table 27. 5.0 V I/O characteristics for all I/O pins except EXTAL, XTAL, TEST, D2DI, and supply pins
(4.5 V < VDDRX < 5.5 V; TJ: –40 °C to +150 °C, unless otherwise noted) (continued)
Ratings
Symbol
Min.
Typ.
Max.
Unit
Input High Voltage
VIH
0.65*VDDRX
—
—
V
Input High Voltage
VIH
—
—
VDDRX+0.3
V
Input Low Voltage
VIL
—
—
0.35*VDDRX
V
Input Low Voltage
VIL
VSSRX–0.3
—
—
V
250
—
mV
—
1.00
Input Hysteresis
VHYS
Input Leakage Current (pins in high-impedance input mode)(35)
VIN = VDDRX or VSSRX
I
Input Leakage Current (pins in high-impedance input mode)(36)
VIN = VDDX or VSSX
TA = –40 C
TA = 25 C
TA = 70 C
TA = 85 C
TA = 105 C
TA = 110 C
TA = 120 C
TA = 125 C
TA = 130 C
TA = 150 C
I
Output High Voltage (pins in output mode), IOH = –4.0 mA
V
Output Low Voltage (pins in output mode), IOL = 4.0 mA
IN
–1.00
1.0
1.0
8.0
14
26
32
40
60
74
92
240
IN
A
nA
VDDRX – 0.8
—
—
V
VOL
—
—
0.8
V
Internal Pull-up Current, VIH min > input voltage > VIL max
IPUL
-10
—
-130
A
Internal Pull-down Current, VIH min > input voltage > VIL max
IPDH
10
—
130
A
Cin
—
7
—
pF
Input Capacitance
MM912_637D1
Data sheet: Technical data
OH
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Table 27. 5.0 V I/O characteristics for all I/O pins except EXTAL, XTAL, TEST, D2DI, and supply pins
(4.5 V < VDDRX < 5.5 V; TJ: –40 °C to +150 °C, unless otherwise noted) (continued)
Ratings
Symbol
Min.
Typ.
Max.
Unit
IICS
IICP
–2.5
–25
—
2.5
25
mA
Injection Current(37)
Single pin limit
Total device Limit, sum of all injected currents
Notes
35. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8.0 C to 12 C in the
temperature range from 50 C to 125 C.
36. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8.0 C to 12 C in the
temperature range from 50 C to 125 C.
37. Refer to Section 3.5.2.1, “Current injection" for more details
3.5.2.1
Current injection
The power supply must maintain regulation within the VDDX operating range during instantaneous and operating maximum current
conditions. If positive injection current (VIN > VDDX) is greater than IDDX, the injection current may flow out of VDDX and could result in
the external power supply going out of regulation. Ensure that the external VDDX load will shunt current greater than the maximum injection
current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if the clock rate is very
low, which would reduce overall power consumption.
3.6
Dynamic electrical characteristics
Dynamic characteristics noted under conditions 3.5 V VSUP28 V, -40 C TA125 C, unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
3.6.1
Dynamic electrical characteristics analog die
Table 28. Dynamic electrical characteristics - modes of operation
Ratings
Symbol
Min.
Typ.
Max.
Unit
Low Power Oscillator Frequency
fOSCL
—
512
—
kHz
Low Power Oscillator Tolerance over full temperature range
Analog Option 2
Analog Option 1
fTOL_A
-4.0
-5.0
—
—
4.0
5.0
%
Low Power Oscillator Tolerance - synchronized ALFCLK(38)
ALF clock cycle = 1.0 ms
ALF clock cycle = 2.0 ms
ALF clock cycle = 4.0 ms
ALF clock cycle = 8.0 ms
fTOLC_A
fTOL
fTOL+0.2
fTOL+0.1
fTOL+0.05
fTOL+0.025
fTOL-0.2
fTOL-0.1
fTOL-0.05
fTOL-0.025
%
Notes
38. Parameter not tested. Guaranteed by design and characterization.
Table 29. Dynamic electrical characteristics - die to die interface - D2D
Ratings
Symbol
Min.
Typ.
Max.
Unit
fD2D
—
—
32.768
MHz
Symbol
Min.
Typ.
Max.
Unit
Reset Deglitch Filter Time
tRSTDF
1.0
2.0
3.2
µs
Reset Time for watchdog and Hardware Reset (RESETA pin set low)
tRSTRT
—
32
—
µs
Operating Frequency (D2DCLK, D2D[0:3])
Table 30. Dynamic electrical characteristics - resets
Ratings
MM912_637D1
Data sheet: Technical data
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Table 31. Dynamic electrical characteristics - wake-up / cyclic sense
Ratings
Cyclic Wake-up Time(39)
Cyclic Current Measurement Step Width
Symbol
Min.
Typ.
Max.
Unit
tWAKEUP
ALFCLK
—
TIM4CH
ms
tSTEP
ALFCLK
—
16Bit
ms
Min.
Typ.
Max.
Unit
(40)
Notes
39. Cyclic wake-up on ALFCLK clock based 16 Bit TIMER with maximum 128x prescaler (min 1x)
40. Cyclic wake-up on ALFCLK clock with 16 Bit programmable counter
Table 32. Dynamic electrical characteristics - window watchdog
Ratings
Symbol
tIWDTO
Initial Non-window Watchdog Timeout
see Figure 39
ms
Table 33. Dynamic electrical characteristics - LIN physical layer interface - LIN (continued)
Ratings
Symbol
Min.
Typ.
Max.
Unit
Bus Wake-up Deglitcher (Sleep and Stop Mode)
tPROPWL
60
80
100
µs
Fast Bit Rate (Programming Mode)
BRFAST
—
—
100
kBit/s
Propagation delay of receiver
tRX_PD
—
—
6.0
µs
tRX_SYM
-2.0
—
2.0
µs
0.396
—
—
—
—
0.581
0.417
—
—
—
—
0.590
-7.25
0
7.25
Symmetry of receiver propagation delay rising edge w.r.t. falling edge
LIN driver - 20.0 kBit/s; bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 k / 6,8 nF;660 / 10 nF;500
Duty Cycle 1:
THREC(MAX) = 0.744 x VSUP
THDOM(MAX) = 0.581 x VSUP
7.0 V VSUP18 V; tBIT = 50 µs;
D1 = tBUS_REC(MIN)/(2 x tBIT)
D1
Duty Cycle 2:
THREC(MIN) = 0.422 x VSUP
THDOM(MIN) = 0.284 x VSUP
7.6 V VSUP18 V; tBit = 50 µs
D2 = tBUS_REC(MAX)/(2 x tBIT)
D2
LIN driver - 10.0 kBit/s; bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 k / 6,8 nF;660 / 10 nF;500
Duty Cycle 3:
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
7.0 V VSUP18 V; tBit = 96 µs
D3 = tBUS_REC(MIN)/(2 x tBIT)
D3
Duty Cycle 4:
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
7.6 V VSUP18 V; tBIT = 96 µs
D4 = tBUS_REC(MAX)/(2 x tBIT)
D4
LIN Transmitter Timing, (VSUP from 7.0 to 18 V) - See Figure 5
Transmitter Symmetry
tTRAN_SYM < MAX(ttran_sym60%, tTRAN_SYM40%)
tTRAN_SYM60% = tTRAN_PDF60% - tTRAN_PDR60%
tTRAN_SYM40% = tTRAN_PDF40% - tTRAN_PDR40%
MM912_637D1
Data sheet: Technical data
tTRAN_SYM
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TX
BUS
60%
40%
ttran_pdf60%
ttran_pdr40%
ttran_pdf40%
ttran_pdr60%
Figure 5. LIN transmitter timing
Table 34. Dynamic electrical characteristics - general purpose I/O - PTB3 / L0]
Ratings
Symbol
Min.
tWUPF
Wake-up Glitch Filter Time
Typ.
Max.
20
Unit
µs
Table 35. Dynamic electrical characteristics - general purpose I/O - PTB[0...2]
Ratings
Symbol
Min.
Typ.
Max.
Unit
GPIO Digital Frequency
fPTB
10
MHz
Propagation Delay - Rising Edge(41)
tPDr
20
ns
tRISE
17.5
ns
tPDf
20
ns
tFALL
17.5
ns
Rise Time - Rising Edge
(41)
Propagation Delay - Falling
Rise Time - Falling
Edge(41)
Edge(41)
Notes
41. Load PTBx = 100 pF
MM912_637D1
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Table 36. Dynamic Electrical Characteristics - Current Sense Module
Ratings
Symbol
Frequency Attenuation(42),(43)
500 Hz (fSTOP)
Min
Typ
3.0
40
Signal Update Rate(44)
fIUPDATE
Signal Path Match with Voltage Channel
fIVMATCH
Gain Change Duration (Automatic GCB active)(45)
Max
0.5
8.0
2.0
tGC
Unit
dB
kHz
µs
14
µs
Max.
Unit
Notes
42. Characteristics identical to Voltage Sense Module
43. With default LPF coefficients
44. After passing decimation filter
45. Parameter not tested. Guaranteed by design and characterization.
Table 37. Dynamic electrical characteristics - voltage sense module
Ratings
Symbol
Min.
Typ.
attenuation(46),(47)
Frequency
95...105 Hz (fPASS)
>500 Hz (fSTOP)
3.0
40
Signal update rate(48)
fVUPDATE
Signal path match with Current Channel(49)
fIVMATCH
0.5
8.0
2.0
dB
kHz
µs
Notes
46. Characteristics identical to Voltage Sense Module
47. With default LPF coefficients
48. After passing decimation filter
49. Parameter not tested. Guaranteed by design and characterization.
Table 38. Dynamic electrical characteristics - temperature sense module
Ratings
Signal Update
Rate(50)
Symbol
Min.
fTUPDATE
1.0
Typ.
Max.
Unit
4.0
kHz
Notes
50. 1.0 kHz with Chopper Enabled, 4.0 kHz with Chopper Disabled (fixed decimeter = 128)
3.6.2
3.6.2.1
3.6.2.1.1
Dynamic electrical characteristics MCU die
NVM
Timing parameters
The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV register. The frequency of this
derived clock must be set within the limits specified as fNVMOP. The NVM module does not have any means to monitor the frequency, and
will not prevent program or erase operations at frequencies above or below the specified minimum. When attempting to program or erase
the NVM module at a lower frequency, a full program or erase transition is not assured.
The following sections provide equations which can be used to determine the time required to execute specific flash commands. All timing
parameters are a function of the bus clock frequency, fNVMBUS. All program and erase times are also a function of the NVM operating
frequency, fNVMOP. A summary of key timing parameters can be found in Table 39.
MM912_637D1
Data sheet: Technical data
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3.6.2.1.1.1
Erase verify all blocks (blank check) (FCMD=0x01)
The time required to perform a blank check on all blocks is dependent on the location of the first non-blank word starting at relative address
zero. It takes one bus cycle per phrase to verify, plus a setup of the command. Assuming that no non-blank location is found, then the time
to erase verify all blocks is given by:
1
t check = 35500 -------------------f NVMBUS
3.6.2.1.1.2
Erase verify block (blank check) (FCMD=0x02)
The time required to perform a blank check is dependent on the location of the first non-blank word starting at relative address zero. It
takes one bus cycle per phrase to verify, plus a setup of the command.
Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by:
1
t pcheck = 33500 -------------------f NVMBUS
Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by:
1
t dcheck = 2800 -------------------f NVMBUS
3.6.2.1.1.3
Erase verify p-flash section (FCMD=0x03)
The maximum time to erase verify a section of P-Flash depends on the number of phrases being verified (NVP) and is given by:
1
t 450 + N VP -------------------f NVMBUS
3.6.2.1.1.4
Read once (FCMD=0x04)
The maximum read once time is given by:
1
t = 400 -------------------f NVMBUS
3.6.2.1.1.5
Program p-flash (FCMD=0x06)
The programming time for a single phrase of four P-Flash words and the two seven-bit ECC fields is dependent on the bus frequency,
fNVMBUS, as well as on the NVM operating frequency, fNVMOP.
The typical phrase programming time is given by:
1
1
t ppgm 164 ----------------- + 2000 -------------------f NVMOP
f NVMBUS
The maximum phrase programming time is given by:
1
1
t ppgm 164 ----------------- + 2500 -------------------f NVMOP
f NVMBUS
3.6.2.1.1.6
Program once (FCMD=0x07)
The maximum time required to program a P-Flash Program Once field is given by:
1
1
t 164 ----------------- + 2150 -------------------f NVMOP
f NVMBUS
3.6.2.1.1.7
Erase all blocks (FCMD=0x08)
The time required to erase all blocks is given by:
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1
1
t mass 100100 ----------------- + 70000 -------------------f NVMOP
f NVMBUS
3.6.2.1.1.8
Erase p-flash block (FCMD=0x09)
The time required to erase the P-Flash block is given by:
1
1
t pmass 100100 ----------------- + 67000 -------------------f NVMOP
f NVMBUS
3.6.2.1.1.9
Erase p-flash sector (FCMD=0x0A)
The typical time to erase a 512-byte P-Flash sector is given by:
1
1
t pera 20020 ----------------- + 700 -------------------f NVMOP
f NVMBUS
The maximum time to erase a 512-byte P-Flash sector is given by:
1
1
t pera 20020 ----------------- + 1400 -------------------f NVMOP
f NVMBUS
3.6.2.1.1.10 Unsecure flash (FCMD=0x0B)
The maximum time required to erase and unsecure the Flash is given by:
(for 128 kByte P-Flash and 4.0 kByte D-Flash)
1
1
t uns 100100 ----------------- + 70000 -------------------f NVMOP
f NVMBUS
3.6.2.1.1.11 Verify backdoor access key (FCMD=0x0C)
The maximum verify back door access key time is given by:
1
t = 400 -------------------f NVMBUS
3.6.2.1.1.12 Set user margin level (FCMD=0x0D)
The maximum set user margin level time is given by:
1
t = 350 -------------------f NVMBUS
3.6.2.1.1.13 Set field margin level (FCMD=0x0E)
The maximum set field margin level time is given by:
1
t = 350 -------------------f NVMBUS
3.6.2.1.1.14 Erase verify d-flash section (FCMD=0x10)
The time required to Erase Verify D-Flash for a given number of words NW is given by:
1
t dcheck 450 + N W -------------------f NVMBUS
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3.6.2.1.1.15 Program d-flash (FCMD=0x11)
D-Flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary,
since programming across a row boundary requires extra steps. The D-Flash programming time is specified for different cases: 1,2,3,4
words and 4 words across a row boundary. The typical D-Flash programming time is given by the following equation, where NW denotes
the number of words; BC=0 if no row boundary is crossed and BC=1, if a row boundary is crossed:
1
1
t dpgm 14 + 54 N W + 14 BC ----------------- + 500 + 525 N W + 100 BC --------------------
f NVMOP
f NVMBUS
The maximum D-Flash programming time is given by:
1
1
t dpgm 14 + 54 N W + 14 BC ----------------- + 500 + 750 N W + 100 BC --------------------
f NVMOP
f NVMBUS
3.6.2.1.1.16 Erase d-flash sector (FCMD=0x12)
Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given by:
1
1
t dera 5025 ----------------- + 700 -------------------f NVMOP
f NVMBUS
Maximum D-Flash sector erase times is given by:
1
1
t dera 20100 ----------------- + 3400 -------------------f NVMOP
f NVMBUS
The D-Flash sector erase time is ~5.0 ms on a new device and can extend to ~20 ms as the flash is cycled.
Table 39. NVM timing characteristics (FTMRC)
Symbol
Min.
Typ.(51)
Max.(52)
Unit(53)
Bus Frequency
fNVMBUS
1.0
—
32.768
MHz
Operating Frequency
fNVMOP
0.8
1.0
1.05
MHz
Erase All Blocks (mass erase) Time
tMASS
—
100
130
ms
Erase Verify All Blocks (blank check) Time
tCHECK
—
—
35500
tCYC
tUNS
—
100
130
ms
P-flash Block Erase Time
tPMASS
—
100
130
ms
P-flash Erase Verify (blank check) Time
tPCHECK
—
—
33500
tCYC
P-flash Sector Erase Time
tPERA
—
20
26
ms
P-flash Phrase Programming Time
tPPGM
—
226
285
s
tDERA
—
(54)
26
ms
D-flash Erase Verify (blank check) Time
tDCHECK
—
—
2800
tCYC
D-flash One Word Programming Time
tDPGM1
—
100
107
s
D-flash Two Word Programming Time
tDPGM2
—
170
185
s
D-flash Three Word Programming Time
tDPGM3
—
241
262
s
D-flash Four Word Programming Time
tDPGM4
—
311
339
s
D-flash Four Word Programming Time Crossing Row Boundary
tDPGM4C
—
328
357
s
Rating
Unsecure Flash Time
D-flash Sector Erase Time
5
Notes
51. Typical program and erase times are based on typical fNVMOP and maximum fNVMBUS
52. Maximum program and erase times are based on minimum fNVMOP and maximum fNVMBUS
53. tCYC = 1 / fNVMBUS
54. Typical value for a new device
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3.6.2.1.2
NVM reliability parameters
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors, and burn-in to screen early
life failures. The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase
cycle count on the sector is incremented every time a sector or mass erase event is executed.
Table 40. NVM reliability characteristics(55)
Rating
Symbol
Min.
Typ.
Max.
Unit
tNVMRET
20
100(57)
—
Years
nFLPE
10 K
100 K(58)
—
Cycles
tNVMRET
5.0
100(57)
—
Years
Data retention at an average junction temperature of TJAVG = 85 C(55) after up to
10,000 program/erase cycles
tNVMRET
10
100(57)
—
Years
Data retention at an average junction temperature of TJAVG = 85 C(55) after less than
100 program/erase cycles
tNVMRET
20
100(57)
—
Years
nFLPE
50 K
500 K(58)
—
Cycles
Data retention at an average junction temperature of TJAVG = 85 C(55) after up to
10,000 program/erase cycles
Program Flash number of program/erase cycles (-40 C TJ 150 C
(55)
Data retention at an average junction temperature of TJAVG = 85 C
50,000 program/erase cycles
after up to
Data Flash number of program/erase cycles (-40 C TJ 150C
Notes
55. Conditions are shown in Table 10, unless otherwise noted
56. TJAVG does not exceed 85 C in a typical temperature profile over the lifetime of a consumer, industrial, or automotive application.
57. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the
Arrhenius equation. For additional information on how NXP defines Typical Data Retention, refer to Engineering Bulletin EB618
58. Spec table quotes typical endurance evaluated at 25C for this product family. For additional information on how NXP defines Typical Endurance,
refer to Engineering Bulletin EB619.
3.6.2.2
Phase locked loop
3.6.2.2.1
Jitter definitions
With each transition of the feedback clock, the deviation from the reference clock is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the VCOCLK frequency. Noise, voltage, temperature, and
other factors, cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock
periods as illustrated in Figure 6.
1
0
2
3
N-1
N
tmin1
tnom
tmax1
tminN
tmaxN
Figure 6. Jitter definitions
The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N).
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Defining the jitter as:
t
N
t
N
max
min
J N = max 1 – ----------------------- , 1 – -----------------------
Nt
Nt
nom
nom
For N < 100, the following equation is a good fit for the maximum jitter:
j
1
J N = -------N
J(N)
1
5
10
20
Figure 7. Maximum bus clock jitter approximation
N
NOTE
On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent.
3.6.2.2.2
Electrical characteristics for the PLL
Table 41. PLL characteristics
Rating
Max
Unit
8
32
MHz
fVCO
32.768
65.536
MHz
Lock Detection
LOCK|
0
1.5
%(59)
Un-lock Detection
UNL|
0.5
2.5
%(59)
tLOCK
150 + 256/fREF
s
j1
1.2
%
VCO Frequency During System Reset
VCO Locking Range
Time to Lock
(60)
Jitter Fit Parameter 1
Symbol
Min
fVCORST
Typ
Notes
59. % deviation from target frequency
60. fREF = 1.024 MHz, fBUS = 32.768 MHz equivalent fPLL = 65.536 MHz, REFRQ=00, SYNDIV=$1F, VCOFRQ=01, POSTDIV=$00
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3.6.2.3
Reset, oscillator and internal clock generation
Table 42. Dynamic electrical characteristics - MCU clock generator
Ratings
Symbol
Min.
Typ.
Max.
Unit
fBUS
—
—
32.768
MHz
fIRC1M_TRIM
—
1.024
—
MHz
fTOL
-1.0
-1.2
—
—
1.0
1.2
%
tTOLEXT
-0.5
0.5
%
fOSC
4.0
16
MHz
Oscillator Start-up Time (LCP, 4.0 MHz)(64)
tUPOSC
—
2.0
10
ms
Oscillator Start-up Time (LCP, 8.0 MHz)(64)
tUPOSC
—
1.6
8.0
ms
Oscillator Start-up Time (LCP, 16 MHz)
tUPOSC
—
1.0
5.0
ms
Clock Monitor Failure Assert Frequency
fCMFA
200
400
1000
kHz
Bus Frequency
Internal Reference Frequency
Internal Clock Frequency Tolerance(61),(62)
Analog Option 2
Analog Option 1
Clock Frequency Tolerance with External Oscillator(63)
Crystal Oscillator Range
(64)
Notes
61. -40 C TA125 C
62. 1.3%, including lifetime drift
63. Dependent on the external OSC
64. These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements
3.6.2.4
Reset characteristics
Table 43. Reset and stop characteristics(65)
Rating
Reset Input Pulse Width, minimum input time
Startup from Reset
STOP Recovery Time
Symbol
Min.
PWRSTL
2.0
Typ.
Max.
Unit
tVCORST
nRST
768
tVCORST
tSTP_REC
50
s
Notes
65. Conditions are shown in Table 10 unless otherwise noted
3.6.2.5
SPI timing
This section provides electrical parameters and ratings for the SPI. The measurement conditions are listed in Table 44.
Table 44. Measurement conditions
Description
Drive mode
Load capacitance CLOAD(66), on all outputs
Value
Unit
Full drive mode
—
50
pF
Notes
66. Conditions are shown in Table 10 unless otherwise noted
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3.6.2.5.1
Master mode
The timing diagram for master mode with transmission format CPHA = 0 is depicted in Figure 8.
SS
(Output)
2
1
SCK
(CPOL = 0)
(Output)
12
13
12
13
3
4
4
SCK
(CPOL = 1)
(Output)
5
MISO
(Input)
6
Bit MSB-1... 1
MSB IN2
10
MOSI
(Output)
LSB IN
9
11
Bit MSB-1... 1
MSB OUT2
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.
Figure 8. SPI master timing (CPHA = 0)
The timing diagram for master mode with transmission format CPHA=1 is depicted in Figure 9.
SS
(Output)
1
2
SCK
(CPOL = 0)
(Output)
4
SCK
(CPOL = 1)
(Output)
4
5
MISO
(Input)
12
13
Bit MSB-1... 1
MSB IN2
Port Data
13
3
6
LSB IN
11
9
MOSI
(Output)
12
Master MSB OUT2
Bit MSB-1... 1
Master LSB OUT
Port Data
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.
Figure 9. SPI master timing (CPHA = 1)
The timing characteristics for master mode are listed in Table 45.
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Table 45. SPI master mode timing characteristics
Num
C
1
D
1
Symbol
Min.
Typ.
Max.
Unit
SCK Frequency
fSCK
1/2048
—
12
fBUS
D
SCK Period
tSCK
2.0
—
2048
tBUS
2
D
Enable Lead Time
tLEAD
—
1/2
—
tSCK
3
D
Enable Lag Time
tLAG
—
1/2
—
tSCK
4
D
Clock (SCK) High or Low Time
tWSCK
—
1/2
—
tSCK
5
D
Data Setup Time (inputs)
tSU
8.0
—
—
ns
6
D
Data Hold Time (inputs)
tHI
8.0
—
—
ns
9
D
Data Valid After SCK Edge
tVSCK
—
—
29
ns
10
D
Data Valid After SS Fall (CPHA = 0)
tVSS
—
—
15
ns
11
D
Data Hold Time (outputs)
tHO
20
—
—
ns
12
D
Rise and Fall Time Inputs
tRFI
—
—
8.0
ns
13
D
Rise and Fall Time Outputs
tRFO
—
—
8.0
ns
3.6.2.5.2
Characteristic
Slave mode
The timing diagram for slave mode with transmission format CPHA = 0 is depicted in Figure 10.
SS
(Input)
1
12
13 3
12
13
SCK
(CPOL = 0)
(Input)
4
2
SCK
(CPOL = 1)
(Input) 10
4
8
7
MISO
(Output)
9
See
Note
Slave MSB
5
MOSI
(Input)
11
Bit MSB-1... 1
11
Slave LSB OUT
See
Note
6
MSB IN
Bit MSB-1... 1
LSB IN
NOTE: Not defined
Figure 10. SPI slave timing (CPHA = 0)
The timing diagram for slave mode with transmission format CPHA = 1 is depicted in Figure 11.
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SS
(Input)
3
1
2
SCK
(CPOL = 0)
(Input)
4
SCK
(CPOL = 1)
(Input)
4
See
Note
Slave
7
MSB OUT
5
MOSI
(Input)
13
12
13
8
11
9
MISO
(Output)
12
Bit MSB-1... 1
Slave LSB OUT
6
MSB IN
Bit MSB-1... 1
LSB IN
NOTE: Not defined
Figure 11. SPI slave timing (CPHA = 1)
The timing characteristics for slave mode are listed in Table 46.
Table 46. SPI slave mode timing characteristics
Num
C
1
D
1
Characteristic
Symbol
Min.
Typ.
Max.
Unit
SCK Frequency
fSCK
DC
—
14
fBUS
D
SCK Period
tSCK
4.0
—
fBUS
2
D
Enable Lead Time
tLEAD
4.0
—
—
fBUS
3
D
Enable Lag Time
tLAG
4.0
—
—
fBUS
4
D
Clock (SCK) High or Low Time
tWSCK
4.0
—
—
fBUS
5
D
Data Setup Time (inputs)
tSU
8.0
—
—
ns
6
D
Data Hold Time (inputs)
tHI
8.0
—
—
ns
7
D
Slave Access Time (time to data active)
tA
—
—
20
ns
8
D
Slave MISO Disable Time
tDIS
—
—
22
ns
(67)
ns
9
D
Data Valid After SCK Edge
tVSCK
—
—
29 + 0.5 tBUS
10
D
Data Valid After SS Fall
tVSS
—
—
29 + 0.5 tBUS(67)
ns
11
D
Data Hold Time (outputs)
tHO
20
—
—
ns
12
D
Rise and Fall Time Inputs
tRFI
—
—
8.0
ns
13
D
Rise and Fall Time Outputs
tRFO
—
—
8.0
ns
Notes
67. 0.5 tBUS added due to internal synchronization delay
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3.7
Thermal protection characteristics
Characteristics noted under conditions 3.5 V VSUP28 V, -40 C TA125 C, unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Table 47. Thermal characteristics
Ratings
Symbol
Min
Typ
Max
Unit
VDDH/VDDA/VDDX High Temperature Warning (HTI)
Threshold
Hysteresis
THTI
THTI_H
110
125
10
140
°C
VDDH/VDDA/VDDX Overtemperature Shutdown
Threshold
Hysteresis
TSD
TSD_H
155
165
10
180
°C
LIN Overtemperature Shutdown
TLINSD
150
165
180
°C
TLINSD_HYS
LIN Overtemperature Shutdown Hysteresis
3.8
20
°C
Electromagnetic compatibility (EMC)
All ESD testing is in conformity with the CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device
qualification, ESD stresses are performed for the Human Body Model (HBM), Machine Model (MM), Charge Device Model (CDM), as well
as LIN transceiver specific specifications.
A device will be defined as a failure, if after exposure to ESD pulses, the device no longer meets the device specification. Complete DC
parametric and functional testing is performed per the applicable device specification at room temperature, followed by hot temperature,
unless specified otherwise in the device specification. The immunity against transients for the LIN, PTB3/L0, VSENSE, ISENSEH,
ISENSEL, and VSUP, is specified according to the LIN Conformance Test Specification - Section LIN EMC Test Specification (ISO7637-2),
refer to the LIN Conformance Test Certification Report - available as separate document.
Table 48. Electromagnetic compatibility
Ratings
Symbol
Value/limit
Unit
ESD - Human Body Model (HBM) following AEC-Q100 / JESD22-A114
(CZAP = 100 pF, RZAP = 1500 )
- LIN (all GNDs shorted)
- All other Pins
VHBM
ESD - Charged Device Model (CDM) following AEC-Q100
Corner Pins
All other Pins
VCDM
±750
±500
V
ESD - Machine Model (MM) following AEC-Q100 (CZAP = 200 pF, RZAP = 0 ), All Pins
VMM
±200
V
Latch-up current at TA = 125 C(68)
ILAT
±100
mA
ESD GUN - LIN Conformance Test
unpowered, contact discharge. (CZAP=
150 pF, RZAP = 330 ); LIN (no bus filter CBUS); VSENSE with serial RVSENSE; VSUP with
CVSUP; PTB3 with serial RPTB3
± 6000
V
ESD GUN - IEC 61000-4-2 Test Specification(70), unpowered, contact discharge. (CZAP=
150 pF, RZAP = 330 ); LIN (no bus filter CBUS); VSENSE with serial RVSENSE; VSUP with
CVSUP; PTB3 with serial RPTB3
± 6000
V
ESD GUN - ISO10605(70), unpowered, contact discharge, CZAP= 150 pF,
RZAP = 2.0 kLIN (no bus filter CBUS); VSENSE with serial RVSENSE; VSUP with CVSUP;
PTB3 with serial RPTB3
± 8000
V
ESD GUN - ISO10605(70), powered, contact discharge, CZAP= 330 pF, RZAP = 2.0 kLIN (no
bus filter CBUS); VSENSE with serial RVSENSE; VSUP with CVSUP; PTB3 with serial RPTB3
± 8000
V
±8.0
±2.0
kV
Specification(69),
Notes
68. Input Voltage Limit = -2.5 to 7.5 V
69. Certification available on request
70. Tested internally only, following the reference document test procedure.
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4
Functional description and application information
This chapter describes the MM912_637 dual die device functions on a block by block base. The following symbols are shown on all
module cover pages to distinguish between the module location being the MCU die or the analog die:
The documented module is physically located on the Analog die. This applies to Section 4.2, “MM912_637 - analog die
overview" through Section 4.15, “Die to die interface - target".
MCU
ANALOG
The documented module is physically located on the Microcontroller die. This applies to Section 4.2, “MM912_637 - analog
die overview" through Section 4.26, “MCU - die-to-die initiator (9S12I128PIMV1)".
Sections concerning both die or the complete device will not have a specific indication (e.g. Section 5, “MM912_637 - trimming").
4.1
Introduction
Many types of electronic control units (ECUs) are connected to and supplied from the main car battery in modern cars. Depending on the
cars mode of operation (drive, start, stop, standby), the battery must deliver different currents to the different ECUs. The vehicle power
management has several sub-functions, like control of the set-point value of the power generator, dynamic load management during drive,
start, stop, and standby mode.
The Application Specific Integrated Circuit (ASIC) allows for two application circuits, depending on whether the bias current of the
MM912_637 itself shall be included into the current measurement.
Battery Plus Pole
CBAT
RSENSE
RSHUNT
ISENSEH
VSUP
LIN
LIN
GND
ISENSEL
VSENSE
Battery Minus Pole
CLIN
Chassis Ground
Figure 12. Typical IBS application (device GND = chassis GND)
Battery Plus Pole
CBAT
RSENSE
ISENSEH
VSUP
LIN
LIN
GND
ISENSEL
RSHUNT
VSENSE
Battery Minus Pole
CLIN
Chassis Ground
Figure 13. Typical IBS application (device GND = battery minus)
MM912_637D1
Data sheet: Technical data
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The vehicle power system needs actual measurement data from the battery, mainly voltage, current, and temperature. Out of these
measurement data, it needs calculated characteristics, such as dynamic internal battery resistance. Therefore, an intelligent battery
sensor (IBS) module is required.
To efficiently measure the battery voltage, current, and temperature, the IBS module is directly connected to and supplied from the battery.
It is located directly on the negative pole of the battery; the supply of the IBS module comes from 'KL30'. The battery current is measured
via a low-ohmic shunt resistor, connected between the negative pole of the battery and the chassis ground of the car. The battery voltage
is measured at 'KL30'.
The data communication between the IBS module and the higher level ECU is done via a LIN interface. The MM912_637 is able to
measure its junction temperature. That temperature is the basis for a model in software that calculates the battery temperature out of the
junction temperature. An optional external temperature sense input is provided as well.
4.1.1
Device register map
Table 49 shows the device register memory map overview.
Table 49. Device register memory map overview
Address
Module
Size (Bytes)
0x0000–0x0003
PIM (port integration module)
4
0x0004–0x0009
Reserved
6
0x000A–0x000B
MMC (memory map control)
2
0x000C–0x000D
PIM (port integration module)
2
0x000E–0x000F
Reserved
2
0x0010–0x0015
MMC (memory map control)
8
0x0016–0x0019
Reserved
2
0x001A–0x001B
Device ID register
2
0x001C–0x001E
Reserved
4
0x001F
INT (interrupt module)
1
0x0020–0x002F
DBG (debug module)
16
0x0030–0x0033
Reserved
4
0x0034–0x003F
CPMU (clock and power management)
12
0x0040–0x00D7
Reserved
152
0x00D8–0x00DF
D2DI (die 2 die initiator)
8
0x00E0–0x00E7
Reserved
32
0x00E8–0x00EF
SPI (serial peripheral interface)
8
0x00F0–0x00FF
Reserved
32
0x0100–0x0113
FTMRC control registers
20
0x0114–0x011F
Reserved
12
0x0120–0x017F
PIM (port integration module)
96
0x0180–0x01EF
Reserved
112
0x01F0–0x01FC
CPMU (clock and power management)
13
0x01FD–0x01FF
Reserved
3
0x0200-0x02FF
D2DI (die 2 die initiator, blocking access window)
256
0x0300–0x03FF
D2DI (die 2 die initiator, non-blocking write window)
256
MM912_637D1
Data sheet: Technical data
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NOTE
The reserved register space shown in Table 49 is not allocated to any module. This register space is
reserved for future use. Writing to these locations has no effect. Read access to these locations
returns a zero.
4.1.2
Detailed module register map
Table 50 to Table 63 show the detailed module maps of the MM912_637.
Table 50. 0x0000–0x0009 port integration module (PIM) 1 of 3
Address
Name
0x0000
PTA
0x0001
PTE
0x0002
DDRA
0x0003
DDRE
0x0004-0x
0009
Reserved
R
W
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
0
0
0
0
0
PE1
PE0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
DDRE1
DDRE0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
Table 51. 0x000A–0x000B memory map control (MMC) 1 of 2
Address
Name
0x000A
Reserved
0x000B
MODE
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
RDRD
RDRC
0
0
W
R
W
MODC
Table 52. 0x000C–0x000F port integration module (PIM) map 2 of 3
Address
Name
0x000C
PUCR
0x000D
RDRIV
0x000E-0x
000F
Reserved
MM912_637D1
Data sheet: Technical data
Bit 7
R
0
W
R
Bit 6
BKPUE
0
0
0
0
0
0
0
0
W
R
PDPEE
0
0
0
0
0
W
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Table 53. 0x0010–0x0019 memory map control (MMC) 2 of 2
Address
Name
0x0010
Reserved
0x0011
DIRECT
0x0012-0x
0014
Reserved
0x0015
PPAGE
0x0016-0x
0019
Reserved
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
0
0
0
0
0
0
0
0
0
0
0
0
PIX3
PIX2
PIX1
PIX0
0
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
Bit 2
Bit 1
Bit 0
W
R
W
R
W
R
W
R
W
Table 54. 0x001A–0x001E miscellaneous peripheral
Address
Name
0x001A
PARTIDH
0x001B
PARTIDL
0x001C-0x
001E
Reserved
Bit 7
Bit 6
R
PARTIDH
W
R
PARTIDL
W
R
0
0
0
0
0
W
Table 55. 0x001F interrupt module (S12SINT)
0x001F
IVBR
R
IVB_ADDR[7:0]
W
Table 56. 0x0020–0x002F debug module (S12XDBG)
Address
Name
0x0020
DBGC1
0x0021
DBGSR
0x0022
DBGTCR
0x0023
DBGC2
0x0024
DBGTBH
0x0025
DBGTBL
MM912_637D1
Data sheet: Technical data
Bit 7
R
W
R
ARM
TBF(71)
Bit 6
Bit 5
Bit 4
Bit 3
0
0
BDM
DBGBRK
0
0
0
0
0
TRIG
0
0
SSF2
COMRV
SSF1
SSF0
W
R
0
W
R
TSOURCE
0
TRCMOD
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ABCM
W
R
TALIGN
W
R
W
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Table 56. 0x0020–0x002F debug module (S12XDBG) (continued)
Address
Name
0x0026
DBGCNT
0x0027
DBGSCRX
0x0027
DBGMFR
0x0028(72)
DBGACTL
0x0028(73)
DBGBCTL
0x0028(74)
DBGCCTL
0x0029
DBGXAH
0x002A
DBGXAM
0x002B
DBGXAL
0x002C
DBGADH
0x002D
DBGADL
0x002E
DBGADHM
0x002F
DBGADLM
Bit 7
R
(71)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SC3
SC2
SC1
SC0
TBF
0
CNT
0
0
0
0
0
0
0
0
0
MC2
MC1
MC0
SZE
SZ
TAG
BRK
RW
RWE
NDB
COMPE
SZE
SZ
TAG
BRK
RW
RWE
0
0
TAG
BRK
RW
RWE
0
0
0
0
0
0
Bit 15
14
13
12
11
Bit 7
6
5
4
Bit 15
14
13
Bit 7
6
Bit 15
Bit 7
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
0
COMPE
COMPE
Bit 17
Bit 16
10
9
Bit 8
3
2
1
Bit 0
12
11
10
9
Bit 8
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
W
R
0
Notes
71. This bit is visible at DBGCNT[7] and DBGSR[7]
72. This represents the contents if the Comparator A control register is blended into this address.
73. This represents the contents if the Comparator B control register is blended into this address.
74. This represents the contents if the Comparator C control register is blended into this address.
Table 57. 0x0034–0x003F Clock and Power Management (CPMU) 1 of 2
Address
Name
0x0034
CPMU
SYNR
R
0x0035
CPMU
REFDIV
R
MM912_637D1
Data sheet: Technical data
Bit 7
W
W
Bit 6
Bit 5
Bit 4
VCOFRQ[1:0]
REFFRQ[1:0]
SYNDIV[5:0]
0
0
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Table 57. 0x0034–0x003F Clock and Power Management (CPMU) 1 of 2 (continued)
Address
Name
0x0036
CPMU
POSTDIV
0x0037
CPMUFLG
0x0038
CPMUINT
0x0039
CPMUCLKS
0x003A
CPMUPLL
0x003B
CPMURTI
0x003C
CPMUCOP
0x003D
Reserved
0x003E
Reserved
0x003F
CPMU
ARMCOP
R
Bit 7
Bit 6
Bit 5
0
0
0
RTIF
PORF
LVRF
0
0
Bit 4
Bit 3
W
R
W
R
RTIE
0
PRE
PCE
RTI
OSCSEL
COP
OSCSEL
0
0
0
0
RTR2
RTR1
RTR0
CR2
CR1
CR0
OSCIE
0
RTR3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
WCOP
RSBCK
0
0
0
R
W
R
0
LOCKIE
RTR4
RTR6
W
UPOSC
RTR5
RTDEC
W
R
OSCIF
FM0
0
W
ILAF
FM1
0
R
LOCK
LOCKIF
0
PSTP
R
Bit 0
0
PLLSEL
W
Bit 1
POSTDIV[4:0]
W
R
Bit 2
WRTMASK
W
R
W
Table 58. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) 1 of 3
Address
Name
0x00D8
D2DCTL0
0x00D9
D2DCTL1
0x00DA
D2DSTAT0
0x00DB
D2DSTAT1
0x00DC
D2DADRHI
0x000D
D2DADRLO
0x00DE
D2DDATAHI
MM912_637D1
Data sheet: Technical data
R
W
R
W
R
W
R
Bit 7
Bit 6
Bit 5
D2DEN
D2DCW
D2DSWAI
0
0
0
ACKERF
CNCLF
TIMEF
TERRF
PARF
PAR1
PAR0
D2DIF
D2DBSY
0
0
0
0
0
0
RWB
SZ8
0
NBLK
0
0
0
0
D2DIE
ERRIF
D2DCLKDIV[1:0]
TIMOUT[3:0]
W
R
W
R
ADR[7:0]
W
R
DATA[15:8]
W
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Table 58. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) 1 of 3 (continued)
0x00DF
D2DDATALO
R
DATA[7:0]
W
Table 59. 0x00E8–0x00EF serial peripheral interface (SPI)
Address
Name
0x00E8
SPICR1
0x00E9
SPICR2
0x00EA
SPIBR
0x00EB
SPISR
0x00EC
SPIDRH
0x00ED
SPIDRL
0x00EE
Reserved
0x00EF
Reserved
R
W
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
MODFEN
BIDIROE
SPISWAI
SPC0
SPR2
SPR1
SPR0
0
W
R
0
XFRW
0
0
0
SPPR2
SPPR1
SPPR0
SPIF
0
SPTEF
MODF
0
0
0
0
R
R15
R14
R13
R12
R11
R10
R9
R8
W
T15
T14
T13
T12
T11
T10
T9
T8
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
W
R
W
Table 60. 0x0100–0x0113 flash control & status register FTMRC
Address
Name
0x0100
FCLKDIV
0x0101
FSEC
0x0102
FCCOBIX
0x0103
Reserved
0x0104
FCNFG
0x0105
FERCNFG
0x0106
FSTAT
MM912_637D1
Data sheet: Technical data
Bit 7
R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FDIVLCK
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
KEYEN1
KEYEN0
RNV5
RNV4
RNV3
RNV2
SEC1
SEC0
0
0
0
0
0
CCOBIX2
CCOBIX1
CCOBIX0
0
0
0
0
0
0
0
0
0
0
0
0
FDFD
FSFD
0
0
0
0
0
DFDIE
SFDIE
ACCERR
FPVIOL
MGBUSY
RSVD
MGSTAT1
MGSTAT0
FDIVLD
W
R
W
R
W
R
W
R
W
R
CCIE
0
IGNSF
W
R
W
CCIF
0
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Table 60. 0x0100–0x0113 flash control & status register FTMRC (continued)
0x0107
FERSTAT
0x0108
FPROT
0x0109
DFPROT
0x010A
FCCOBHI
0x010B
FCCOBLO
0x010C-0x
010F
Reserved
0x0110
FOPT
0x01110x0113
Reserved
R
0
0
0
0
0
0
FPHDIS
FPHS1
FPHS0
0
0
0
CCOB15
CCOB14
CCOB13
CCOB7
CCOB6
0
DFDIF
SFDIF
FPLDIS
FPLS1
FPLS0
DPS3
DPS2
DPS1
DPS0
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
CCOB5
CCOB4
CCOB3
CCOB2
CCOB1
CCOB0
0
0
0
0
0
0
0
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
W
R
FPOPEN
DPOPEN
RNV6
W
R
W
R
W
Table 61. 0x0120 port integration module (PIM) 2 of 2
Address
Name
0x0120
PTIA
0x0121
PTIE
0x01220x017F
Reserved
R
W
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTIA7
PTIA6
PTIA5
PTIA4
PTIA3
PTIA2
PTIA1
PTIA0
0
0
0
0
0
0
PTIE1
PTIE0
0
0
0
0
0
0
0
0
W
R
W
Table 62. 0x01F0–0x01FF clock and power management (CPMU) 2of 2
Address
Name
0x01F0
Reserved
0x01F1
CPMU
LVCTL
0x01F20x01F7
Reserved
0x01F8
CPMU
IRCTRIMH
R
0x01F9
CPMU
IRCTRIML
R
MM912_637D1
Data sheet: Technical data
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVDS
LVIE
LVIF
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
W
TCTRIM[3:0]
IRCTRIM[9:8]
IRCTRIM[7:0]
W
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Table 62. 0x01F0–0x01FF clock and power management (CPMU) 2of 2 (continued)
0x01FA
CPMUOSC
R
OSCE
OSCBW
OSCPINS_
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OSCFILT[4:0]
W
0x01FB
CPMUPROT
0x01FC
Reserved
R
PROT
W
R
0
W
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3
Offset(75)
0x00
R
15
7
0
14
6
0
13
5
0
12
4
0
W
HTIEM
UVIEM
HWRM
0
HTIE
UVIE
0
0
HWR
0
HTF
UVF
HWRF
WDRF
Name
PCR_CTL
PCR Control Register
R
W
0x02
0x03
PCR_SR (hi)
R
PCR Status Register
W
PCR_SR (lo)
R
PCR Status Register
W
11
3
0
10
2
0
9
1
0
8
0
0
PFM[1:0]
OPMM[1:0]
PF[1:0]
OPM[1:0]
HVRF
LVRF
WULTCF
WLPMF
WUPTB2
F
WUPTB1
F
WUPTB0
F
Write 1 will clear the flags
WUAHTH
F
WUCTHF
WUCALF
WULINF
WUPTB3
F
Write 1 will clear the flags
R
0x04
PCR_PRESC
PCR 1.0 ms prescaler
W
PRESC[15:0]
R
W
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
PCR_WUE (hi)
R
Wake-up Enable Register
W
PCR_WUE (lo)
R
Wake-up Enable Register
W
INT_SRC (hi)
R
Interrupt source register
W
INT_SRC (lo)
R
Interrupt source register
W
INT_VECT
R
Interrupt vector register
W
Reserved
R
R
Interrupt mask register
W
INT_MSK (lo)
R
Interrupt mask register
W
Data sheet: Technical data
WUCTH
WUCAL
WULIN
WUPTB3
WUPTB2
WUPTB1
WUPTB0
0
0
0
0
0
0
0
TOV
CH3
CH2
CH1
CH0
LTI
HTI
UVI
0
0
CAL
LTC
CVMI
RX
TX
ERR
0
0
0
0
0
0
0
0
0
0
0
0
TOVM
CH3M
CH2M
CH1M
CH0M
LTIM
HTIM
UVIM
0
0
CALM
LTCM
CVMM
RXM
TXM
ERRM
WULTC
IRQ[3:0]
W
INT_MSK (hi)
MM912_637D1
WUAHTH
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0x0E
0x0F
0x10
Name
TRIM_ALF (hi)
R
Trim for accurate 1.0 ms low freq
clock
W
TRIM_ALF (lo)
R
Trim for accurate 1.0 ms low freq
clock
W
WD_CTL
Watchdog control register
0
W
Reserved
R
0x13
0x14
WD_SR
R
Watchdog status register
W
Reserved
R
Watchdog rearm register
W
Reserved
0x16
Reserved
0x17
Reserved
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
R
R
11
3
10
2
APRESC[12:8]
9
1
8
0
0
0
0
0
0
0
0
WDTOM[2:0]
0
0
0
0
0
0
0
0
0
0
WDOFF
WDWO
0
0
0
0
0
0
0
0
Reserved
WDTO[2:0]
WDR[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LBKDIE
RXEDGIE
SBR12
SBR11
SBR10
SBR9
SBR8
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
ILT
PE
PT
W
R
W
R
SCI Baud Rate Register
W
SCIBD (lo)
R
SCI Baud Rate Register
W
SCIC1
R
SCI Control Register 1
W
SCIC2
R
SCI Control Register 2
W
SCIS1
R
SCI Status Register 1
W
SCIS2
R
SCI Status Register 2
W
SCIC3
R
SCI Control Register 3
W
Data sheet: Technical data
12
4
W
SCIBD (hi)
MM912_637D1
13
5
0
W
WD_RR
0x15
0x18
R
14
6
0
APRESC[7:0]
R
W
0x12
15
7
PRDF
LOOPS
0
0
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
LBKDIF
RXEDGIF
RXINV
RWUID
BRK13
LBKDE
TXINV
ORIE
NEIE
FEIE
R8
T8
0
TXDIR
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 6/2021
RAF
PEIE
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MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
SCID
R
15
7
R7
SCI Data Register
W
T7
T6
T5
T4
TIOS
R
0
0
0
0
Timer Input Capture/Output
Compare Select
W
CFORC
R
Timer Compare Force Register
W
OC3M
R
Name
0
14
6
R6
13
5
R5
12
4
R4
11
3
R3
10
2
R2
9
1
R1
8
0
R0
T3
T2
T1
T0
IOS3
IOS2
IOS1
IOS0
0
0
0
0
FOC3
FOC2
FOC1
FOC0
OC3M3
OC3M2
OC3M1
OC3M0
OC3D3
OC3D2
OC3D1
OC3D0
0
0
0
0
TOV3
TOV2
TOV1
TOV0
0
0
0
0
0
0
0
0
0
0
0
Output Compare 3 Mask Register W
OC3D
R
Output Compare 3 Data Register W
TCNT (hi)
R
Timer Count Register
W
TCNT (lo)
R
Timer Count Register
W
TSCR1
R
Timer System Control Register 1 W
TTOV
R
Timer Toggle Overflow Register
W
TCTL1
R
Timer Control Register 1
W
TCTL2
R
Timer Control Register 2
W
TIE
R
Timer Interrupt Enable Register
W
TSCR2
R
Timer System Control Register 2 W
TFLG1
R
Main Timer Interrupt Flag 1
W
TFLG2
R
Main Timer Interrupt Flag 2
W
TC0 (hi)
R
Timer Input Capture/Output
Compare Register 0
W
TC0 (lo)
R
Timer Input Capture/Output
Compare Register 0
W
MM912_637D1
Data sheet: Technical data
TCNT[15:0]
0
0
0
0
0
0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
0
0
0
0
C3I
C2I
C1I
C0I
0
0
0
TCRE
PR2
PR1
PR0
0
0
0
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
TEN
TOI
0
TOF
TFFCA
TC0[15:0]
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 6/2021
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MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
15
7
Name
TC1 (hi)
R
Timer Input Capture/Output
Compare Register 1
W
TC1 (lo)
R
Timer Input Capture/Output
Compare Register 1
W
TC2 (hi)
R
Timer Input Capture/Output
Compare Register 2
W
TC2 (lo)
R
Timer Input Capture/Output
Compare Register 2
W
TC3 (hi)
R
Timer Input Capture/Output
Compare Register 3
W
TC3 (lo)
R
Timer Input Capture/Output
Compare Register 3
W
TIMTST
R
Timer Test Register
W
Reserved
LTC_CTL (hi)
R
R
R
Life Time Counter control register W
12
4
11
3
10
2
9
1
8
0
TC1[15:0]
TC2[15:0]
TC3[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCBYP
LTCIEM
LTCIE
LTC_SR
R
LTCOF
Life Time Counter status register
W
1 will clr
R
0
Reserved
13
5
0
W
Life Time Counter control register W
LTC_CTL (lo)
14
6
LTCEM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LTCE
W
R
0x3C
LTC_CNT1
Life Time Counter Register
W
LTC[31:16]
R
W
R
0x3E
LTC_CNT0
Life Time Counter Register
W
LTC[15:0]
R
W
MM912_637D1
Data sheet: Technical data
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 6/2021
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45/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
14
6
0
13
5
0
12
4
0
11
3
0
10
2
0
9
1
0
8
0
0
DIR2M
DIR1M
DIR0M
PE3M
PE2M
PE1M
PE0M
DIR2
DIR1
DIR0
PE3
PE2
PE1
PE0
0
0
0
0
PDE3
PUE2
PUE1
PUE0
0
0
0
0
PD3
PD2
PD1
PD0
TCAP3
TCAP2
TCAP1
TCAP0
SCIRX
LINTX
TCOMP3
TCOMP2
TCOMP1
TCOMP0
SCITX
LINRX
TCAP3
TCAP2
TCAP1
TCAP0
SCIRX
LINTX
TCOMP3
TCOMP2
TCOMP1
TCOMP0
SCITX
LINRX
TCAP3
TCAP2
TCAP1
TCAP0
SCIRX
LINTX
WKUP
TCOMP3
TCOMP2
TCOMP1
TCOMP0
SCITX
LINRX
PTWU
PTWU
TCAP3
TCAP2
TCAP1
TCAP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
W
OTIEM
Name
R
0x40
GPIO_CTL
GPIO control register
15
7
0
W
R
0
W
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
GPIO_PUC
R
GPIO pull up/down configuration
W
GPIO_DATA
R
GPIO port data register
W
GPIO_IN0
R
Port 0 input configuration
W
GPIO_OUT0
R
Port 0 output configuration
W
GPIO_IN1
R
Port 1 input configuration
W
GPIO_OUT1
R
Port 1 output configuration
W
GPIO_IN2
R
Port 2 input configuration
W
GPIO_OUT2
R
Port 2 output configuration
W
GPIO_IN3
R
Port 3 input configuration
W
0x4B
Reserved
0x4C
Reserved
0x4D
Reserved
0x4E
Reserved
0x4F
Reserved
0x50
LIN_CTL
LIN control register
R
Data sheet: Technical data
WKUP
0
WKUP
0
0
0
PTBX0
0
0
PTBX1
0
0
PTBX2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXDM
LVSDM
ENM
SRSM[1:0]
TXD
LVSD
EN
SRS[1:0]
W
R
W
R
W
R
W
R
W
R
W
MM912_637D1
0
OTIE
0
0
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46/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0x52
0x53
0x54
0x55
Name
LIN_SR (hi)
R
LIN status register
W
LIN_SR (lo)
R
LIN status register
W
LIN_TX
R
LIN transmit line definition
W
LIN_RX
R
LIN receive line definition
W
0x61
0x62
0x63
9
1
0
8
0
0
RX
TX
FROMPT
B
FROMSCI
TOPTB
TOSCI
Write 1 will clear the flags
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
W
AHCRM
OPTEM
OPENEM
CVMIEM
ETMENM
ITMENM
VMENM
CMENM
R
0
W
AHCR
OPTE
OPENE
CVMIE
ETMEN
ITMEN
VMEN
CMEN
ACQ_SR (hi)
R
AVRF
PGAG
VMOW
CMOW
ETM
ITM
VM
CM
Acquisition status register
W
ACQ_SR (lo)
R
Acquisition status register
W
ACQ_CTL
Acquisition control register
ACQ_ACC1
Acquisition chain control 1
R
W
R
W
ACQ_ACC0
Acquisition chain control 0
0
0
VTH
ETCHOP
ITCHOP
VCHOP
CCHOP
R
0
0
0
0
0
0
0
0
W
TCOMPM
LPFENM
ETCHOP
M
ITCHOPM
CVCHOP
M
AGENM
R
VCOMP
CCOMP
LPFEN
ETCHOP
ITCHOP
CVCHOP
AGEN
R
0
0
0
0
0
0
0
0
W
ZEROM
ECAPM
TADCGM
VADCGM
CADCGM
TDENM
VDENM
CDENM
ZERO
ECAP
TADCG
VADCG
CADCG
TDEN
VDEN
CDEN
0
0
0
0
0
0
0
0
0
R
R
Decimation rate
W
ACQ_BGC
R
BandGap control
W
ACQ_GAIN
R
PGA gain
W
ACQ_GCB
R
GCB threshold
W
Data sheet: Technical data
VCOMPM CCOMPM
TCOMP
ACQ_DEC
MM912_637D1
Write 1 will clear the flags
OPEN
W
0x60
10
2
0
0
W
0x5E
11
3
UV
0
Reserved
0x5C
12
4
0
0
0x57
0x5B
13
5
HF
0
Reserved
0x5A
14
6
0
RDY
0x56
0x58
15
7
OT
BGADC[1:0]
0
BGLDO
0
0
DEC[2:0]
BG3EN
BG2EN
BG1EN
IGAIN[2:0]
D[7:0]
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47/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0x64
0x65
0x66
15
7
Name
ACQ_ITEMP (hi)
R
Internal temperature
measurement
W
ACQ_ITEMP (lo)
R
Internal temperature
measurement
W
ACQ_ETEMP (hi)
R
External temperature
measurement
W
ACQ_ETEMP (lo)
R
0x67
External temperature
measurement
W
0x68
Reserved
0x69
R
14
6
13
5
12
11
4
3
ITEMP[15:8]
8
0
0
0
0
0
0
0
EEMP[15:8]
EEMP[7:0]
0
0
0
0
0
W
ACQ_CURR1
R
Current measurement
W
ACQ_CURR0
Current measurement
9
1
ITEMP[7:0]
CURR[23:16]
R
0x6A
10
2
CURR[15:8]
W
R
CURR[7:0]
W
R
0x6C
ACQ_VOLT
Voltage measurement
VOLT[15:8]
W
R
VOLT[7:0]
W
0x6E
0x6F
ACQ_LPFC
R
0
0
0
0
0
0
0
0
LPFC[3:0]
Low pass filter coefficient number W
Reserved
R
0
W
R
0x70
ACQ_TCMP
Low power trigger current
measurement period
W
TCMP[15:0]
R
W
0x72
0x73
0x74
ACQ_THF
R
Low power current threshold
filtering period
W
Reserved
R
R
I and V chopper control register
W
Data sheet: Technical data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
ACQ_CVCR (hi)
MM912_637D1
THF[7:0]
DBTM[1:0]
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 6/2021
IIRCM[2:0]
PGAFM
© NXP B.V. 2021. All rights reserved.
48/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
Name
ACQ_CVCR (lo)
R
I and V chopper control register
W
ACQ_CTH
R
Low power current threshold
W
Reserved
R
R
Low power Ah counter threshold
W
ACQ_AHTH1 (lo)
R
Low power Ah counter threshold
W
ACQ_AHTH0 (hi)
R
Low power Ah counter threshold
W
ACQ_AHTH0 (lo)
R
Low power Ah counter threshold
W
ACQ_AHC1 (hi)
R
Low power Ah counter
W
ACQ_AHC1 (lo)
R
Low power Ah counter
W
ACQ_AHC0 (hi)
R
Low power Ah counter
W
ACQ_AHC0 (lo)
R
Low power Ah counter
W
LPF_A0 (hi)
R
A0 filter coefficient
W
LPF_A0 (lo)
R
A0 filter coefficient
W
LPF_A1 (hi)
R
A1 filter coefficient
W
LPF_A1 (lo)
R
A1 filter coefficient
W
LPF_A2 (hi)
R
A2 filter coefficient
W
LPF_A2 (lo)
R
A2 filter coefficient
W
Data sheet: Technical data
14
6
0
13
5
12
4
11
3
DBT[1:0]
10
2
9
1
IIRC[2:0]
8
0
PGAF
CTH[7:0]
0
0
0
0
0
0
0
0
W
ACQ_AHTH1 (hi)
MM912_637D1
15
7
0
0
AHTH[30:16]
AHTH[15:0]
AHC[31:24]
AHC[23:16]
AHC[15:8]
AHC[7:0]
A0[15:0]
A1[15:0]
A2[15:0]
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 6/2021
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49/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
15
7
Name
LPF_A3 (hi)
R
A3 filter coefficient
W
LPF_A3 (lo)
R
A3 filter coefficient
W
LPF_A4 (hi)
R
A4 filter coefficient
W
LPF_A4 (lo)
R
A4 filter coefficient
W
LPF_A5 (hi)
R
A5 filter coefficient
W
LPF_A5 (lo)
R
A5 filter coefficient
W
LPF_A6 (hi)
R
A6 filter coefficient
W
LPF_A6 (lo)
R
A6 filter coefficient
W
LPF_A7 (hi)
R
A7 filter coefficient
W
LPF_A7 (lo)
R
A7 filter coefficient
W
LPF_A8 (hi)
R
A8 filter coefficient
W
LPF_A8 (lo)
R
A8 filter coefficient
W
LPF_A9 (hi)
R
A9 filter coefficient
W
LPF_A9 (lo)
R
A9 filter coefficient
W
LPF_A10 (hi)
R
A10 filter coefficient
W
LPF_A10 (lo)
R
A10 filter coefficient
W
LPF_A11 (hi)
R
A11 filter coefficient
W
LPF_A11 (lo)
R
A11 filter coefficient
W
MM912_637D1
Data sheet: Technical data
14
6
13
5
12
4
11
3
10
2
9
1
8
0
A3[15:0]
A4[15:0]
A5[15:0]
A6[15:0]
A7[15:0]
A8[15:0]
A9[15:0]
A10[15:0]
A11[15:0]
All information provided in this document is subject to legal disclaimers.
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© NXP B.V. 2021. All rights reserved.
50/396
MM912_637
NXP Semiconductors
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
15
7
Name
LPF_A12 (hi)
R
A12 filter coefficient
W
LPF_A12 (lo)
R
A12 filter coefficient
W
LPF_A13 (hi)
R
A13 filter coefficient
W
LPF_A13 (lo)
R
A13 filter coefficient
W
LPF_A14 (hi)
R
A14 filter coefficient
W
LPF_A14 (lo)
R
A14 filter coefficient
W
LPF_A15 (hi)
R
A15 filter coefficient
W
LPF_A15 (lo)
R
A15 filter coefficient
W
COMP_CTL
Compensation control register
0xA2
0xA3
R
Compensation status register
W
COMP_TF
R
Temperature filtering period
W
11
3
10
2
9
1
8
0
A14[15:0]
A15[15:0]
W
COMP_SR
12
4
A13[15:0]
0
W
13
5
A12[15:0]
R
R
14
6
0
0
0
0
0
BGCALM[1:0]
PGAZM
PGAOM
DIAGVM
DIAGIM
CALIEM
BGCAL[1:0]
PGAZ
PGAO
DIAGV
DIAGI
0
PGAOF
0
0
0
0
BGRF
CALIE
0
CALF
Write 1 will clear the flags
0
0
0
0
0
TMF[2:0]
R
0xA4
COMP_TMAX
Max temp before recalibration
W
TCMAX[15:0]
R
W
R
0xA6
COMP_TMIN
Min temp before recalibration
W
TCMIN[15:0]
R
W
0xA8
Reserved
0xA9
Reserved
MM912_637D1
Data sheet: Technical data
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
0xAA
0xAB
15
7
Name
COMP_VO
R
Offset voltage compensation
W
COMP_IO
R
Offset current compensation
W
R
0xAC
COMP_VSG
Gain voltage compensation
vsense channel
14
6
13
5
12
4
Reserved
0xAF
Reserved
0xB0
0
0
0
0
R
R
VSGC[7:0]
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
R
0
0
0
0
W
R
R
0xB4
0
0
0
0
R
0xB6
0
0
0
0
W
R
0xB8
COMP_IG64
Gain current compensation 64
0
0
0
0
W
R
0xBA
COMP_IG128
Gain current compensation 128
0
0
0
Data sheet: Technical data
0
W
R
IGC128[9:8]
IGC128[7:0]
W
MM912_637D1
IGC64[9:8]
IGC64[7:0]
W
R
IGC32[9:8]
IGC32[7:0]
W
R
IGC16[9:8]
IGC16[7:0]
W
COMP_IG32
Gain current compensation 32
IGC8[9:8]
IGC8[7:0]
W
R
IGC4[9:8]
IGC4[7:0]
W
COMP_IG16
Gain current compensation 16
VSGC[9:8]
W
R
0xB2
0
8
0
COC[7:0]
W
COMP_IG8
Gain current compensation 8
0
9
1
W
R
COMP_IG4
Gain current compensation 4
10
2
VOC[7:0]
W
0xAE
11
3
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
R
0xBC
COMP_IG256
Gain current compensation 256
15
7
0
14
6
0
13
5
0
R
R
0xBE
0
0
0
R
0xC2
0
0
0
R
0xC4
0
0
0
R
0xC6
0
0
0
R
0xC8
0
0
0
R
0xCA
0
0
0
R
0xCC
0
0
0
R
Data sheet: Technical data
PGAOC8[10:8]
0
PGAOC16[10:8]
0
0
PGAOC32[10:8]
0
0
PGAOC64[10:8]
0
0
PGAOC128[10:8]
PGAOC128[7:0]
0
0
0
0
0
W
R
PGAOC256[10:8]
PGAOC256[7:0]
W
MM912_637D1
0
W
R
PGAOC4[10:8]
PGAOC64[7:0]
W
COMP_PGAO256
Offset PGA compensation 256
0
W
R
IGC512[9:8]
PGAOC32[7:0]
W
COMP_PGAO128
Offset PGA compensation 128
0
W
R
0
PGAOC16[7:0]
W
COMP_PGAO64
Offset PGA compensation 64
0
W
R
IGC256[9:8]
PGAOC8[7:0]
W
COMP_PGAO32
Offset PGA compensation 32
0
W
R
8
0
PGAOC4[7:0]
W
COMP_PGAO16
Offset PGA compensation 16
0
W
R
9
1
IGC512[7:0]
W
COMP_PGAO8
Offset PGA compensation 8
0
W
R
0xC0
10
2
0
IGC256[7:0]
W
COMP_PGAO4
Offset PGA compensation 4
11
3
0
W
W
COMP_IG512
Gain current compensation 512
12
4
0
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
R
0xCE
COMP_PGAO512
Offset PGA compensation 512
15
7
0
14
6
0
13
5
0
0xD1
0xD2
0xD3
R
COMP_ITO
R
Internal temp. offset
compensation
W
COMP_ITG
R
COMP_ETO
R
External temp. offset
compensation
W
COMP_ETG
R
External temp. gain
compensation
W
Reserved
0xD5
Reserved
0xD6
Reserved
0xD7
Reserved
0xD8
Reserved
0xD9
Reserved
0xDA
Reserved
0xDB
Reserved
0xDC
Reserved
0xDD
Reserved
0xDE
Reserved
MM912_637D1
Data sheet: Technical data
10
2
R
9
1
8
0
PGAOC512[10:8]
PGAOC512[7:0]
ITOC[7:0]
ITGC[7:0]
Internal temp. gain compensation W
0xD4
11
3
0
W
W
0xD0
12
4
0
ETOC[7:0]
ETGC[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
0xDF
Reserved
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
R
R
Trim bandgap 0
W
TRIM_BG0 (lo)
R
Trim bandgap 0
W
TRIM_BG1 (hi)
R
Trim bandgap 1
W
TRIM_BG1 (lo)
R
Trim bandgap 1
W
TRIM_BG2 (hi)
R
Trim bandgap 2
W
TRIM_BG2 (lo)
R
Trim bandgap 2
W
TRIM_LIN
R
Trim LIN
W
TRIM_LVT
R
Trim low voltage threshold
W
TRIM_OSC (hi)
R
Trim LP oscillator
W
TRIM_OSC (lo)
R
Trim LP oscillator
W
Reserved
0xEB
Reserved
0xEC
Reserved
0xED
Reserved
0xEE
Reserved
0xEF
Reserved
0xF0
Reserved
MM912_637D1
Data sheet: Technical data
14
6
0
0
0
0
0
UBG3
DBG3
0
0
13
5
0
12
4
0
11
3
0
10
2
0
9
1
0
8
0
0
W
TRIM_BG0 (hi)
0xEA
15
7
0
R
0
TCIBG2[2:0]
TCIBG1[2:0]
IBG2[2:0]
IBG1[2:0]
TCBG2[2:0]
TCBG1[2:0]
0
0
SLPBG[2:0]
V1P2BG2[3:0]
V1P2BG1[3:0]
V2P5BG2[3:0]
V2P5BG1[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LIN
LVT
LPOSC[12:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
W
R
W
R
W
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
0xF1
Reserved
0xF2
Reserved
0xF3
Reserved
0xF4
Reserved
0xF5
Reserved
0xF6
Reserved
0xF7
Reserved
0xF8
Reserved
0xF9
Reserved
0xFA
Reserved
0xFB
Reserved
0xFC
Reserved
0xFD
Reserved
0xFE
Reserved
0xFF
Reserved
R
15
7
0
14
6
0
13
5
0
12
4
0
11
3
0
10
2
0
9
1
0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Notes
75. Register Offset with the “lo” address value not shown have to be accessed in 16-Bit mode. 8-Bit access will not function.
4.2
4.2.1
MM912_637 - analog die overview
Introduction
MM912_637D1
Data sheet: Technical data
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VDDL
DGND
VDDH
VDDX
PTB3
PTB2
PTB1
PTB0
The MM912_637 analog die implements all system base functionality to operate the integrated microcontroller, and delivers application
specific input capturing.
Analog
VSUP
Watchdog
GPIO
Digital
Bias
Regulator(s)
VDDA
GNDA
MMC
Oscillator
SCI
LIN
LIN
LGND
D2DDAT0..7
MCU
Die
D2D
Interface
Internal Bus
D2DCLK
D2DINT
Wake Up /
Power Down
Timer
Fuse
Box
VFUSE
GNDSUB
Temperature
Measurement
ADCGND
TSUP
VTEMP
Battery Voltage Battery Current
Measurement
Measurement
VSENSE
Test
Interface
ISENSEH
TCLK
TEST_A
Gain and offset
compensation
ISENSEL
RESET_A
Gain and offset compensation
Prog. Low pass filter
DECV
DECC
VOPT
Interrupt
Control
Figure 14. Analog die block overview
The following chapters describe the analog die functionality on a module by module basis.
4.2.2
Analog die options
NOTE
This document describes the features and functions of Analog Option 2 (all modules available and
tested). Beyond this chapter, there will be no additional note or differentiation between the different
implementations.
The following section describes the differences between analog die options 1 and 2.
Table 64. Analog options
Feature
Analog option 1
Analog option 2
Not Characterized or Tested
Fully Characterized and Tested
External Wake-up (PTB3/L0)
No
Yes
External Temperature Sensor Option (VTEMP)
No
Yes
Optional 2nd External Voltage Sense Input (VOPT)
No
Yes
Cranking Mode
4.2.2.1
Cranking mode
For devices with Analog Option 1 (Cranking mode not characterized), the following considerations are to be made:
4.2.2.1.1
Data sheet considerations
MM912_637D1
Data sheet: Technical data
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In Analog Option 1 devices, Operation in Cranking mode is neither characterized not tested. All data sheet parameters and descriptions
relating to Cranking mode operation apply to Analog Option 2 devices only.
4.2.2.2
External wake-up (PTB3/L0)
For devices with Analog Option 1 (External Wake-up not available), the following considerations are to be made:
4.2.2.2.1
Register considerations
Table 65. Wake-up enable register (PCR_WUE (hi))
Offset (76) 0x06
Access: User read/write
R
W
Reset
7
6
5
4
3
2
1
0
WUAHTH
WUCTH
WUCAL
WULIN
WUPTB3
WUPTB2
WUPTB1
WUPTB0
0
0
0
0
0
0
0
0
Notes
76. Offset related to 0x0200 for blocking access and 0x300 for non-blocking access within the global address space.
For Analog Option 1 devices, WUPTB3 must be set to 0 (wake-up on a GPIO 3 event disabled).
4.2.2.3
External temperature sensor option (VTEMP)
For devices with Analog Option 1 (External Temperature Sensor Option not available), the following considerations are to be made:
4.2.2.3.1
Pinout considerations
Pin
Pin name for option 2
Pin name for option 1
Comment
28
VTEMP
NC
NC pin should be connected to GND
29
TSUP
NC
Pin should be left unconnected
4.2.2.3.2
Register considerations
Table 66. Acquisition control register (ACQ_CTL)
Offset (77),(78) 0x58
Access: User read/write
15
14
13
12
11
10
9
8
R
0
0
0
0
0
0
0
0
W
AHCRM
OPTEM
OPENEM
CVMIEM
ETMENM
ITMENM
VMENM
CMENM
Reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
OPTE
OPENE
CVMIE
ETMEN
ITMEN
VMEN
CMEN
0
0
0
0
0
0
0
R
0
W
AHCR
Reset
0
Notes
77. Offset related to 0x0200 for blocking access and 0x300 for non-blocking access within the global address space.
78. This register is 16-bit access only.
For Analog Option 1 devices, ETMEN must be set to 0 (external temperature measurement disabled).
MM912_637D1
Data sheet: Technical data
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4.2.2.4
Optional 2nd external voltage sense input (VOPT)
For devices with Analog Option 1 (Optional 2nd External Voltage Sense Input not available), the following considerations are to be made:
4.2.2.4.1
Pinout considerations
Pin
Pin name for option 2
Pin name for option 1
Comment
28
VOPT
NC
NC pin should be connected to GND
4.2.2.4.2
Register considerations
Table 67. Acquisition control register (ACQ_CTL)
Offset (79),(80) 0x58
Access: User read/write
15
14
13
12
11
10
9
8
R
0
0
0
0
0
0
0
0
W
AHCRM
OPTEM
OPENEM
CVMIEM
ETMENM
ITMENM
VMENM
CMENM
Reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
OPTE
OPENE
CVMIE
ETMEN
ITMEN
VMEN
CMEN
0
0
0
0
0
0
0
R
0
W
AHCR
Reset
0
Notes
79. Offset related to 0x0200 for blocking access and 0x300 for non-blocking access within the global address space.
80. This register is 16-bit access only.
For Analog Option 1 devices, OPTE must be set to 0 (VSENSE routed to ADC).
4.3
4.3.1
Analog die - power, clock and resets - PCR
Introduction
The following chapter describes the MM912_637’s system base functionality primary location on the analog die. The chapter is divided in
the following sections:
1. 4.3.2, “Device operating modes"
2. 4.3.3, “Power management"
3. 4.3.4, “Wake-up sources"
4. 4.3.5, “Device clock tree"
5. 4.3.6, “System resets"
6. 4.3.7, “PCR - memory map and registers"
4.3.2
Device operating modes
The MM912_637 features three main operation modes: normal operation, stop mode, and sleep mode. The full signal conditioning and
measurements are permanently running in normal operation mode. The total current consumption of the MM912_637 is reduced in the
two low power modes.
The analog die of the MM912_637 is still partially active and able to monitor the battery current, temperature, activities on the LIN interface
and L0 terminal, during both low power modes.
4.3.2.1
Operating mode overview
MM912_637D1
Data sheet: Technical data
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•
•
•
•
•
•
•
Normal Mode
— All device modules active
— Microcontroller fully supplied
— D2DCLK active analog die clock source
— Window watchdog clocked by the low power oscillator (LPCLK) to operate on independent clock
Stop Mode
— MCU in low power mode, MCU regulator supply (VDDX) with reduced current capability
— D2D interface supply disabled (VDDH=OFF)
— Unused analog blocks disabled
— Watchdogs = OFF
— LIN wake-up, calibration request wake-up, cyclic wake-up, external wake-up, current threshold wake-up, and lifetime
counter wake-up optional
— Current Measurement / current averaging and temperature measurement optional
Sleep Mode
— MCU powered down (VDDH and VDDX = OFF)
— Unused Analog Blocks disabled
— Watchdogs = OFF
— LIN wake-up, calibration request wake-up, cyclic wake-up, external wake-up, current threshold wake-up, and lifetime
counter wake-up optional
— Current measurement / current averaging and temperature measurement optional
Intermediate Mode
— Every transition from Stop or Sleep into Normal mode will go through an intermediate mode where the analog die clock is
not yet switched to the D2D clock. If required, the MM912_637 analog die can be put back to low power mode without
changing the frequency domain.
Reset Mode
— Every reset source within the analog die will bring the system into a Reset state
Power On Reset Mode
— For both low voltage thresholds are defined to indicate a loss of internal state.
Cranking Mode(81)
— Special Mode implemented to guarantee the RAM content being valid though very low power conditions.
Notes
81. Not available on all device derivatives
4.3.2.2
Operating mode transitions
The device operating modes are controlled by the microcontroller, as well as external and internal wake-up sources. Figure 15 shows the
basic principal.
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POR
ANALOG: VDDL > VPORH
MCU: VDDRX>VPORD
ANALOG: VDDL < VPORL
MCU: VDDRX ON
VUVIL
Under Voltage IRQ
(UVI) issued.
Inactive during Stop /
Sleep
Handle IRQ, prepare
for Cranking Mode
Inactive during Stop /
Sleep
VLVIA
Handle IRQ, prepare
for Cranking Mode
Inactive during Stop /
Sleep
Under Voltage IRQ
(UVI) issued.
Cranking Mode Entry
without MCU
interaction. MCU will
stay in STOP mode or
turned off.
VUVCIL
Inactive for Non
Cranking Mode Device
Option
Inactive for Non
Cranking Mode Device
Option
MCU in LVR, Analog
Die remains in Low
Power Mode
Inactive during Stop /
Sleep
MCU initiates rapid shutdown
to Cranking Mode (OPM=11) and
enters STOP.
CRANKING MODE
(MCU = Stop or Off,
Analog = Cranking Mode
LPOSC gated => operation stopped)
VSUP Decrease
Normal /
Intermediate
Mode
Device with Cranking Mode Disabled
Inactive during Cranking Mode
VLVRA
Inactive during Cranking Mode
VLVRXL
LOW VOLTAGE RESET at VDDX
=> Analog Die + MCU in Reset Mode
Inactive during Cranking Mode
VLVRHL
VLVRAL
System remains in Reset
Mode
MCU POR, RAM invalid,
Analog Die Remains in
Cranking Mode
VPORA
MCU POR, RAM invalid, Both
Dice Remain in Reset Mode
Inactive for Cranking Mode
Device Option
VPORL
Analog Die Power On Reset
Analog Die Power On Reset
VPORCL
Inactive for Non - Cranking
Mode Device Option
Figure 18. Power down sequence
MM912_637D1
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4.3.4
Wake-up sources
Several wake-up sources have been implemented in the MM912_637, to exit from Sleep or Stop mode. Figure 19 shows the wake-up
sources and the corresponding configuration and status bits.
To indicate the internal wake-up signal, a routing of the internal wake-up signal to the PTBx output (WKUP) is implemented. See
Section 4.11, “General purpose I/O - GPIO", for additional details on the required configuration.
GPIO
TIM4CH
WKUP
TCOMP3..0
PTB0
I/O
Output Compare CH3
WUPTB0
TCOMP3..0
Output Compare CH2
PTB1
I/O
Output Compare CH1
Output Compare CH0
Sytem
Wake
Up
WUPTB1
TCOMP3..0
PTB2
I/O
WUPTB2
=1
WLPMF
WUPTB0F
PTB3
I/O
PTWU
WUPTB1F
L0
WUPTB3
WUPTB2F
WUPTB3F
WULINF
LIN
WULIN
WUAHTHF
WUCTHF
LIN Wake Up detected
WUCALF
Current Trigger
Current Accumulator
Threshold reached
Current
Threshold reached
Calibration Request
Life Time Counter
WUAHTH
WULTCF
WUCTH
WUCAL
WULTC
Life Time Counter
Overflow
Figure 19. Wake-up sources
4.3.4.1
4.3.4.1.1
Wake-up source details
Cyclic current acquisition/calibration temperature check
A configurable (ACQ_TCMP) independent low power mode counter/trigger, based on the ALFCLK, has been implemented to trigger a
cyclic current measurement during the low power modes. To validate that the temperature is still within the calibration range, the
temperature measurement can be enabled during this event as well.
As a result of the cyclic conversions, three wake-up conditions are implemented.
•
Current Threshold Wake-up
•
Current Averaging Wake-up
•
Calibration Request Wake-up
The configuration of the counter and the cyclic measurements is part of the acquisition paragraph (see Section 4.8, “Channel acquisition").
The actual cyclic measurement does not wake-up the microcontroller unless one of the three wake-up conditions become valid.
4.3.4.1.1.1
Current threshold wake-up
Every cyclic current measurement result (absolute content of the ADC result I_CURR register) is compared with a programmable
unsigned current threshold (CTH in the ACQ_CTH register).
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The comparison is done with the CTH content left - shifted by 1, as shown in Table 69.
Table 69. Current Threshold Comparison
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
CTH[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ABS(CURR[23:0])
X
8
7
6
5
4
CTH[7:0]
3
2
1
0
0
ABS(CURR[23:0])
If the absolute result is greater or equal to the programmed and shifted threshold, a filter counter is incremented (decremented if below).
If the filter counter (8-Bit) reaches the programmable low power current threshold filtering period (ACQ_THF), a wake-up initiated if the
Current Threshold Wake-up is enabled (WUCTH). The filter counter is reset every time a low power mode is entered. The implementation
is shown in Figure 20.
The wake-up source is flagged with the WUCTHF Bit.
Figure 20. Current threshold - wake-up counter
4.3.4.1.1.2
Current ampere hour threshold wake-up
As shown in Figure 21, every cyclic current measurement (signed content of the ADC result ACQ_CURR register) is added to the 32-Bit
(signed) current accumulator (ACQ_AHC) (both in two’s complement format). If the absolute accumulator value reaches (|ACQ_AHC|
ACQ_AHTH), the absolute programmable 31-Bit current threshold (ACQ_AHTH), a wake-up is initiated if the Current AH Threshold
Wake-up is enabled (WUAHTH). The accumulator could be reset by writing 1 into the AHCR register.
The Ampere Hour Counter is counting after wake-up. In normal mode, the accumulator register ACQ_AHC can be read out anytime. The
wake-up source is flagged with the WUAHTHF Bit.
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Ah counter
Accu
threshold
(progr.)
actual
measured
current
measurement
interval
uC
wake-up
t
start low-power mode = reset of
Ah counter
Figure 21. Ah counter function
4.3.4.1.1.3
Calibration request wake-up
Once the temperature measured during the cyclic sense is indicating a potential “out of calibration” situation, a wake-up is issued if the
Calibration Request Wake-up is enabled (WUCAL). For additional details, refer to Section 4.8.5, “Calibration". The wake-up source is
flagged with the WUCALF Bit.
4.3.4.1.2
Timed wake-up
To generate a programmable wake-up timer, the integrated 4 Channel Timer Module is supplied, during both low power modes and
running on the ALFCLK clock. To wake-up from one of the low power modes, the output compare signal (OC) of any of the 4 channels
can be routed to the PTB[2:0] logic (standard feature also in Normal mode). Enabling the corresponding Wake-up Enable Bit (WUPTBx)
will generate the wake up, once the timer output compare becomes active.
NOTE
Only the internal GPIO logic is active during the low power modes. The Port I/O structures will not be
active.
To allow an accurate wake-up configuration during the clock transition, the timer should be configured before entering one of the low power
modes, without the Timer Enable Bit (TEN) being set. Setting the Timer Wake-up Enable Bit (WUPTB) will enable the TIMER interrupts
as wake-up sources, and cause the Timer Enable Bit (TEN) to be set, once the timer clock domain was changed to the ALFCLK clock
supplied by LPOSC.
During low-power mode, only current and temperature measurements are performed, so only the current measurement channel is active
with the temperature channel being optional - the voltage measurement channel is inactive. To reduce further the power consumption,
only triggered current measurements are done. For this purpose, an independent Timer Module is used to periodically start a current
measurement after a programmable time (ACQ_TCMP).
4.3.4.1.3
Wake-up from LIN
During Low Power mode, operation of the transmitter of the physical layer is disabled. The receiver remain, active and able to detect
wake-up events on the LIN bus line. For further details, refer to Section 4.12, “LIN". A dominant level longer than tWUPF followed by a rising
edge, will generate a wake-up event if the WULIN is enabled. The wake-up source is flagged with the WULINF Bit.
NOTE
If the LIN module is disabled (LIN_CTL:EN=0), no wake-up will be issued after the dominant to
recessive transition, when the device goes to low power mode, while the LIN bus is in the DOMINANT
STATE.
If the LIN module is enabled (LIN_CTL:EN=1), the device will wake-up after the dominant to recessive
transition, when the device goes to low power mode, while the LIN bus is in the DOMINANT STATE.
A full dominant -> recessive -> dominant sequence, during low power mode, will wake-up the device
in both cases.
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4.3.4.1.4
Wake-up on wake-up pin high level
Once a Wake-up signal (high level) is detected on the PTB3/L0 input, with the Wake-up Enable Bit (WUPTB3) and the port configuration
bit (PTWU) set, a wake-up is issued. The wake-up source is flagged with the WUPTB3F Bit.
4.3.4.1.5
Wake-up on life time counter overflow
The life time counter continues to run during low power mode, if configured. Once the counter overflows with the life time counter wake-up
enabled (WULTC=1), a wake-up is issued. The wake-up source is flagged with the WULTC Bit. Life Time Counter has to be configured in
Normal mode only.
4.3.4.1.6
General wake-up indicator
To indicate the system has been awakened after power up, the WLPMF flag will be set.
4.3.5
4.3.5.1
Device clock tree
Clock scheme overview
There are two system oscillators implemented. The low power oscillator is located on the analog die, and is supplied permanently and has
a nominal frequency of fOSCL (512 kHz), providing a LPCLK clock signal. It is primarily used in low power mode, and as an independent
clock source for the watchdog during Normal mode.
The high power oscillator is basically the internal or external microcontroller oscillator (active only during normal mode). The high power
oscillator is distributed to the analog die via the D2DCLK (via configurable MCU prescalers), and there it’s divided into two clocks
(D2DSCLK and D2DFCLK), based on the PRESC[15:0] prescaler. For the D2DSCLK, an additional 2 Bit divider PF[1:0] is implemented
(87)
. During Normal mode, D2DSCLK is continuously synchronizing the LPCLK, to create the accurate ALFCLK (See Section 4.3.5.2,
“ALFCLK calibration"), D2DCLK is the clock source of the TIM16B4C (Timer), and S08SCIV4 (SCI) module with a fixed by 4 divider.
Notes
87. PF[1:0] is not implemented as a simple divider. To accomplish a D2DSCLK period ranging from 1.0 ms to 8.0 ms, the following scheme is used: 00 1; 01 - 2; 10 - 4; 11 - 8.
D2DSCLK - D2D Slow Clock (1... 0.125 kHz)
Eqn. 1
D2DCLK
D2DSCLK = ------------------------------------------------------------------------
PF 1 0
2
PRESC 15 0
D2DFCLK - D2D Fast Clock (512 kHz)
Eqn. 2
D2DCLK
D2DFCLK = --------------------------------------------------------------------------------------
2 PRESC 15 10 + PRESC 9
During low power mode, D2DCLK is not available. The low power oscillator is the only system clock. Figure 22 and Figure 23 show the
different clock sources for normal and low power mode.
NOTE
D2DFCLK has to be set to match 512 kHz, resulting in D2DSCLK being 1.0, 2.0, 4.0, or 8.0 kHz,
based on PF[1:0]
The minimum value for PRESC[15:0] has to be 0x0400. Any value lower than 0x0400 will result in
faulty behavior and is not recommended. Values of 0x0003 or less are not stored by the internal logic.
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LPOSC
(fOSCL)
LPCLK
WDTO[2:0]=100
tIWDTO
WDTO[2:0]
tWDTO
LP CLK Synch
D2DSCLK
trim_lposc
ALFCLK
Life Time Counter
PF[1:0]
D2DFCLK
D2D Interface
Window
Watchdog
Channel
Acquisition
PRESC[15:0]
D2DCLK
[15:10]
TIM16B4C
(Timer)
[9:0]
DIV4
S08SCIV4
(SCI)
Figure 22. Clock tree overview - normal mode
LPOSC
LPCLK
LP CLK Synch
ALFCLK
Life Time Counter
TIM16B4C
(Timer)
trim_lposc
Current Trigger
Channel
Acquisition
Figure 23. Clock tree overview - low power modes
4.3.5.2
ALFCLK calibration
To increase the accuracy of the 1.0 kHz (or 2.0, 4.0, 8.0 kHz based on PF[1:0]) system clock (ALFCLK), the low power oscillator (LPCLK)
is synchronized to the more precise D2DCLK, via the D2DSCLK signal. The “Calibrated Low Power Clock” (ALFCLK) could be trimmed
to the D2DCLK accuracy plus a maximum error adder of 1 LPCLK period, by internally counting the number of periods of the LPCLK
(512 kHz) during a D2DSCLK period. The APRESC[12:0] register will represent the calculated internal prescaler. The PRDF bit (Prescaler
Ready flag) will indicate the synchronization complete after a power up or prescaler (PRESC/PF) change.
The adjustment is continuously performed during Normal mode. During low power mode (STOP or SLEEP), the last adjustment factor
would be used.
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D2DCLK
PRESC[15:0]+PF[1:0] Counter based ms clock (D2DSCLK) period
LPCLK
1
2
3
4
5
6
7
APRESC[12:0]
0x0200 (512d) default
PRDF
0
8
9
0x0009 (9d)
1
Synch
Start
Synch
Finished
Figure 24. ALF clock calibration procedure during normal mode
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
LPCLK
PRDF
APRESC[12:0]
0
1
?
0x0009 (9d)
ALFCLK
Figure 25. ALFCLK after calibration
4.3.5.3
Recommended clock settings
Considering the system is running on the internal oscillator, Table 70 shows the recommended clock settings to achieve the optimal
512 kHz D2DFCLK. For details on the MCU divider settings, including POSTDIV and SYNDIV, see Section 4.23, “S12 clock, reset, and
power management unit (9S12I128PIMV1)". The D2D initiator module includes D2DCLKDIV see Section 4.26, “MCU - die-to-die initiator
(9S12I128PIMV1)".
30.720
15.360
10.240
14.336
7.168
9.216
13.312
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0
0
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15=32.768
16=34.816
17=36.864
18=38.912
19=40.960
20=43.008
21=45.056
22=47.104
23=49.152
24=51.200
25=53.248
0
27.648
26.624
26=55.296
0
29.696
28.672
27=57.344
0
PRESC[15:9]
(dec)(88)
31.744
28=59.392
0
29=61.440
8.192
30=63.488
31=65.536
16.384
POSTDIV for (SYNDIV=fVCO in MHz)
D2DCLKDIV=4
D2DCLKDIV=2
32.768
D2DCLKDIV=3
D2DCLKDIV=1
(fBUS)
fD2D / MHz
Divider for(88)
D2DFCLK=512kHz
Table 70. Recommended clock settings
64
63;64
62
61;62
60
59;60
58
57;58
56
55;56
54
53;54
52
51;52
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24.576
12.288
8.192
6.144
11.264
7.168
10.240
5.120
0
0
9.216
6.144
0
0
8.192
15.360
14.336
4.096
1
5.120
0
1
7.168
1
13.312
12.288
1
6.144
4.096
3.072
1
11.264
10.240
1
5.120
9.216
8.192
2
1
3.072
4.096
2
2.048
2
1
3
3.072
2.048
2
4
5.120
4.096
1
3
7.168
6.144
15=32.768
0
17.408
16.384
16=34.816
17=36.864
0
19.456
18.432
18=38.912
19=40.960
20=43.008
0
21.504
20.480
21=45.056
0
23.552
22.528
22=47.104
23=49.152
0
3
5
2.048
4
7
3.072
6
9
2.048
15
2
5
8
14
13
3
4
7
12
11
6
10
3
5
9
8
7
PRESC[15:9]
(dec)(88)
25.600
24=51.200
25=53.248
26=55.296
27=57.344
28=59.392
29=61.440
30=63.488
31=65.536
POSTDIV for (SYNDIV=fVCO in MHz)
D2DCLKDIV=4
D2DCLKDIV=3
D2DCLKDIV=2
D2DCLKDIV=1
(fBUS)
fD2D / MHz
Divider for(88)
D2DFCLK=512kHz
Table 70. Recommended clock settings (continued)
50
49;50
48
47;48
46
45;46
44
43;44
42
41;42
40
39;40
48
47;48
36
35;36
34
33;34
32
31;32
30
29;30
28
27;28
26
25;26
24
23;24
22
21;22
20
19;20
18
17;18
16
15;16
14
13;14
12
11;12
10
9;10
8
7;8
6
5;6
4
4
Notes
88. For D2DCLKDIV=1
4.3.6
System resets
To guarantee safe operation, several RESET sources have been implemented in the MM912_637 device. Both the MCU and the analog
die are designed to initiate reset events on internal sources and the MCU is capable of being reset by external events including the analog
die reset output. The analog die can be reset through RESETA in stop and cranking mode only. In normal mode, the MCU can reset the
analog die only by writing 1 into HWR bit (remind the mask bit HWRM).
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4.3.6.1
Device reset overview
RESET
RESET_A
The MM912_637 reset concept includes two external reset signals, RESET (MCU) and RESET_A (analog Die). Figure 26 illustrates the
general configuration.
Reset Module
Low Voltage
Reset (LVR)
Reset Module
Power-On Reset
(POR)
External pin
RESET
Illegal Address
Reset
Clock monitor
reset
Hardware Reset
Watchdog Reset
Low Voltage
Reset
Thermal
Shutdown Reset
COP watchdog
reset
MCU
Analog Die
Figure 26. Device reset overview
Both RESET and RESET_A signals are low active I/Os, based on the 5.0 V supply (VDDRX for RESET and VDDX for RESET_A).
4.3.6.2
Analog die reset implementation
There are 7 internal reset sources implemented in the analog die of the MM912_637 that causing the internal analog die status to be reset
to default (Internal analog RST), and to trigger an external reset, activating the RESET_A pin. In addition, during stop and cranking mode,
an external reset at the RESET_A pin will also reset the analog die.
VDDLR
VDDHR
1
0
RESET_A
0
1
WDR
tRSTRT
HWR
TSDR
VDDXR
VDDAR
LPM
Cranking
Mode
1
0
Measure
during LPM
LPM = Low Power Mode
Figure 27. Analog die reset implementation
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The WDR and HWR will issue a reset on the RESET_A pin during tRSTRT (see Table 30). The other reset VDDLR, VDDHR, VDDXR,
VDDAR, and TSDR will drive the RESET_A pin as long as the condition is present. During cranking mode (89), only the VDDLR is active.
During Low Power modes, only VDDXR and VDDAR are active reset sources. VDDAR is only active during active measurement in LPM.
VDDXR and VDDAR are not active in Normal mode.
Notes
89. Not available on all device derivatives
4.3.6.3
•
•
•
•
•
Reset source summary
HWR - Hardware Reset
— Forced internal reset caused by writing the HWR bit in the PCR_CTL register. The source will be indicated by the HWRF bit.
WDR - Watchdog Reset
— Window watchdog failure. The source will be indicated by the WDRF bit.
LVR - Low Voltage Reset
— The Voltage at the VDDL, VDDH, VDDX, or VDDA has dropped below its reset threshold level. The source will be indicated
for the VDDL by the LVRF + HVRF, for the VDDA by the AVRF, and for the VDDH by the HVRF bit. VDDX resets are not
indicated via individual reset flags. See Figure 27 for dependencies.
TSDR - Temperature Shutdown Reset
— The critical shutdown temperature threshold has been reached. VDDA, VDDX, and VDDH will be disabled as long as the
overtemperature condition is pending(90) and the reset source is indicated by the HTF bit.
External Reset
— During stop and cranking(90) mode, a low signal at the RESET_A pin will reset the analog die. Since this condition can only
be initiated by the microcontroller, no specific indicator flag is implemented.
Notes
90. Resulting in a VDDH Low Voltage Reset taking over the reset after the 2 LPCLK reset pulse
TSDR
HTF
WDR
WDRF
HWR
HWRF
VDDHR
HVRF
VDDLR
LVRF
VDDAR
AVRF
VDDXR
No Flag Indicator
Figure 28. Reset status information
4.3.7
4.3.7.1
PCR - memory map and registers
Overview
This section provides a detailed description of the memory map and registers.
4.3.7.2
Module memory map
The memory map for the Analog Die - Power, Clock and Resets - PCR module is given in Table 63
Table 71. Module Memory Map
Offset
Name
(91),(92)
0x00
PCR_CTL
PCR Control Register
7
Data sheet: Technical data
5
4
3
0
R
0
0
0
0
W
HTIEM
UVIEM
HWRM
0
HTIE
UVIE
0
0
HWR
0
R
W
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2
1
0
0
0
0
PFM[1:0]
OPMM[1:0]
PF[1:0]
OPM[1:0]
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Table 71. Module Memory Map
Offset
Name
(91),(92)
0x02
0x03
PCR_SR (hi)
R
PCR Status Register
W
PCR_SR (lo)
R
PCR Status Register
W
PCR_PRESC
PCR 1.0 ms prescaler
W
7
6
5
4
3
2
1
0
HTF
UVF
HWRF
WDRF
HVRF
LVRF
WULTCF
WLPMF
WUAHTHF
WUCTHF
WUCALF
WUPTB2F
WUPTB1F
WUPTB0F
Write 1 will clear the flags
WULINF
WUPTB3F
Write 1 will clear the flags
R
0x04
PRESC[15:0]
R
W
0x06
0x07
0x0E
0x0F
PCR_WUE (hi)
R
Wake-up Enable Register
W
PCR_WUE (lo)
R
Wake-up Enable Register
W
TRIM_ALF (hi)
R
Trim for accurate 1.0 ms low freq clock
W
TRIM_ALF (lo)
R
Trim for accurate 1.0 ms low freq clock
W
WUAHTH
WUCTH
WUCAL
WULIN
WUPTB3
WUPTB2
WUPTB1
WUPTB0
0
0
0
0
0
0
0
0
0
WULTC
PRDF
APRESC[12:8]
APRESC[7:0]
Notes
91. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
92. Register Offset with the “lo” address value not shown have to be accessed in 16-Bit mode. 8-Bit access will not function.
4.3.7.3
Register descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.3.7.3.1
PCR control register (PCR_CTL)
Table 72. PCR control register (PCR_CTL)
Offset
,
0x00
(93) (94)
Access: User read/write
15
14
13
12
11
10
9
8
R
0
0
0
0
0
0
0
0
W
HTIEM
UVIEM
HWRM
0
Reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
HTIE
UVIE
0
0
HWR
0
0
0
0
0
R
W
Reset
PFM[1:0]
OPMM[1:0]
PF[1:0]
0
OPM[1:0]
0
0
0
Notes
93. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
94. Register Offset with the “lo” address value not shown have to be accessed in 16-Bit mode. 8-Bit access will not function.
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Table 73. PCR control register (PCR_CTL) - register field descriptions
Field
Description
15
HTIEM
High temperature interrupt enable mask
0 - writing the HTIE bit will have no effect
1 - writing the HTIE bit will be effective
14
UVIEM
Supply undervoltage interrupt enable mask
0 - writing the UVIE bit will have no effect
1 - writing the UVIE bit will be effective
13
HWRM
Hardware reset mask
0 - writing the HWR bit will have no effect
1 - writing the HWR bit will be effective
12
Reserved
Reserved. Must remain “0”
11-10
PFM[1:0]
Prescaler factor mask
00,01,10 - writing the PF bits will have no effect
1 - writing the PF bits will be effective
9-8
OPMM[1:0]
Operation mode mask
00,01,10 - writing the OPM bits will have no effect
11 - writing the OPM bits will be effective
7
HTIE
High Temperature Interrupt enable. Writing only effective with corresponding mask bit HTIEM set.
0 - High temperature interrupt (HTI) enabled
1 - High temperature interrupt (HTI) disabled
6
UVIE
Low supply voltage interrupt enable. Writing only effective with corresponding mask bit UVIEM set.
0 - Low supply voltage interrupt (UVI) enabled
1 - Low supply voltage interrupt (UVI) disabled
5
HWR
Hardware Reset. Writing only effective with corresponding mask bit HWRM set. Write only.
0 - No effect
1 - All analog die digital logic is reset and external reset (RESET_A) is set to reset the MCU.
4
Reserved
3-2
PF[1:0]
1-0
OPM[1:0]
Reserved. Must remain “0”
1.0 ms Prescaler. Writing only effective with corresponding mask bits PFM set to 11.
00 - 1
01 - 2
10 - 4
11 - 8
Operation mode select. Writing only effective with “11” mask bits OPMM set to 11.
00 - Normal mode
01 - Stop mode
10 - Sleep mode
11 with Cranking feature disabled - same effect as 01 (STOP mode)
11 with Cranking feature enabled - Cranking mode
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4.3.7.3.2
PCR status register (PCR_SR (hi))
Table 74. PCR status register (PCR_SR (hi))
Offset(95) 0x02
R
Access: User read/write
7
6
5
4
3
2
1
0
HTF
UVF
HWRF
WDRF
HVRF
LVRF
WULTCF
WLPMF
0/1
0
0
W
Reset
Write 1 will clear the
0
0
0/1
flags(96)
0/1
0/1
Notes
95. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
96. HTF and UVF represent the current status and cannot be cleared. Writing 1 to HTF / UVF will clear the Interrupt flag in the Interrupt Source Register
and Interrupt Vector Register instead.
Table 75. PCR status register (PCR_SR (hi)) - register field descriptions
Field
Description
7
HTF
High Temperature Condition Flag. This bit is set once a temperature warning is detected, or the last reset being caused by a temperature
shutdown event (TSDR). Writing HTF=1 will clear the flag and the interrupt flag in the Interrupt Source Register and Interrupt Vector
Register, if the condition is gone.
0 - No High Temperature condition detected.
1 - High Temperature condition detected or last reset = TSDR.
6
UVF
Supply Undervoltage Condition Flag. This bit is set once a undervoltage warning is detected. Writing UVF=1 will clear the flag and the
Interrupt flag in the Interrupt Source Register and Interrupt Vector Register, if the condition is gone (UVF=0).
0 - No undervoltage condition detected.
1 - Undervoltage condition detected.
5
HWRF
Hardware Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last reset was caused by a HWR command.
4
WDRF
Watchdog Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last reset was caused by the analog die window watchdog.
3
HVRF
VDDH Low Voltage Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last reset was caused by a low voltage condition at the VDDH regulator. (LVRF = 0)
1 - Last reset was caused by a low voltage condition at the VDDL regulator. (LVRF = 1)
2
LVRF
VDDL Low Voltage (POR) Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last reset was caused by a low voltage condition at the VDDL regulator. (Power on Reset - POR)
1
WULTCF
Life Time Counter Wake-up Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last Wake-up was caused by a life time counter overflow
0
WLPMF
Wake-up after Low Power Mode Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after Low Power mode.
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4.3.7.3.3
PCR status register (PCR_SR (lo))
Table 76. PCR status register (PCR_SR (lo))
Offset(97) 0x03
R
Access: User read/write
7
6
5
4
3
2
1
0
WUAHTHF
WUCTHF
WUCALF
WULINF
WUPTB3F
WUPTB2F
WUPTB1F
WUPTB0F
0
0
0
W
Reset
Write 1 will clear the flags
0
0
0
0
0
Notes
97. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 77. PCR status register (PCR_SR (lo)) - register field descriptions
Field
7
WUAHTHF
Description
Wake-up on Ah counter threshold Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after Ah counter threshold reached.
6
WUCTHF
Wake-up on current threshold Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after current threshold reached.
5
WUCALF
Wake-up on calibration request flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after calibration request.
4
WULINF
Wake-up on LIN flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after LIN wake-up detected
3
WUPTB3F
Wake-up on GPIO 3 event (L0 external wake-up) flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after GPIO 3 event
2
WUPTB2F
Wake-up on GPIO 2 event (TIMER output compare) flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after GPIO 2 event
1
WUPTB1F
Wake-up on GPIO 1 event (TIMER output compare) flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after GPIO 1 event
0
WUPTB0F
Wake-up on GPIO 0 event (TIMER output compare) flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after GPIO 0 event
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4.3.7.3.4
PCR 1.0 ms prescaler (PCR_PRESC)
Table 78. PCR 1.0 ms Prescaler (PCR_PRESC)
Offset (98),(99)
Access: User read/write
0x04
15
14
13
12
R
11
10
9
8
PRESC[15:8]
W
Reset
0
1
1
1
1
1
0
1
7
6
5
4
3
2
1
0
0
0
0
0
R
PRESC[7:0]
W
Reset
0
0
0
0
Notes
98. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
99. This Register is 16 Bit access only.
Table 79. PCR 1.0 ms prescaler (PCR_PRESC) - register field descriptions
Field
15-0
PRESC[15:0]
Description
1.0 ms Prescaler, used to derive D2DSCLK and D2DFCLK from the D2DCLK signal. See 4.3.5, “Device clock tree" for details.
4.3.7.3.5
Wake-up enable register (PCR_WUE (hi))
Table 80. Wake-up enable register (PCR_WUE (hi))
Offset(100) 0x06
R
W
Reset
Access: User read/write
7
6
5
4
3
2
1
0
WUAHTH
WUCTH
WUCAL
WULIN
WUPTB3
WUPTB2
WUPTB1
WUPTB0
0
0
0
0
0
0
0
0
Notes
100. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 81. Wake-up enable register (PCR_WUE (hi)) - register field descriptions
Field
7
WUAHTH
Description
0 - Wake-up on Ah counter disabled
1 - Wake-up on Ah counter enabled
6
WUCTH
0 - Wake-up on current threshold disabled
1 - Wake-up on current threshold enabled
5
WUCAL
0 - Wake-up on calibration request disabled
1 - Wake-up on calibration request enabled
4
WULIN
0 - Wake-up on LIN disabled
1 - Wake-up on LIN enabled
3
WUPTB3
0 - Wake-up on GPIO 3 event disabled
1 - Wake-up on GPIO 3 event enabled
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Table 81. Wake-up enable register (PCR_WUE (hi)) - register field descriptions (continued)
Field
Description
2
WUPTB2
0 - Wake-up on GPIO 2 event disabled
1 - Wake-up on GPIO 2 event enabled
1
WUPTB1
0 - Wake-up on GPIO 1 event disabled
1 - Wake-up on GPIO 1 event enabled
0
WUPTB0
0 - Wake-up on GPIO 0 event disabled
1 - Wake-up on GPIO 0 event enabled
4.3.7.3.6
Wake-up enable register (PCR_WUE (lo))
Table 82. Wake-up enable register (PCR_WUE (lo))
Offset(101) 0x07
Access: User read/write
7
R
W
WULTC
Reset
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Notes
101. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 83. Wake-up enable register (PCR_WUE (lo)) - register field descriptions
Field
7
WULTC
Description
0 - Wake-up on Life Timer Counter Overflow disabled
1 - Wake-up on Life Timer Counter Overflow enabled
4.3.7.3.7
Trim for accurate 1.0 ms low freq clock (TRIM_ALF (hi))
Table 84. Trim for accurate 1.0 ms low freq clock (TRIM_ALF (hi))
Offset(102) 0x0E
R
Access: User read
15
14
13
PRDF
0
0
12
11
10
9
8
APRESC[12:8]
W
Notes
102. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4.3.7.3.8
Trim for accurate 1.0 ms low freq clock (TRIM_ALF (lo))
Table 85. Trim for accurate 1.0 ms low freq clock (TRIM_ALF (lo))
Offset(103) 0x0F
Access: User read
7
R
6
5
4
3
2
1
0
APRESC[7:0]
W
Notes
103. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 86. Trim for accurate 1.0 ms low freq clock (TRIM_ALF (lo)) - register field descriptions
Field
Description
ALFCLK Prescaler ready Flag
0 - The ALFCLK synchronization after power up or PRESC[15:0] / PF[1:0] change is not completed.
1 - The ALFCLK synchronization is complete. The ALFCLK signal is synchronized to the D2DCLK.
15
PRDF
12-0
APRESC[12:0]
4.4
ALFCLK Prescaler
This read only value represents the current ALFCLK prescaler value. With the synchronization complete (PRDF=1), the prescaler is
used to create the calibrated clock for the Life Time Counter (Normal mode and Low Power mode), and Timer and Current trigger (Low
Power Mode only), based on the low power oscillator.
After Power Up, the APRESC register is reset to 0x0200 (512dec) until the first synchronization is complete. This will initialize the
ALFCLK to 1.0 kHz.
Interrupt module - IRQ
4.4.1
Introduction
Several interrupt sources are implemented on the analog die to indicate important system conditions. Those Interrupt events are
signalized via the D2DINT signal to the microcontroller. See Section 4.18, “MCU - interrupt module (S12S9S12I128PIMV1V1)".
4.4.2
Interrupt source identification
Once an Interrupt is signalized, there are two options to identify the corresponding source(s).
NOTE
The following Interrupt source registers (Interrupt Source Mirror and Interrupt Vector Emulation by
Priority) are indicators only. After identifying the interrupt source, the acknowledgement of the
interrupt has to be performed in the corresponding block.
4.4.2.1
Interrupt source mirror
All Interrupt sources in the MM912_637 analog die are mirrored to a special Interrupt Source Register (INT_SRC). This register is read
only and will indicate all currently pending Interrupts. Reading this register will not acknowledge any interrupt. An additional D2D access
is necessary to serve the specific module.
4.4.2.2
Interrupt vector emulation by priority
To allow a vector based interrupt handling by the MCU, the number of the highest prioritized interrupt pending is returned in the Interrupt
Vector Register (INT_VECT). Reading this register will not acknowledge an interrupt. An additional D2D access is necessary to serve the
specific module.
4.4.3
Interrupt global mask
The Global Interrupt mask registers INT_MSK (hi) and INT_MSK (lo) are implemented to allow a global enable / disable of all analog die
Interrupt sources. The individual blocks mask registers should be used to control the individual sources.
4.4.4
Interrupt sources
The following Interrupt sources are implemented on the analog die.
Table 87. Interrupt sources
IRQ
Description
UVI
Undervoltage Interrupt (or wake-up from Cranking mode)
HTI
High Temperature Interrupt
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Table 87. Interrupt sources
IRQ
LTI
Description
LIN Driver Overtemperature Interrupt
CH0
TIM Channel 0 Interrupt
CH1
TIM Channel 1 Interrupt
CH2
TIM Channel 2 Interrupt
CH3
TIM Channel 3 Interrupt
TOV
TIM Timer Overflow Interrupt
ERR
SCI Error Interrupt
TX
SCI Transmit Interrupt
RX
SCI Receive Interrupt
CVMI
Current / Voltage Measurement Interrupt
LTC
Lifetime Counter Interrupt
CAL
Calibration Request Interrupt
4.4.4.1
Undervoltage interrupt (UVI)
This maskable interrupt signalizes a undervoltage condition on the VSUP supply input. Acknowledge the interrupt by writing a 1 into the
UVF Bit in the PCR Status Register (PCR_SR (hi)). The flag cannot be cleared as long as the condition is present. To issue a new interrupt,
the condition has to vanish and occur again. The UVF Bit represents the current condition, and might not be set after an interrupt was
signalized by the interrupt source registers. See Section 4.3, “Analog die - power, clock and resets - PCR" for details on the PCR Status
Register (PCR_SR (hi)), including masking information.
NOTE
The undervoltage interrupt is not active in devices with the Cranking mode enabled. For those
devices, the undervoltage threshold is used to enable the high precision low voltage threshold during
Stop/Sleep mode. Once the device wakes up from cranking mode, the UVI flag is indicating the
wake-up source.
4.4.4.2
High temperature interrupt (HTI)
This maskable interrupt signalizes a high temperature condition on the analog die. The sensing element is located close to the major
thermal contributors, the system voltage regulators.
Acknowledge the interrupt by writing a 1 into the HTF Bit in the PCR Status Register (PCR_SR (hi)). The flag cannot be cleared as long
as the condition is present. To issue a new interrupt, the condition has to vanish and occur again. The HTF Bit represents the current
condition and might not be set after an interrupt was signalized by the interrupt source registers. See Section 4.3, “Analog die - power,
clock and resets - PCR" for details on the PCR Status Register (PCR_SR (hi)), including masking information.
4.4.4.3
LIN driver overtemperature interrupt (LTI)
Acknowledge the interrupt by reading the LIN Register - LINR. The flag cannot be cleared as long as the condition is present. To issue a
new interrupt, the condition has to vanish and occur again. See Section 4.12, “LIN" for details on the LIN Register, including masking
information.
4.4.4.4
TIM channel 0 interrupt (CH0)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
4.4.4.5
TIM channel 1 interrupt (CH1)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
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4.4.4.6
TIM channel 2 interrupt (CH2)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
4.4.4.7
TIM channel 3 interrupt (CH3)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
4.4.4.8
TIM timer overflow interrupt (TOV)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
4.4.4.9
SCI error interrupt (ERR)
See Section 4.13, “Serial communication interface (S08SCIV4)".
4.4.4.10
SCI transmit interrupt (TX)
See Section 4.13, “Serial communication interface (S08SCIV4)".
4.4.4.11
SCI receive interrupt (RX)
See Section 4.13, “Serial communication interface (S08SCIV4)".
4.4.4.12
Current/voltage measurement interrupt (CVMI)
Indicates the current or voltage measurement finished (VM or CM bit set). See Section 4.8, “Channel acquisition".
4.4.4.13
Life time counter interrupt (LTC)
In case a Life Time Counter overflow occurs with the corresponding interrupt enabled, the LTC interrupt is issued. See Section 4.14, “Life
time counter (LTC)".
4.4.4.14
Calibration request interrupt (CAL)
Once a request for re-calibration is present (Temperature out of pre-set range), the Calibration Interrupt is issued. After a calibration
wake-up, the reading of ACQ_ITEMP must be done after waiting for the latency of the temperature acquisition chain. Then ACQ_ITEMP
is valid to adjust the compensation over temperature. See full documentation on the interrupt source inSection 4.8, “Channel acquisition".
4.4.5
4.4.5.1
IRQ - memory map and registers
Overview
This section provides a detailed description of the memory map and registers.
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4.4.5.2
Module memory map
The memory map for the IRQ module is given in Table 63
Table 88. Module memory map
Offset(104)
Name
0x08
0x09
0x0A
INT_SRC (hi)
R
Interrupt source register
W
INT_SRC (lo)
R
Interrupt source register
W
INT_VECT
R
Interrupt vector register
W
0x0B
0x0C
0x0D
7
6
4
3
2
1
0
TOV
CH3
CH2
CH1
CH0
LTI
HTI
UVI
0
0
CAL
LTC
CVMI
RX
TX
ERR
0
0
0
0
0
0
0
0
0
0
0
0
TOVM
CH3M
CH2M
CH1M
CH0M
LTIM
HTIM
UVIM
0
0
CALM
LTCM
CVMM
RXM
TXM
ERRM
R
Reserved
5
IRQ[3:0]
W
INT_MSK (hi)
R
Interrupt mask register
W
INT_MSK (lo)
R
Interrupt mask register
W
Notes
104. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4.4.5.3
Register descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.4.5.3.1
Interrupt source register (INT_SRC (hi))
Table 89. Interrupt source register (INT_SRC (hi))
Offset(105) 0x08
R
Access: User read
7
6
5
4
3
2
1
0
TOV
CH3
CH2
CH1
CH0
LTI
HTI
UVI
W
Notes
105. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 90. Interrupt Source Register (INT_SRC (hi)) - register field descriptions
Field
Description
7
TOV
TIM16B4C - Timer overflow interrupt status
0 - No timer overflow interrupt pending
1 - Timer overflow interrupt pending
6
CH3
TIM16B4C - TIM channel 3 interrupt status
0 - No channel 3 interrupt pending
1 - Channel 3 interrupt pending
5
CH2
TIM16B4C - TIM channel 2 interrupt status
0 - No channel 2 interrupt pending
1 - Channel 2 interrupt pending
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Table 90. Interrupt Source Register (INT_SRC (hi)) - register field descriptions (continued)
Field
Description
4
CH1
TIM16B4C - TIM channel 1 interrupt status
0 - No channel 1 interrupt pending
1 - Channel 1 interrupt pending
3
CH0
TIM16B4C - TIM channel 0 interrupt status
0 - No channel 0 interrupt pending
1 - Channel 0 interrupt pending
2
LTI
LIN Driver overtemperature interrupt status
0 - No LIN driver overtemperature interrupt
1 - LIN driver overtemperature interrupt
1
HTI
High temperature interrupt status
0 - No high temperature interrupt pending
1 - High temperature interrupt pending
0
UVI
Undervoltage interrupt pending or wake-up from Cranking mode status
0 - No undervoltage Interrupt pending or wake-up from Cranking mode
1 - Undervoltage interrupt pending or wake-up from Cranking mode
4.4.5.3.2
Interrupt source register (INT_SRC (lo))
Table 91. Interrupt source register (INT_SRC (lo))
Offset(106) 0x09
R
Access: User read
7
6
5
4
3
2
1
0
0
0
CAL
LTC
CVMI
RX
TX
ERR
W
Notes
106. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 92. Interrupt source register (INT_SRC (lo)) - register field descriptions
Field
Description
5
CAL
Calibration request interrupt status
0 - No calibration request interrupt pending
1 - Calibration request interrupt pending
4
LTC
Life time counter interrupt status
0 - No life time counter interrupt pending
1 - Life time counter interrupt pending
3
CVMI
Current / Voltage measurement interrupt status
0 - No Current / Voltage measurement interrupt pending
1 - Current / Voltage measurement interrupt pending
2
RX
SCI receive interrupt status
0 - No SCI receive interrupt pending
1 - SCI receive interrupt pending
1
TX
SCI transmit interrupt status
0 - No SCI transmit interrupt pending
1 - SCI transmit interrupt pending
0
ERR
SCI error interrupt status
0 - No SCI transmit interrupt pending
1 - SCI transmit interrupt pending
4.4.5.3.3
Interrupt vector register (INT_VECT)
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Table 93. Interrupt vector register (INT_VECT)
Offset(107) 0x0A
R
Access: User read
7
6
5
4
0
0
0
0
3
2
1
0
IRQ
W
Notes
107. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 94. Interrupt vector register (INT_VECT) - register field descriptions
Field
4-0
IRQ
Description
Represents the highest prioritized interrupt pending. See Table 95. If no interrupt is pending, the result will be 0.
Table 95. Interrupt vector/priority
IRQ
IRQ
Priority
No interrupt pending or wake-up from Stop mode
0x00
-
UVI
Undervoltage interrupt or wake-up from Cranking mode
0x01
1 (highest)
HTI
High temperature interrupt
0x02
2
LTI
LIN driver overtemperature interrupt
0x03
3
CH0
TIM channel 0 interrupt
0x04
4
CH1
TIM channel 1 interrupt
0x05
5
CH2
TIM channel 2 interrupt
0x06
6
CH3
TIM channel 3 interrupt
0x07
7
TOV
TIM timer overflow interrupt
0x08
8
ERR
SCI error interrupt
0x09
9
TX
SCI transmit interrupt
0x0A
10
RX
SCI receive interrupt
0x0B
11
CVMI
Acquisition interrupt
0x0C
12
LTC
Life time counter interrupt
0x0D
13
CAL
Calibration request interrupt
0x0E
14 (lowest)
-
Description
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4.4.5.3.4
Interrupt mask register (INT_MSK (hi))
Table 96. Interrupt mask register (INT_MSK (hi))
Offset(108) 0x0C
R
W
Access: User read/write
7
6
5
4
3
2
1
0
TOVM
CH3M
CH2M
CH1M
CH0M
LTIM
HTIM
UVIM
0
0
0
0
0
0
0
0
Reset
Notes
108. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 97. Interrupt mask register (INT_MSK (hi)) - register field descriptions
Field
Description
7
TOVM
Timer overflow interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
6
CH3M
Timer channel 3 interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
5
CH2M
Timer channel 2 interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
4
CH1M
Timer channel 1 interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
3
CH0M
Timer channel 1 interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
2
LTIM
LIN driver overtemperature interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
1
HTIM
High temperature interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
0
UVIM
Undervoltage interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
4.4.5.3.5
Interrupt mask register (INT_MSK (lo))
Table 98. Interrupt mask register (INT_MSK (lo))
Offset(109) 0x0D
R
Access: User read/write
7
6
0
0
0
0
W
Reset
5
4
3
2
1
0
CALM
LTCM
CVMM
RXM
TXM
ERRM
0
0
0
0
0
0
Notes
109. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 99. Interrupt mask register (INT_MSK (lo)) - register field descriptions
Field
Description
5
CALM
Calibration request interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
4
LTCM
Life time counter interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
3
CVMM
Current / Voltage measurement interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
2
RXM
SCI receive interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
1
TXM
SCI transmit interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
0
ERRM
4.5
SCI error interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
Current measurement - ISENSE
4.5.1
Introduction
This chapter only gives a summary of the current sense module. Refer to Section 4.8, “Channel acquisition" for the complete description
of all acquisition channels, including the current measurement channel.
4.5.1.1
•
•
•
•
•
•
•
•
•
•
•
Features
Dedicated 16 Bit Sigma Delta () ADC
Programmable Gain Amplifier (PGA) with 8 programmable gain factors
Gain Control Block (GCB) for automatic gain adjustment
Simultaneous Sampling with Voltage Channel
Programmable Gain and Offset Compensation
Optional Chopper Mode with moving average
SINC3 + IIR Stage
Calibration mode to compute compensation buffers
Programmable Low Pass Filter (LPF), configuration shared with the Voltage Measurement Channel
Optional Shunt resistor sensing feature
Triggered Sampling during Low Power Mode with programmable wake-up conditions
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4.5.1.2
Block diagram
PGA
Auto
Zero
Battery
Minus
Pole
ESD
Input
Swap
ISENSEL
RSHUNT
PGA
Compensation
Decimation
with IIR
LPF
24Bit
ESD
ISENSEH
GCB
Chassis
Ground
Vref
Digital Chopper
Figure 29. Current measurement channel
The battery current is measured by measuring the voltage drop VDROP over an external shunt resistor, connected to ISENSEH and
ISENSEL. VDROP, and is defined as the differential voltage between the ISENSEL and ISENSEH inputs (VDROP=ISENSEL-ISENSEH). A
positive voltage drop means a positive current is flowing, and vice versa.
If the GND pin of the module is connected to ISENSEH, the measured current includes the supply current of the MM912_637 (current
flows back to negative battery pole). If the GND pin is connected to the ISENSEL input, the supply current of the MM912_637 is not
measured. However, the voltage at the ISENSEH input could go below GND (see max ratings). In this case, the current measurement still
functions as specified.
4.6
Voltage measurement - VSENSE
4.6.1
Introduction
This chapter only gives a summary of the voltage sense module. Refer to Section 4.8, “Channel acquisition" for the complete description
of all acquisition channels, including the voltage measurement channel.
4.6.1.1
•
•
•
•
•
•
•
•
•
Features
Dedicated 16 Bit Sigma Delta () ADC
Fixed High Precision Divider
Optional External Voltage Input “VOPT”
Simultaneous Sampling with Current Channel
Programmable Gain and Offset Compensation
Calibration mode to compute compensation buffers
Optional Chopper mode with moving average
SINC3 + IIR Stage
Programmable Low Pass Filter (LPF), Configuration shared with Current Measurement Channel
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4.6.1.2
Block diagram
VOPT
Input
Swap
ESD
DIV28
MUX
Compensation
DIV28
VSENSE
Decimator
with IIR
LPF
16Bit
ESD
Vref
Digital Chopper
Figure 30. Voltage Measurement Channel
The battery voltage is measured by default, via the VSENSE input. A high precision divider stage scales down the battery voltage by a
fixed factor K =1/28, to a voltage below the internal reference voltage of the Sigma Delta ADC (VSENSE*K < VREF). If an optional external
voltage is measured, the multiplexer (MUX) is selected to feed the VOPT input to the buffer.
4.7
Temperature measurement - TSENSE
4.7.1
Introduction
This chapter only gives a summary of the temperature sense module. Refer to Section 4.8, “Channel acquisition" for the complete
description of all acquisition channels, including the temperature measurement channel.
4.7.1.1
•
•
•
•
•
•
Features
Internal on chip Temperature Sensor
Optional External Temperature Sensor Input (VTEMP)
Dedicated 16-Bit Sigma Delta ADC
Programmable Gain and Offset Compensation
Optional External Sensor Supply (TSUP) with selectable capacitor
Optional Measurement during Low Power mode to trigger recalibration
4.7.1.2
Block diagram
TSUP
internal
TempSense
R1
Input
Swap
TSUP
MUX
Compensation
Decimation
16Bit
VTEMP
ESD
CTSUP
RVTEMP
Vref
R2
Digital Chopper
AGND
Figure 31. Temperature measurement channel
NOTE
To minimize ground shift effects while using the external sensor option, R2 must be placed as close
to the AGND pin as possible. CTSUP is optional. The supply output must be configured to operate with
the capacitor.
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4.8
Channel acquisition
4.8.1
Introduction
This chapter documents the current, voltage, and temperature acquisition flow. The chapter is structured in the following sections.
•
Section 4.8.2, “Channel structure overview"
•
Section 4.8.3, “Current and voltage measurement"
— Section 4.8.3.1, “Shunt sense, PGA, and GCB (current channel only)"
— Section 4.8.3.2, “Voltage sense multiplexer (voltage channel only)"
— Section 4.8.3.3, “Sigma delta converter"
— Section 4.8.3.4, “Compensation"
— Section 4.8.3.5, “IIR/decimation/chopping stage"
— Section 4.8.3.6, “Low pass filter"
— Section 4.8.3.7, “Format and clamping"
•
Section 4.8.4, “Temperature measurement channel"
— Section 4.8.4.1, “Compensation"
•
Section 4.8.5, “Calibration"
•
Section 4.8.6, “Memory map and registers"
4.8.2
Channel structure overview
The MM912_637 offers three parallel measurement channels. Current, Voltage, and Temperature. The Voltage Channel is shared
between the VSENSE and VOPT voltage source, the Temperature channel between ETEMP and ITEMP.
I
PGA
V
T
SD
SD
SD
1
10
8
Gain
(IGCx)
Offset
(COC)
1
10
8
Gain
(VSGC)
Offset
(VOC)
SINC3
+IIR
SINC1
LPF
Format &
Clamp
SINC3
+IIR
SINC1
LPF
Format &
Clamp
SINC1
Format &
Clamp
SINC3
1
8
Gain
(ITGC/
ETGC)
24
16
16
8
Offset
(ITOC/
ETOC)
Figure 32. Simplified measurement channel
Figure 33 shows an overview of the detailed dependencies between the control and status registers and the channels. Refer to the
following sections of this chapter for details.
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ESD
ESD
ESD
ESD
VSENSE
VTEMP
TSUP
ESD
SENSEH
VOPT
ESD
SENSEL
ECAP(M)
Internal
TEMP
Sensor
DIAGI(M)
D
VMEN(M)
TSUP
ETEMP
ITEMP
OPTE(M)
DIV28
DIV28
PGAO(M)
PGAZ(M)
OPEN
OPENE(M)
Open
Test
PGAF(M)
R/W
R
R/W
R/W
R/W R/W R/W
R/W
ITMEN(M)
ETMEN(M)
PGA
Offset
Cal.
Cal Ref
Diag
AGEN(M)
G
C
B
CDEN(M)
CADCG(M)
PGAG
MUX
MUX
VADCG(M)
DIAGV(M)
Cal
Ref
ITCHOP(M)
ETCHOP(M)
TDEN(M)
TADCG(M)
VDEN(M)
ZERO(M)
PGAOF
PGAOC4..512[10:0]
PGA
000
R
R/W
R/W
R/W
R/W
Short
R/W
R/W
R/W R/W
Chopper Control
ADC
Ref
Chopper Control
ADC Ref
1 Bit
1 Bit
R/W
R/W
200
ITCHOP
80
80
R/W
IIRC(M)[2:0]
DBT(M)[1:0]
00
R/W
R/W
Voltage Measurement Control
Temperature Measurement Control
00
00
R/W
R/W R/W
ETCHOP
00
Gain and Offset Compensation and Sinc 3 Filter
200
R/W
SINC1
L=2
16 Bit
DEC[2:0]
SINC1
L=4
ITM
Calibration
Request
ITEMP[15:0]
SINC1
L=4
ETEMP[15:0]
R/W
ETM
TMF[2:0]
TCMIN[15:0]
TCMAX[15:0]
Format &
Clamp
Gain and Offset Compensation, Sinc 3 Filter, and IIR Filter Block
R/W R/W
VCHOP
CVCHOP(M)
R
1 Bit
Gain and Offset Compensation, Sinc 3 Filter, and IIR Filter Block
R/W R/W
R
R/W
R/W R/W
Diag
IGAIN[2:0]
R/W R/W
R/W
R/W R/W
Short
Short
R/W R/W
R/W
R
CCHOP
ITGC[7:0]
R
ETGC[7:0]
R
COC4..512[7:0]
VOC[7:0]
IGC4..512[9:0]
ETOC[7:0]
ITOC[7:0]
CCOMP(M)
VCOMP(M)
0A4
041
00B
0812
0212
4
B
5
10E
0E3
1021
4
5
Chopper Control
0000 0000
VSGC[9:0]
TCOMP(M)
A7[15:0]
A6[15:0]
A5[15:0]
A4[15:0]
A3[15:0]
A2[15:0]
A1[15:0]
A0[15:0]
LPFEN(M)
0
1
R/W
CALIE(M)
LPF
R/W
24 Bit
16 Bit
PRESC[15:0]
PF[1:0]
Clock Control
BGCAL(M)[1:0]
BGLDO
BGADC[1:0]
VM
VMOW
AHTH[30:0]
TCMP[15:0]
Low Power Current
measurement result
AHCR(M)
VTH
VOLT[15:0]
=?
CMOW
CM
CURR[23:0]
BG Control
Format &
Clamp
0xDAC0
Format &
Clamp
R
THF[7:0]
CTH[7:0]
AHC[31:0]
Current
Threshold
Wake Up
AH Threshold
Wake Up
Calibration
Wake Up
PRDF
APRESC[12:0]
AVRF
BGRF
BG2EN
BG3EN
=1
BG1EN
Wake Up Control (low power mode only)
Cal
Ref
ADC
Ref
A15[15:0]
A14[15:0]
A13[15:0]
A12[15:0]
A11[15:0]
A10[15:0]
A9[15:0]
A8[15:0]
LPFC[3:0]
Calibration
Interrupt
CALF
LPF
R/W R/W R/W R/W R/W R/W R/W R/W
00B
041
0A4 0E3
0212
0812
1021
5
B
4
5
Current Measurement Control
R
R
0000
W
R/W
R
R
R/W R/W R/W
R
R
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R/W
R
R
R
R
R
R/W
R
R
R/W
R
R
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R/W R/W
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R/W R/W
CMEN(M)
0
1
CVMIE(M)
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Figure 33. Channel complete overview
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4.8.3
Current and voltage measurement
To guarantee synchronous voltage and current acquisition, both channels are implemented equal in terms of digital signal conditioning
and timing. The analog signal conditioning, before the Sigma Delta Converter, is different to match the different sources.
4.8.3.1
Shunt sense, PGA, and GCB (current channel only)
Current Channel specific analog signal conditioning.
4.8.3.1.1
Shunt sense
An optional current sense feature is implemented to sense the presence of the current shunt resistor. Setting the OPEN bit (ACQ_CTL
register), will activate the feature. The OPEN bit (ACQ_SR register) will indicate the shunt resistor open. The sense feature will detect an
open condition for a shunt resistance RSHUNT > ROPEN.
4.8.3.1.2
Programmable gain amplifier (PGA)
To allow a wide range of current levels to be measured, a programmable gain amplifier is implemented. Following the input chopper (see
Section 4.8.3.5, “IIR/decimation/chopping stage"), the differential voltage is amplified by one of the 8 gains controlled by the Gain Control
Block. The PGA has an internal offset compensation feature - see Section 4.8.4.1, “Compensation" and Section 4.8.5, “Calibration" for
details.
4.8.3.1.3
Gain control block (GCB)
To allow a transparent Gain adjustment with minimum MCU load, an automatic gain control has been implemented. The absolute output
of the PGA is constantly compared with a programmable up and down threshold (ACQ_GCB register). The threshold is a D/A output
according Table 100.
Table 100. Gain control block - register
ACQ_GCB D[7:0]
GCB high (up) threshold
ACQ_GCB D[7:0]
GCB low (down) threshold
0000xxxx
1/16 VREF
xxxx0000
0
0001xxxx
2/16 VREF
xxxx0001
1/16 VREF
0010xxxx
3/16 VREF
xxxx0010
2/16 VREF
0011xxxx
4/16 VREF
xxxx0011
3/16 VREF
0100xxxx
5/16 VREF
xxxx0100
4/16 VREF
0101xxxx
6/16 VREF
xxxx0101
5/16 VREF
0110xxxx
7/16 VREF
xxxx0110
6/16 VREF
0111xxxx
8/16 VREF
xxxx0111
7/16 VREF
1000xxxx
9/16 VREF
xxxx1000
8/16 VREF
1001xxxx
10/16 VREF
xxxx1001
9/16 VREF
1010xxxx
11/16 VREF
xxxx1010
10/16 VREF
1011xxxx
12/16 VREF
xxxx1011
11/16 VREF
1100xxxx
13/16 VREF
xxxx1100
12/16 VREF
1101xxxx
14/16 VREF
xxxx1101
13/16 VREF
1110xxxx
15/16 VREF
xxxx1110
14/16 VREF
1111xxxx
16/16 VREF
xxxx1111
15/16 VREF
Once the programmed threshold is reached, the gain is adjusted to the next level. The currently active gain setting can be read in the
IGAIN[2:0] register. Once the gain has been adjusted by the GCB, the PGAG bit will be set.
The automatic Gain Control can be disabled by clearing the AGEN bit. In this case, writing the IGAIN[2:0] register will allow manual gain
control.
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NOTE
The IGAIN[2:0] register content does determine the offset compensation register access, as there are
8 individual offset register buffers implemented, accessed through the same COC[7:0] register.
4.8.3.2
Voltage sense multiplexer (voltage channel only)
A multiplexer has been implemented to select between the VSENSE or VOPT voltage input. The OPTE bit controls the multiplexer. Both
input signals are divided by a fixed DIV28 divider.
NOTE
There is no further state machine separation of the two voltage channels. The software has to assure
all compensation registers are configured properly after changing the multiplexer. Both voltage
source conversion results will be stored in the same result register.
The divided and multiplexed voltages will be routed through the optional chopper (see Section 4.8.3.5, “IIR/decimation/chopping stage")
before entering the Sigma Delta converter stage.
4.8.3.3
Sigma delta converter
4.8.3.3.1
Overview
A high resolution ADC is needed for current and battery voltage measurements of the MM912_637. A second order sigma delta modulator
based architecture is chosen.
4.8.3.4
Compensation
Following the optional chopper stage, the sigma delta bit stream is first gain and then offset compensated using the compensation
registers.
The compensation stages for both channels can be completely bypassed by clearing the CCOMP / VCOMP bits.
4.8.3.4.1
Gain compensation
Table 101 shows the gain compensation register for the current and voltage channel. At system startup, the factory trimmed values have
to be copied into the VSGC and IGCx registers (see Section 5.2, “IFR trimming content and location").
NOTE
There are 8 individual Gain compensation registers for the current measurement channels different
PGA gains with 8 individual gain trim values present in the IFR trimming flash.
Based on the voltage channel multiplexer configuration, a different trim gain compensation value has
to be used in the compensation register. The compensation register content has to be updated when
changing the multiplexer setting.
Table 101. Gain compensation - voltage and current channel
VSGC[9:0]
IGCx[9:0]
Voltage channel gain
Current channel gain
0x3FF
1.3174
1.7832
0x3FE
1.3169
1.7822
0x3FD
1.3164
1.7812
.
.
.
.
.
.
0x203
1.0694
1.2872
0x202
1.0689
1.2862
0x201
1.0684
1.2852
0x200 (default)
1.0679
1.2842
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Table 101. Gain compensation - voltage and current channel (continued)
VSGC[9:0]
IGCx[9:0]
Voltage channel gain
Current channel gain
0x1FF
1.0674
1.2832
0x1FE
1.0669
1.2822
0x1FD
1.0664
1.2812
.
.
.
.
.
.
0x002
0.8189
0.7862
0x001
0.8184
0.7852
0x000
0.8179
0.7842
4.8.3.4.2
Offset compensation
Table 102 shows the offset compensation register for the current and voltage channel. At system startup, the factory trimmed values have
to be copied into the VOC and COC registers (see Section 5.2, “IFR trimming content and location").
NOTE
Based on the voltage channel multiplexer and copper configuration, a different trim offset
compensation value has to be used in the compensation register. The compensation register content
has to be updated when changing the multiplexer setting.
While there is only one offset compensation register VOC[7:0] for the voltage channel, there are 8
individual offset compensation registers for the current channel. The access happens through the
COC[7:0] register mapped, based on the IGAIN[2:0] register content.
Table 102. Offset compensation - voltage and current channel
VOC[7:0]
COC[7:0]
Voltage channel offset(110)
Current channel offset(110)
0x7F
+9.073
+15.092
0x7E
+9.002
+14.974
0x7D
+8.93
+14.855
.
.
.
.
.
.
0x03
0.214
+0.357
0x02
0.143
+0.238
0x01
0.071
+0.119
0x00 (default)
0
0
0xFF
-0.071
-0.119
0xFE
-0.143
-0.238
0xFD
-0.214
-0.357
.
.
.
.
.
.
0x82
-9.002
-14.974
0x81
-9.073
-15.092
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Table 102. Offset compensation - voltage and current channel (continued)
VOC[7:0]
COC[7:0]
Voltage channel offset(110)
Current channel offset(110)
0x80
-9.145
-15.211
Notes
110. SD input related (mV)
4.8.3.5
4.8.3.5.1
IIR/decimation/chopping stage
Functional description
The chopper frequency is set to one eighth of the decimator frequency (512 kHz typ). On each phase, four decimation cycles are
necessary to get a steady signal. The equation of the IIR is yn+1=.xn+(1-).yn.
The parameter can be configured by the IIRC[2:0] register. See Section 4.8.6.3.18, “I and V chopper control register (ACQ_CVCR (lo))".
The decimation process is then completed by a programmable (DEC[2:0]) sinc3 filter, which outputs a 0.5...8 kS/s signal. The modulated
noise is removed by an averaging filter (SINC1; L=4), which has an infinite rejection at the chopping frequency.
4.8.3.5.2
•
•
Latency and throughput
The throughput is 512 kHz/DF with DF configurable from 64 to 1024.
The latency is given by (4+3*IIR+3*Avger+N_LPF)*DF/512 kHz where:
— IIR=1 if IIR is enabled (0 otherwise),
— Avger=1 if the chopper mode is activated (0 otherwise),
— N_LPF is the LPF coefficient number.
4.8.3.6
Low pass filter
To achieve the required attenuation of the measured voltage and current signals in the frequency domain, a programmable low-pass filter
following the SINC3+IIR filter, is implemented for both channels with shared configuration registers to deliver the equivalent filtering.
The following filter characteristic is implemented:
•
FPASS = 100 Hz (Att100 Hz)
•
FSTOPP = 500 Hz (Att500 Hz)
The number of filter coefficients used can be programmed in the ACQ_LPFC[3:0] register. The filter can be bypassed completely clearing
the LPFEN bit.
The filter uses an algorithmic and logic unit (ALU) for calculating the filtered output data, depending on the incoming data stream at “DATA
IN” and the low-pass coefficients (A0...15) at the input “COEFF”, 16-bit width of each coefficient (See 4.8.6.3.22, “Low pass filter coefficient
Ax (LPF_Ax (hi))"). The filter structure calculates during one cycle (Tcyc=1/Fadc) the filtered data output.
Y(n)
+
+
+
a0
a1
a2
Z-1
Z-1
Z-1
Z-1
……
……
……
+
+
+
a13
a14
a15
Z-1
Z-1
Z-1
Z-1
Z-1
Z-1
X(n)
y(n) = a0.x(n)+a1.x(n-1)+a2.x(n-2)+a3.x(n-3)+a4.x(n-4)+a5.x(n-5)+a6.x(n-6)+a7.x(n-7)
+a8.x(n-8)+a9.x(n-9)+a10.x(n-10)+a11.x(n-11)+a12.x(n-12)+a13.x(n-13)+a14.x(n-14)+a15.x(n-15)
Figure 34. FIR structure
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Z-1 Unit delay is done at a programmable frequency, depending on the decimation factor programmed in the DEC[2:0] register. See
Table 120.
NOTE
There is no decimation from SINC3 to the LPF output, LPF uses same output rate than decimator.
It's therefore possible to select an output update rate independent of the filter characteristic and
bandwidth.
The coefficient vector consists of 16*16-bit elements and is free programmable, the maximum response time for 16 coefficients structure
is 16*1/output rate. The following filter function can be realized.
M
H LP ( z ) ai * z i
i 0
LP filter function
Eqn. 3
The coefficients aj are the elements of the coefficient vector and determine the filter function. M GO
18
none
Description
(Previous enable tagging and go to user program.) This command will be deprecated and
should not be used anymore. Opcode will be executed as a GO command.
Notes
265. If enabled, ACK will occur when data is ready for transmission for all BDM READ commands, and will occur after the write is complete for all BDM
WRITE commands.
266. When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space, the BDM resources are accessed, rather
than user code. Writing BDM firmware is not possible.
267. System stop disables the ACK function and ignored commands will have no ACK-pulse (e.g., CPU in stop or wait mode). The GO_UNTIL command
will not get an Acknowledge, if the CPU executes the wait or stop instruction before the “UNTIL” condition (BDM active again) is reached (see
Section 4.22.4.7, “Serial interface hardware handshake protocol" last note).
4.22.4.5
BDM command structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word, depending on
the command. All the read commands return 16 bits of data despite the byte or word implication in the command name.
8-bit reads return 16-bits of data, only one byte of which contains valid data. If reading an even
address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear
in the LSB.
16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware
command, the BDM ignores the least significant bit of the address and assumes an even address
from the remaining bits.
For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting
to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write
commands, the external host must wait 150 bus clock cycles after sending the data to be written, before attempting to send a new
command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay, in both
cases, includes the maximum 128 cycle delay that can be incurred, as the BDM waits for a free cycle before stealing a cycle.
The external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read
data for BDM firmware read commands. The 48 cycle wait allows enough time for the requested data to be made available in the BDM
shift register, ready to be shifted out.
The external host must wait 36 bus clock cycles after sending the data to be written, before attempting to send a new command for BDM
firmware write commands. This is to avoid disturbing the BDM shift register before the write has been completed.
The external host should wait for at least for 76 bus clock cycles, after a TRACE1 or GO command and before starting any new serial
command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code.
Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table.
NOTE
If the bus rate of the target processor is unknown or could be changing, it is recommended that the
ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK,
the delay times are automated.
Figure 82 represents the BDM command structure. The command blocks illustrate a series of eight bit times, starting with a falling edge.
The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 16 target
clock cycles.(268)
Notes
268. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 4.22.4.6, “BDM serial interface" and Section 4.22.3.2.1,
“BDM status register (BDMSTS)" for information on how serial clock rate is selected.
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8-Bits
AT ~16 TC/Bit
16-Bits
AT ~16 TC/Bit
Command
Address
Hardware
Read
150-BC
Delay
16 Bits
AT ~16 TC/Bit
Data
Next
Command
150-BC
Delay
Hardware
Write
Command
Address
Data
Next
Command
48-BC
DELAY
Firmware
Read
Command
Next
Command
Data
36-BC
DELAY
Firmware
Write
Command
Next
Command
Data
76-BC
Delay
GO,
TRACE
Command
Next
Command
BC = Bus Clock Cycles
TC = Target Clock Cycles
Figure 82. BDM command structure
4.22.4.6
BDM serial interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects
between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM.
The BDM serial interface is timed, based on the VCO clock (refer to the CPMU Block Guide for more details), which gets divided by 8.
This clock will be referred to as the target clock in the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start
of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred, most significant bit (MSB)
first, at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is
an external pull-up and drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long,
the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the
host for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 83, and that of target-to-host in Figure 84 and Figure 85. All four cases begin when the
host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can take the
target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time, while
the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization
between the host and target is established in this manner at the start of every bit time.
Figure 83 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is
asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes
this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch
detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
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BDM Clock
(Target MCU)
Host
Transmit 1
Host
Transmit 0
Perceived
Start of Bit Time
Target Senses Bit
Earliest
Start of
Next Bit
10 Cycles
Synchronization
Uncertainty
Figure 83. BDM host-to-target serial bit timing
The receive cases are more complicated. Figure 84 shows the host receiving a logic 1 from the target system. Since the host is
asynchronous to the target, there is up to one clock cycle delay from the host-generated falling edge on BKGD to the perceived start of
the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The
host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of
the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
Target System
Speedup
Pulse
Perceived
Start of Bit Time
High-impedance
High-impedance
High-impedance
R-C Rise
BKGD Pin
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Figure 84. BDM target-to-host serial bit timing (logic 1)
Earliest
Start of
Next Bit
Figure 85 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock cycle
delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time
but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then
briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.
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BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
High-impedance
Speedup Pulse
Target System
Drive and
Speedup Pulse
Perceived
Start of Bit Time
BKGD Pin
10 Cycles
10 Cycles
Earliest
Start of
Next Bit
Host Samples
BKGD Pin
Figure 85. BDM target-to-host serial bit timing (logic 0)
4.22.4.7
Serial interface hardware handshake protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be modified
when changing the settings for the VCO frequency (CPMUSYNR), it is very helpful to provide a handshake protocol in which the host
could determine when an issued command is executed by the CPU. The BDM clock frequency is always VCO frequency divided by 8.
The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could
be running. This sub-section will describe the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This
protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated
by the target MCU when a command, issued by the host, has been successfully executed (see Figure 86). This pulse is referred to as the
ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start
a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL(267) or TRACE1).
The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is
assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also
that, there is no upper limit for the delay between the command and the related ACK pulse, since the command execution depends upon
the CPU bus, which in some cases could be very slow due to long accesses taking place.This protocol allows a great flexibility for the
POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication.
BDM Clock
(Target MCU)
Target
Transmits
ACK Pulse
High-Impedance
32 Cycles
16 Cycles
High-Impedance
Speedup Pulse
Minimum Delay
From the BDM Command
BKGD Pin
Earliest
Start of
Next Bit
16th Tick of the
Last Command Bit
Figure 86. Target acknowledge pulse (ACK)
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NOTE
If the ACK pulse was issued by the target, the host assumes the previous command was executed.
If the CPU enters wait or stop prior to executing a hardware command, the ACK pulse will not be
issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM
command is no longer pending.
Figure 87 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example.
First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes
the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data,
the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK
pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word, and the host needs to determine which is
the appropriate byte, based on whether the address was odd or even.
Target
BKGD Pin READ_BYTE
Host
Host
(2) Bytes are
Retrieved
Byte Address
New BDM
Command
Host
Target
Target
BDM Issues the
ACK Pulse (out of scale)
BDM Executes the
READ_BYTE Command
BDM Decodes
the Command
Figure 87. Handshake protocol at command level
Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by
the target MCU by issuing a negative edge on the BKGD pin. The hardware handshake protocol in Figure 86 specifies the timing when
the BKGD pin is being driven, so the host should follow this timing constraint to avoid the risk of an electrical conflict on the BKGD pin.
NOTE
The only place the BKGD pin can have an electrical conflict is when one side is driving low and the
other side is issuing a speedup pulse (high). Other “highs” are pulled rather than driven. The time of
the speedup pulse can become lengthy at low rates, and so the potential conflict time becomes longer
as well.
The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host
needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters wait or stop while the
host issues a hardware command (e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.
Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued. After a certain time the
host (not aware of stop or wait) should decide to abort any possible pending ACK pulse, to be sure a new command can be issued. The
protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted.
NOTE
The ACK pulse does not provide a timeout. This means for the GO_UNTIL(267) command, it cannot
be distinguished if a stop or wait has been executed (command discarded and ACK not issued), or if
the “UNTIL” condition (BDM active) is just not reached yet. Therefore, where the ACK pulse of a
command is not issued, the possible pending command should be aborted before issuing a new
command. See the handshake abort procedure described in Section 4.22.4.8, “Hardware handshake
abort procedure".
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4.22.4.8
Hardware handshake abort procedure
The abort procedure is based on the SYNC command. To abort a command which had not issued the corresponding ACK pulse, the host
controller should generate a low pulse on the BKGD pin by driving it low for at least 128 serial clock cycles, and then driving it high for one
serial clock cycle, providing a speedup pulse. By detecting this long low pulse on the BKGD pin, the target executes the SYNC protocol,
see Section 4.22.4.9, “SYNC — request timed reference pulse", and assumes that the pending command, and therefore the related ACK
pulse, are being aborted. Therefore, after the SYNC protocol has been completed, the host is free to issue new BDM commands. For
BDM firmware READ or WRITE commands, it can not be guaranteed that the pending command is aborted, when issuing a SYNC before
the corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins until it is finished and the
corresponding ACK pulse is issued. The latency time depends on the firmware READ or WRITE command that is issued and on the
selected bus clock rate. When the SYNC command starts during this latency time, the READ or WRITE command will not be aborted, but
the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL(267) command can not be aborted. Only the
corresponding ACK pulse can be aborted by the SYNC command.
Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse on the BKGD pin, shorter than 128
serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived
by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, to allow the negative
edge to be detected by the target. In this case, the target will not execute the SYNC protocol, but the pending command will be aborted
along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short
abort pulse, where the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e.,
READ_BYTE). If the abort pulse is not perceived by the target, the host will attempt to send a new command after the abort pulse was
issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism.
However, if the command to be aborted is not a read command, the short abort pulse could be used. After a command is aborted, the
target assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command.
NOTE
The details about the short abort pulse are being provided only as a reference for the reader to better
understand the BDM internal behavior. It is not recommended that this procedure be used in a real
application.
Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the
lower possible target frequency. The host could issue a SYNC very close to the 128 serial clock cycles length, providing a small overhead
on the pulse length, to assure the SYNC pulse will not be misinterpreted by the target. See Section 4.22.4.9, “SYNC — request timed
reference pulse".
Figure 88 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the
command is aborted, a new command could be issued by the host computer.
SYNC Response
From the Target
(Out of Scale)
READ_BYTE CMD is Aborted
by the SYNC Request
(Out of Scale)
BKGD Pin READ_BYTE
Host
Memory Address
READ_STATUS
Target
Host
BDM Decode
and Starts to Execute
the READ_BYTE Command
Target
New BDM Command
Host
Target
New BDM Command
Figure 88. ACK abort procedure at the command level
NOTE
Figure 88 does not represent the signals in a true timing scale.
Figure 89 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected
to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command
at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command.
In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the
protocol does not prevent this conflict from happening.
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At Least 128 Cycles
BDM Clock
(Target MCU)
Target MCU
Drives to
BKGD Pin
Host
Drives SYNC
To BKGD Pin
ACK Pulse
High-impedance
Host and
Target Drive
to BKGD Pin
Electrical Conflict
Speedup Pulse
Host SYNC Request Pulse
BKGD Pin
16 Cycles
Figure 89. ACK pulse and sync request conflict
NOTE
This information is being provided so that the MCU integrator will be aware that such a conflict could
occur.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides
backwards compatibility with the existing POD devices, which are not able to execute the hardware handshake protocol. It also allows for
new POD devices supporting the hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
The commands are described as follows:
•
ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is
executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response.
•
ACK_DISABLE — disables the ACK pulse protocol The host needs to use the worst case delay time at the appropriate places
in the protocol.
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the
BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin,
and when the data bus cycle is complete. See Section 4.22.4.3, “BDM hardware commands" and Section 4.22.4.4, “Standard BDM
firmware commands" for more information on the BDM commands.
The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if
the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the
target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not
issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid command.
The BACKGROUND command issues an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related
to this command could be aborted using the SYNC command.
The GO command issues an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be
aborted using the SYNC command.
The GO_UNTIL(267) command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU
enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a
breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters
BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command
could be aborted using the SYNC command.
The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the
application program is executed. The ACK pulse related to this command could be aborted using the SYNC command.
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4.22.4.9
SYNC — request timed reference pulse
The SYNC command is unlike other BDM commands, because the host does not necessarily know the correct communication speed to
use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should
perform the following steps:
1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (The lowest serial
communication frequency is determined by the settings for the VCO clock (CPMUSYNR). The BDM clock frequency is always
VCO clock frequency divided by 8.)
2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.)
3. Remove all drive to the BKGD pin so it reverts to high-impedance.
4. Listen to the BKGD pin for the sync response pulse.
Upon detecting the SYNC request from the host, the target performs the following steps:
1. Discards any incomplete command received or bit retrieved.
2. Waits for BKGD to return to a logic one.
3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.
4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
6. Removes all drive to the BKGD pin so it reverts to high-impedance.
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM
communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed, and
the communication protocol can easily tolerate speed errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to
as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next negative
edge (issued by the host) as the start of a new BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC
command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization
problem. In this case, the command may not have been understood by the target, so an ACK response pulse will not be issued.
4.22.4.10 Instruction tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single
instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware, the BDM is active, and
ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates
stepping or tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed.
Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step, but peripherals are free running.
Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address pointing
to BDM firmware address space.
When tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is
traced:
The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving the low power mode. This is
the case because BDM active mode can not be entered after the CPU executed the stop instruction. However, all BDM hardware
commands except the BACKGROUND command are operational after tracing a stop or wait instruction, and still being in stop or
wait mode. If system stop mode is entered (all bus masters are in stop mode), no BDM command is operational.
As soon as stop or wait mode is exited, the CPU enters BDM active mode and the saved PC value points to the entry of the
corresponding interrupt service routine.
If the handshake feature is enabled, the corresponding ACK pulse of the TRACE1 command will be discarded when tracing a
stop or wait instruction. Hence, there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command, after
CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait mode or after CPU exited from
stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode has been
reached. After a system stop mode, the handshake feature must be enabled again by sending the ACK_ENABLE command.
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4.22.4.11 Serial communication timeout
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128
target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge
on BKGD, to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any timeout
limit.
Consider now the case where the host returns BKGD to a logic one before 128 cycles. This is interpreted as a valid bit transmission, and
not as a SYNC request. The target will keep waiting for another falling edge, marking the start of a new bit. If, a new falling edge is not
detected by the target within 512 clock cycles, since the last falling edge, a timeout occurs and the current command is discarded without
affecting memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued, but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to
be disregarded. The data is not available for retrieval after the timeout has occurred. This is expected behavior if the handshake protocol
is not enabled. To allow the data to be retrieved, even with a large clock frequency mismatch (between BDM and CPU) when the hardware
handshake protocol is enabled, the timeout between a read command and the data retrieval is disabled. Therefore, the host could wait
for more then 512 serial clock cycles, and still be able to retrieve the data from an issued read command. However, once the handshake
pulse (ACK pulse) is issued, the timeout feature is re-activated, meaning that the target will timeout after 512 clock cycles. The host needs
to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command
is discarded and the data is no longer available for retrieval. Any negative edge in the BKGD pin after the timeout period is considered to
be a new command or a SYNC request.
Note that whenever a partially issued command, or partially retrieved data has occurred, the timeout in the serial communication is active.
This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command
being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to
be disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new
BDM command, or the start of a SYNC request pulse.
4.23
S12 clock, reset, and power management unit (9S12I128PIMV1)
4.23.1
Introduction
This specification describes the function of the Clock, Reset, and Power Management Unit (9S12I128PIMV1).
•
The Pierce oscillator (OSCLCP) provides a robust, low noise and low power external clock source. It is designed for optimal
start-up margin with typical crystal oscillators
•
The voltage regulator (IVREG) operates from the range 3.13 to 5.5 V. It provides all the required chip internal voltages and
voltage monitors
•
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter
•
The Internal Reference Clock (IRC1M) provides a1.0 MHz clock
4.23.1.1
Features
The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with
low harmonic distortion, low power, and good noise immunity.
•
Supports crystals or resonators from 4.0 to 16 MHz
•
High noise immunity due to input hysteresis and spike filtering
•
Low RF emissions with peak-to-peak swing limited dynamically
•
Transconductance (gm) sized for optimum start-up margin for typical crystals
•
Dynamic gain control eliminates the need for external current limiting resistor
•
Integrated resistor eliminates the need for external bias resistor
•
Low power consumption: Operates from an internal 1.8 V (nominal) supply, amplitude control limits power
The Voltage Regulator (IVREG) has the following features:
•
Input voltage range from 3.13 to 5.5 V
•
Low voltage detect (LVD) with low voltage interrupt (LVI)
•
Power-on reset (POR)
•
Low voltage reset (LVR)
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The Phase Locked Loop (PLL) has the following features:
•
Highly accurate and phase locked frequency multiplier
•
Configurable internal filter for best stability and lock time
•
Frequency modulation for defined jitter and reduced emission
•
Automatic frequency lock detector
•
Interrupt request on entry or exit from locked condition
•
Reference clock either external (crystal) or internal square wave (1.0 MHz IRC1M) based
•
PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock
The Internal Reference Clock (IRC1M) has the following features:
•
Trimmable in frequency
•
Factory trimmed value for 1.0 MHz in Flash memory, can be overwritten by application if required
Other features of the 9S12I128PIMV1 include
•
Clock monitor to detect loss of crystal
•
Bus Clock Generator
— Clock switch to select either PLLCLK or external crystal/resonator based bus clock
— PLLCLK divider to adjust system speed
•
System Reset generation from the following possible sources:
— Power-on reset (POR)
— Low voltage reset (LVR)
— Illegal address access
— COP timeout
— Loss of oscillation (clock monitor fail)
— External pin RESET
4.23.1.2
Modes of operation
This subsection lists and briefly describes all operating modes supported by the 9S12I128PIMV1.
4.23.1.2.1
Run mode
The voltage regulator is in Full Performance mode (FPM).
The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
•
PLL Engaged Internal (PEI)
— This is the default mode after system reset and power-on reset.
— The bus clock is based on the PLLCLK.
— After reset the PLL is configured for 64 MHz VCOCLK operation. Post divider is 0x03, so PLLCLK is VCOCLK divided by 4,
that is 16 MHz and bus clock is 8.0 MHz. The PLL can be re-configured for other bus frequencies.
— The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
•
PLL Engaged External (PEE)
— The bus clock is based on the PLLCLK.
— This mode can be entered from default mode PEI by performing the following steps:
– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary.
– Enable the external oscillator (OSCE bit)
•
PLL Bypassed External (PBE)
— The bus clock is based on the oscillator clock (OSCCLK).
— This mode can be entered from default mode PEI by performing the following steps:
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1)
– Select the oscillator clock (OSCCLK) as bus clock (PLLSEL=0).
— The PLLCLK is still on to filter possible spikes of the external oscillator clock.
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4.23.1.2.2
Wait mode
For 9S12I128PIMV1 Wait mode is the same as Run mode.
4.23.1.2.3
Stop mode
This mode is entered by executing the CPU STOP instruction.
The voltage regulator is in Reduced Power mode (RPM).
The Phase Locked Loop (PLL) is off.
The internal reference clock (IRC1M) is off.
Core clock, bus clock and BDM clock are stopped.
Depending on the setting of the PSTP and the OSCE bit, Stop mode can be differentiated between Full Stop mode (PSTP = 0 or OSCE=0)
and Pseudo Stop mode (PSTP = 1 and OSCE=1).
•
Full Stop mode (PSTP = 0 or OSCE=0)
The external oscillator (OSCLCP) is disabled.
After wake-up from Full Stop mode the core clock and bus clock are running on PLLCLK (PLLSEL=1). After wake-up from Full
Stop mode the COP and RTI are running on IRCCLK (COPOSCSEL=0, RTIOSCSEL=0).
•
Pseudo Stop Mode (PSTP = 1 and OSCE=1)
The external oscillator (OSCLCP) continues to run. If the respective enable bits are set the COP and RTI will continue to run.
The clock configuration bits PLLSEL, COPOSCSEL, RTIOSCSEL are unchanged.
NOTE
When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full
Stop mode with OSCE bit already 1), the software must wait for a minimum time equivalent to the
startup-time of the external oscillator tUPOSC before entering Pseudo Stop mode.
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4.23.1.3
9S12I128PIMV1 block diagram
Illegal Address Access
MMC
VDD, VDDF
ILAF
(core supplies)
Low Voltage Interrupt VDDRX
VDDRX
VSS
LVDS
Low Voltage Interrupt
LVIE
Low Voltage Reset VDDRX
VSSRX
Voltage
Regulator
3.13 to 5.5V
LVRF
Power-On Detect
monitor fail
REFDIV[3:0]
IRCTRIM[9:0]
Reference
Divider
Internal
Reference
Clock
(IRC1M)
OSCE
Power-On Reset
Reset
Generator
System Reset
Oscillator status Interrupt
UPOSC
OSCIE
UPOSC=0 sets PLLSEL bit
CAN_OSCCLK
OSCCLK
adaptive
&
(to MSCAN)
spike
OSCFILT[4:0]
filter
PLLSEL
OSCBW
PSTP
S12CPMU
PORF
RESET
Clock
Monitor
Loop
Controlled
EXTAL
Pierce
Oscillator
(OSCLCP)
XTAL
4.0 MHz16 MH
COP timeout
POSTDIV[4:0]
Post
Divider
1,2,...,32
divide
by 4
ECLK2X
(Core Clock)
PLLCLK
ECLK
divide
by 2 (Bus Clock)
IRCCLK
(to LCD)
VCOFRQ[1:0]
divide
by 8
VCOCLK
Lock
detect
REFCLK
FBCLK
Phase
locked
Loop with
internal
Filter (PLL)
BDM Clock
REFFRQ[1:0]
LOCK
LOCKIE
PLL Lock Interrupt
Divide by
2*(SYNDIV+1)
UPOSC
SYNDIV[5:0]
RTIE
UPOSC=0 clears
IRCCLK
OSCCLK
IRCCLK
COP timeout
COPCLK COP
to Reset
Watchdog Generator
OSCCLK
COPOSCSEL
PCE
CPMUCOP
RTI Interrupt
Real Time
RTICLK Interrupt (RTI)
RTIOSCSEL
PRE
CPMURTI
Figure 90. Block diagram of 9S12I128PIMV1
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Figure 91 shows a block diagram of the OSCLCP.
OSCCLK
Peak
Detector
Gain Control
VDD = 1.8 V
VSS
Rf
XTAL
EXTAL
Figure 91. OSCLCP block diagram
4.23.2
Signal description
This section lists and describes the signals that connect off chip.
4.23.2.1
RESET
Pin RESET is an active-low bidirectional pin. As an input, it initializes the MCU asynchronously to a known start-up state. As an open-drain
output, it indicates that an MCU-internal reset has been triggered.
4.23.2.2
EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the external clock input or the input
to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal OSCCLK is derived from the EXTAL
input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 k, and the XTAL pin is pulled
down by an internal resistor of approximately 700 k.
NOTE
NXP recommends an evaluation of the application board and chosen resonator or crystal by the
resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals.
4.23.2.3
VSS — ground pin
VSS must be grounded.
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4.23.2.4
VDDRX, VSSRX— regulator power input pin and pad supply pins
VDDRX is the power input of IVREG and the PAD positive supply pin. All currents sourced into the regulator loads flow through this pin.The
VDDRX/VSSX supply domain is monitored by the low voltage reset circuit. An off-chip decoupling capacitor (100 nF...220 nF, X7R
ceramic) between VDDRX and VSSX can further improve the quality of this supply.
4.23.2.5
VDD — internal regulator output supply (core logic)
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the core logic. This supply domain
is monitored by the low voltage reset circuit.
4.23.2.6
VDDF — internal regulator output supply (NVM logic)
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic. This supply
domain is monitored by the low voltage reset circuit
4.23.3
Memory map and registers
This section provides a detailed description of all registers accessible in the 9S12I128PIMV1.
4.23.3.1
Module memory map
The 9S12I128PIMV1 registers are shown in Table 401.
Table 401. CPMU register summary
Address
Name
0x0034
CPMU
SYNR
0x0035
CPMU
REFDIV
0x0036
CPMU
POSTDIV
0x0037
CPMUFLG
0x0038
CPMUINT
0x0039
CPMUCLKS
0x003A
CPMUPLL
0x003B
CPMURTI
0x003C
CPMUCOP
0x003D
RESERVEDC
Bit 7
R
W
R
W
R
6
5
4
3
VCOFRQ[1:0]
2
W
R
0
REFFRQ[1:0]
0
0
0
RTIF
PORF
LVRF
0
0
W
R
W
R
RTIE
PLLSEL
PSTP
0
0
RTDEC
RTR6
WCOP
RSBCK
0
0
W
R
W
R
W
R
Bit 0
SYNDIV[5:0]
0
REFDIV[3:0]
POSTDIV[4:0]
W
R
1
LOCKIF
LOCK
LOCKIE
OSCIF
UPOSC
0
0
PRE
PCE
RTI
OSCSEL
COP
OSCSEL
0
0
0
0
RTR2
RTR1
RTR0
CR2
CR1
CR0
0
0
0
0
0
FM1
FM0
RTR5
RTR4
RTR3
0
0
0
0
0
WRTMASK
0
ILAF
OSCIE
0
W
= Unimplemented or Reserved
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Table 401. CPMU register summary (continued)
Address
Name
0x003E
RESERVEDC
0x003F
CPMU
ARMCOP
0x02F0
RESERVED
0x02F1
CPMU
LVCTL
W
RESERVED
R
0x02F2
0x02F3
0x02F4
0x02F5
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
LVDS
LVIE
LVIF
0
0
0
0
R
W
W
R
W
RESERVED
R
W
RESERVED
R
W
RESERVED
R
W
0x02F6
RESERVEDC
0x02F7
RESERVED
0x02F8
CPMU
IRCTRIMH
0x02F9
CPMU
IRCTRIML
0x02FA
CPMUOSC
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
IRCTRIM[9:8]
IRCTRIM[7:0]
W
R
0
TCTRIM[4:0]
OSCPINS_E
N
OSCE
OSCBW
OSCFILT[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
0x02FB
CPMUPROT
0x02FC
RESERVEDC
R
W
R
PROT
0
W
= Unimplemented or Reserved
4.23.3.2
Register descriptions
This section describes all the 9S12I128PIMV1 registers and their individual bits. Address order is as listed in Table 401.
4.23.3.2.1
9S12I128PIMV1 synthesizer register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range.
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Table 402. 9S12I128PIMV1 synthesizer register (CPMUSYNR)
0x0034
7
R
6
5
4
3
VCOFRQ[1:0]
W
Reset
0
2
1
0
1
1
1
SYNDIV[5:0]
1
0
1
1
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), Else write has no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
f VCO = 2 f REF SYNDIV + 1
If PLL has locked (LOCK=1)
NOTE
fVCO must be within the specified VCO frequency lock range. Bus frequency fBUS must not exceed
the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation, the VCOFRQ[1:0]
bits have to be selected according to the actual target VCOCLK frequency, as shown in Table 403. Setting the VCOFRQ[1:0] bits
incorrectly can result in a non functional PLL (no locking and/or insufficient stability).
Table 403. VCO clock frequency selection
VCOCLK Frequency Ranges
VCOFRQ[1:0]
32 MHz
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