MPC940LFAR2

MOTOROLA Freescale Semiconductor, Inc. Order this document by MPC940L/D SEMICONDUCTOR TECHNICAL DATA Freescale Semiconductor, Inc... Low Voltage 1:18 Clock Distribution Chip The MPC940L is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50Ω series or parallel terminated transmission lines. With output–to–output skews of 150ps, the MPC940L is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. For a similar device at a lower price/performance point the reader is referred to the MPC9109. • • • • • • MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP LVPECL or LVCMOS Clock Input 2.5V LVCMOS Outputs for Pentium II Microprocessor Support 150ps Maximum Output–to–Output Skew Maximum Output Frequency of 250MHz 32–Lead LQFP Packaging Dual or Single Supply Device: • Dual VCC Supply Voltage, 3.3V Core and 2.5V Output • Single 3.3V VCC Supply Voltage for 3.3V Outputs • Single 2.5V VCC Supply Voltage for 2.5V I/O FA SUFFIX 32–LEAD LQFP PACKAGE CASE 873A–02 With a low output impedance (≈20Ω), in both the HIGH and LOW logic states, the output buffers of the MPC940L are ideal for driving series terminated transmission lines. With a 20Ω output impedance the 940L has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. If a lower output impedance is desired please see the MPC942 data sheet. The differential LVPECL inputs of the MPC940L allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the MPC940L have internal pullup/pulldown resistor so they can be left open if unused. The MPC940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3V core and 3.3V output, a 3.3V core and 2.5V outputs as well as a 2.5V core and 2.5V outputs. The 32–lead LQFP package was chosen to optimize performance, board space and cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. 01/01  Motorola, Inc. 2001 For More Information On This Product, REV 3 1 Go to: www.freescale.com Freescale Semiconductor, Inc. MPC940L LOGIC DIAGRAM PECL_CLK PECL_CLK 0 LVCMOS_CLK 1 Q0 16 LVCMOS_CLK_Sel (Internal Pulldown) Q1–Q16 Q17 Q6 Q7 Q8 VCCI Q9 Q10 Q11 GND 24 23 22 21 20 19 18 17 GNDO 25 16 VCCO Q5 26 15 Q12 LVCMOS_CLK_Sel Q4 27 14 Q13 0 1 Q3 28 13 Q14 VCCO 29 12 GNDO Q2 30 11 Q15 Supply Pin Voltage Level Q1 31 10 Q16 VCCI VCCO 2.5V or 3.3V ± 5% 2.5V or 3.3V ± 5% Q0 32 9 Q17 3 4 5 6 LVCMOS_CLK LVCMOS_CLK_Sel PECL_CLK PECL_CLK 7 8 VCCO 2 VCCI 1 GNDI MPC940L GNDO Freescale Semiconductor, Inc... Pinout: 32–Lead TQFP (Top View) FUNCTION TABLE Input PECL_CLK LVCMOS_CLK POWER SUPPLY VOLTAGES PIN CONFIGURATIONS I/O Type Input LVPECL Reference Clock Input LVCMOS_CLK Input LVCMOS Alternative Reference Clock Input LVCMOS_CLK_SEL Input LVCMOS Selects Clock Source Q0–Q17 Output LVCMOS Clock Outputs Pin Function PECL_CLK PECL_CLK MOTOROLA VCCO Supply Output Positive Power Supply VCCI Supply Core Positive Power Supply GNDO Supply Output Negative Power Supply GNDI Supply Core Negative Power Supply For More Information On This Product, 2 Go to: www.freescale.com TIMING SOLUTIONS DL207 — Rev 0 Freescale Semiconductor, Inc. MPC940L ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VCC Supply Voltage –0.3 3.6 V VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current ±20 mA TStor Storage Temperature Range 125 °C –40 * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. DC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 3.3V ±5%; VCCO = 3.3V ±5%) Freescale Semiconductor, Inc... Symbol Characteristic Min Typ 2.4 Max Unit VCCI V 0.8 V VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak–to–Peak Input Voltage PECL_CLK 500 1000 mV VCMR Common Mode Range PECL_CLK VCC–1.4 VCC–0.6 V VOH Output HIGH Voltage VOL Output LOW Voltage IIN Input Current CIN Input Capacitance Cpd Power Dissipation Capacitance ZOUT Output Impedance ICC Maximum Quiescent Supply Current 2.4 V IOH = –20mA 0.5 V IOH = 20mA ±200 µA 4.0 pF 10 18 Condition pF 23 28 W 0.5 1.0 mA per output AC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 3.3V ±5%; VCCO = 3.3V ±5%) Symbol Characteristic Min Max Unit 250 MHz 2.7 2.5 3.4 3.0 ns 2.9 2.4 3.7 3.2 ns PECL_CLK CMOS_CLK 150 150 ps Note 1. Part–to–Part Skew PECL_CLK < 150MHz CMOS_CLK < 150MHz 1.4 1.2 ns Notes 1., 2. tsk(pp) Part–to–Part Skew PECL_CLK > 150MHz CMOS_CLK > 150MHz 1.7 1.4 ns Notes 1., 2. tsk(pp) Part–to–Part Skew PECL_CLK CMOS_CLK 850 750 ps Notes 1., 3. DC Output Duty Cycle fCLK < 134 MHz fCLK ≤ 250 MHz 55 60 % % Input DC = 50% Input DC = 50% 1.1 ns 0.5 – 2.4 V Fmax Maximum Input Frequency tPLH Propagation Delay PECL_CLK ≤ 150MHz CMOS_CLK ≤ 150MHz 2.0 1.8 tPLH Propagation Delay PECL_CLK > 150MHz CMOS_CLK > 150MHz 2.0 1.8 tsk(o) Output–to–Output Skew tsk(pp) 45 40 tr, tf Output Rise/Fall Time 0.3 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, Includes output skew. 3. For a specific temperature and voltage, Includes output skew. TIMING SOLUTIONS DL207 — Rev 0 Typ 50 50 For More Information On This Product, 3 Go to: www.freescale.com Condition Note 1. MOTOROLA Freescale Semiconductor, Inc. MPC940L DC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 3.3V ±5%; VCCO = 2.5V ±5%) Freescale Semiconductor, Inc... Symbol Characteristic Min Typ 2.4 Max Unit VCCI V 0.8 V VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak–to–Peak Input Voltage PECL_CLK 500 1000 mV VCMR Common Mode Range PECL_CLK VCC–1.4 VCC–0.6 V VOH Output HIGH Voltage VOL Output LOW Voltage IIN Input Current CIN Input Capacitance 4.0 pF Cpd Power Dissipation Capacitance 10 pF ZOUT Output Impedance 23 ICC Maximum Quiescent Supply Current 0.5 1.8 Condition V IOH = –20mA 0.5 V IOH = 20mA ±200 µA per output W 1.0 mA Max Unit AC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 3.3V ±5%; VCCO = 2.5V ±5%) Symbol Characteristic Min Typ Condition Fmax Maximum Input Frequency 250 MHz tPLH Propagation Delay PECL_CLK ≤ 150MHz CMOS_CLK ≤ 150MHz 2.0 1.7 2.8 2.5 3.5 3.0 ns tPLH Propagation Delay PECL_CLK > 150MHz CMOS_CLK > 150MHz 2.0 1.8 2.9 2.5 3.8 3.3 ns tsk(o) Output–to–Output Skew PECL_CLK CMOS_CLK 150 150 ps Note 1. tsk(pp) Part–to–Part Skew PECL_CLK < 150MHz CMOS_CLK < 150MHz 1.5 1.3 ns Notes 1., 2. tsk(pp) Part–to–Part Skew PECL_CLK > 150MHz CMOS_CLK > 150MHz 1.8 1.5 ns Notes 1., 2. tsk(pp) Part–to–Part Skew PECL_CLK CMOS_CLK 850 750 ps Notes 1., 3. DC Output Duty Cycle fCLK < 134 MHz fCLK ≤ 250 MHz 55 60 % % Input DC = 50% Input DC = 50% 1.2 ns 0.5 – 1.8 V 45 40 tr, tf Output Rise/Fall Time 0.3 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, Includes output skew. 3. For a specific temperature and voltage, Includes output skew. MOTOROLA 50 50 For More Information On This Product, 4 Go to: www.freescale.com Note 1. TIMING SOLUTIONS DL207 — Rev 0 Freescale Semiconductor, Inc. MPC940L DC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 2.5V ±5%; VCCO = 2.5V ±5%) Freescale Semiconductor, Inc... Symbol Characteristic Min Typ 2.0 Max Unit VCCI V 0.8 V VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak–to–Peak Input Voltage PECL_CLK 500 1000 mV VCMR Common Mode Range PECL_CLK VCC–1.0 VCC–0.6 V VOH Output HIGH Voltage VOL Output LOW Voltage IIN Input Current CIN Input Capacitance 4.0 pF Cpd Power Dissipation Capacitance 10 pF ZOUT Output Impedance ICC Maximum Quiescent Supply Current 1.8 18 Condition V IOH = –12mA 0.5 V IOH = 12mA ±200 µA 23 28 W 0.5 1.0 mA Max Unit per output AC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 2.5V ±5%; VCCO = 2.5V ±5%) Symbol Characteristic Min Typ Condition Fmax Maximum Input Frequency 200 MHz tPLH Propagation Delay PECL_CLK ≤ 150MHz CMOS_CLK ≤ 150MHz 2.6 2.3 4.0 3.1 5.2 4.0 ns tPLH Propagation Delay PECL_CLK > 150MHz CMOS_CLK > 150MHz 2.8 2.3 3.8 3.1 5.0 4.0 ns tsk(o) Output–to–Output Skew PECL_CLK CMOS_CLK 200 200 ps Note 1. tsk(pp) Part–to–Part Skew PECL_CLK < 150MHz CMOS_CLK < 150MHz 2.6 1.7 ns Notes 1., 2. tsk(pp) Part–to–Part Skew PECL_CLK > 150MHz CMOS_CLK > 150MHz 2.2 1.7 ns Notes 1., 2. tsk(pp) Part–to–Part Skew PECL_CLK CMOS_CLK 1.2 1.0 ns Notes 1., 3. DC Output Duty Cycle fCLK < 134 MHz fCLK ≤ 250 MHz 55 60 % % Input DC = 50% Input DC = 50% 1.2 ns 0.5 – 1.8 V 45 40 tr, tf Output Rise/Fall Time 0.3 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, Includes output skew. 3. For a specific temperature and voltage, Includes output skew. TIMING SOLUTIONS DL207 — Rev 0 50 50 For More Information On This Product, 5 Go to: www.freescale.com Note 1. MOTOROLA Freescale Semiconductor, Inc. MPC940L MPC940L DUT Pulse Generator Z = 50 ZO = 50Ω ZO = 50Ω W RT = 50Ω RT = 50Ω VTT VTT Figure 1. LVCMOS_CLK MPC940L AC test reference for Vcc = 3.3V and Vcc = 2.5V MPC940L DUT ZO = 50Ω Differential Pulse Generator Z = 50 ZO = 50Ω Freescale Semiconductor, Inc... W RT = 50Ω RT = 50Ω VTT VTT Figure 2. PECL_CLK MPC940L AC test reference for Vcc = 3.3V and Vcc = 2.5V PECL_CLK VCC VCC 2 B LVCMOS_CLK VCMR VPP PECL_CLK GND VCC VCC 2 B Q VCC VCC 2 B Q GND GND tPD tPD Figure 3. Propagation delay (tPD) test reference Figure 4. LVCMOS Propagation delay (tPD) test reference VCC VCC 2 VCC VCC 2 GND GND B B tP VOH VCC 2 B T0 GND DC = tP /T0 x 100% tSK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The pin–to–pin skew is defined as the worst case difference in propagation delay between any two similar delay path within a single device Figure 5. Output Duty Cycle (DC) tF Figure 6. Output–to–output Skew tSK(O) VCC=3.3V 2.4 VCC=2.5V 1.8V VCC=3.3V 2.0 VCC=2.5V 1.7V 0.55 0.6V 0.8 0.7V tR Figure 7. Output Transition Time Test Reference MOTOROLA tF tR Figure 8. Input Transition Time Test Reference For More Information On This Product, 6 Go to: www.freescale.com TIMING SOLUTIONS DL207 — Rev 0 Freescale Semiconductor, Inc. MPC940L OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX QFP PACKAGE CASE 873A–02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE H W K X DETAIL AD TIMING SOLUTIONS DL207 — Rev 0 Q_ 0.250 (0.010) C E GAUGE PLANE Freescale Semiconductor, Inc... P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X For More Information On This Product, 7 Go to: www.freescale.com MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MPC940L Motorola reserves the right to make changes without further notice to any products herein. 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