MPC97H73FA

 Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA    
    The MPC97H73 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Features • 1:12 PLL based low-voltage clock generator Order Number: MPC97H73/D Rev 0, 10/2003
  3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Freescale Semiconductor, Inc... • 3.3V power supply • Internal power–on reset • Generates clock signals up to 240 MHz • Maximum output skew of 250 ps • Differential PECL reference clock input • Two LVCMOS PLL reference clock inputs • External PLL feedback supports zero-delay capability • Various feedback and output dividers (see application section) • Supports up to three individual generated output clock frequencies • Synchronous output clock stop circuitry for each individual output for FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D power down support • Drives up to 24 clock lines • Ambient temperature range 0°C to +70°C • Pin and function compatible to the MPC973 Functional Description The MPC97H73 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC97H73 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC97H73 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non–binary factor. The MPC97H73 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC97H73. The MPC97H73 has an internal power–on reset. The MPC97H73 is fully 3.3V compatible and requires no external loop filter components. All inputs (except PCLK) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 W transmission lines. For series terminated transmission lines, each of the MPC97H73 outputs can drive one or two traces giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.  Motorola, Inc. 2003 For1 More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC97H73 ## $%&'( )*+$+(,)+ -./* . /.#'* ,0 1Ω     1     *0 0   0 ÷2 0 ÷1 1 0 ÷! ÷! ÷! ÷ 1 ÷! ÷! ÷! ÷ 1  
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              Freescale Semiconductor, Inc...  .%1 Figure 2. MPC97H73 52–Lead Package Pinout (Top View) MOTOROLA 2 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC97H73 Table 1. PIN CONFIGURATION Freescale Semiconductor, Inc... Pin I/O Type Function CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock PCLK, PCLK Input LVPECL Differential LVPECL reference clock FB_IN Input LVCMOS PLL feedback signal input, connect to an QFB CCLK_SEL Input LVCMOS LVCMOS clock reference select REF_SEL Input LVCMOS LVCMOS/PECL reference clock select VCO_SEL Input LVCMOS VCO operating frequency select PLL_EN Input LVCMOS PLL enable/PLL bypass mode select MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset FSEL_A[0:1] Input LVCMOS Frequency divider select for bank A outputs FSEL_B[0:1] Input LVCMOS Frequency divider select for bank B outputs FSEL_C[0:1] Input LVCMOS Frequency divider select for bank C outputs FSEL_FB[0:2] Input LVCMOS Frequency divider select for the QFB output INV_CLK Input LVCMOS Clock phase selection for outputs QC2 and QC3 STOP_CLK Input LVCMOS Clock input for clock stop circuitry STOP_DATA Input LVCMOS Configuration data input for clock stop circuitry QA[0-3] Output LVCMOS Clock outputs (Bank A) QB[0-3] Output LVCMOS Clock outputs (Bank B) QC[0-3] Output LVCMOS Clock outputs (Bank C) QFB Output LVCMOS PLL feedback output. Connect to FB_IN. QSYNC Output LVCMOS Synchronization pulse output GND Supply Ground Negative power supply VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 2. FUNCTION TABLE (Configuration Controls) Control Default 0 1 REF_SEL 1 Selects CCLKx as the PLL reference clock Selects the LVPECL inputs as the PLL reference clock CCLK_SEL 1 Selects CCLK0 Selects CCLK1 VCO_SEL 1 Selects VCO÷2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). Selects VCO÷1. (high VCO frequency range) PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC97H73 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Normal operation mode with PLL enabled. INV_CLK 1 QC2 and QC3 are in phase with QC0 and QC1 QC2 and QC3 are inverted (180° phase shift) with respect to QC0 and QC1 MR/OE 1 Outputs disabled (high-impedance state) and device is reset. During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC97H73 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power–on reset (POR) circuitry during power–up. Outputs enabled (active) VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the applications section for supported frequency ranges and output to input frequency ratios. TIMING SOLUTIONS 3 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC97H73 Table 3. Output Divider Bank A (NA) Table 5. Output Divider Bank C (NC) VCO_SEL FSEL_A1 FSEL_A0 QA[0:3] VCO_SEL FSEL_C1 FSEL_C0 QC[0:3] 0 0 0 VCO÷8 0 0 0 VCO÷4 0 0 1 VCO÷12 0 0 1 VCO÷8 0 1 0 VCO÷16 0 1 0 VCO÷12 0 1 1 VCO÷24 0 1 1 VCO÷16 1 0 0 VCO÷4 1 0 0 VCO÷2 1 0 1 VCO÷6 1 0 1 VCO÷4 1 1 0 VCO÷8 1 1 0 VCO÷6 1 1 1 VCO÷12 1 1 1 VCO÷8 Freescale Semiconductor, Inc... Table 4. Output Divider Bank B (NB) VCO_SEL FSEL_B1 FSEL_B0 0 0 0 QB[0:3] VCO÷8 0 0 1 VCO÷12 0 1 0 VCO÷16 0 1 1 VCO÷20 1 0 0 VCO÷4 1 0 1 VCO÷6 1 1 0 VCO÷8 1 1 1 VCO÷10 Table 6. Output Divider PLL Feedback (M) VCO_SEL FSEL_FB2 FSEL_FB1 FSEL_FB0 0 0 0 0 VCO÷8 0 0 0 1 VCO÷12 0 0 1 0 VCO÷16 0 0 1 1 VCO÷20 0 1 0 0 VCO÷16 0 1 0 1 VCO÷24 0 1 1 0 VCO÷32 0 1 1 1 VCO÷40 1 0 0 0 VCO÷4 1 0 0 1 VCO÷6 1 0 1 0 VCO÷8 1 0 1 1 VCO÷10 1 1 0 0 VCO÷8 1 1 0 1 VCO÷12 1 1 1 0 VCO÷16 1 1 1 1 VCO÷20 MOTOROLA 4 For More Information On This Product, Go to: www.freescale.com QFB TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC97H73 Table 7. GENERAL SPECIFICATIONS Symbol Characteristics Min Typ Max Unit VCC B 2 VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 HBM Condition V V ESD Protection (Human Body Model) 2000 V LU Latch–Up Immunity 200 mA CPD Power Dissipation Capacitance 12 pF Per output CIN Input Capacitance 4.0 pF Inputs Table 8. ABSOLUTE MAXIMUM RATINGSa Freescale Semiconductor, Inc... Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 3.9 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V ±20 mA ±50 mA 125 °C VOUT IIN IOUT TS DC Input Current DC Output Current Storage Temperature -65 Condition a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 9. DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C) Max Unit VCC_PLL Symbol PLL Supply Voltage 3.0 VCC V LVCMOS VIH Input High Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input Low Voltage 0.8 V LVCMOS VPP Peak–to–peak Input Voltage PCLK, PCLK 250 mV LVPECL Common Mode Range 1.0 V LVPECL V IOH=-24 mAb 0.55 0.30 V V IOL= 24 mA IOL= 12 mA ±200 µA VIN = VCC or GND 13.5 mA VCC_PLL Pin 35 mA All VCC Pins VCMRa VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN ICC_PLL ICCQ a. b. c. Characteristics Min PCLK, PCLK Typ VCC – 0.6 2.4 W 8 - 11 Input Currentc Maximum PLL Supply Current 8.0 Maximum Quiescent Supply Current Condition VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. The MPC97H73 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. Inputs have pull–down resistors affecting the input current. TIMING SOLUTIONS 5 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC97H73 Table 10. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)a b Symbol fREF Characteristics Min ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback Input reference frequency Typ 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Freescale Semiconductor, Inc... Input reference frequency in PLL bypass mode fVCO VCO frequency rangec fMAX Output Frequency fSTOP_CLK Serial interface clock frequency VPP Peak-to-peak input voltage PCLK, PCLK VCMRd Common Mode Range PCLK, PCLK ÷2 output ÷4 output ÷6 output ÷8 output ÷10 output ÷12 output ÷16 output ÷20 output ÷24 output Widthd tPW,MIN Input Reference Pulse tR, tF CCLKx Input Rise/Fall Timee t(∅) Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz PLL locked PLL bypass 250 MHz 480 MHz 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 MHz MHz MHz MHz MHz MHz MHz MHz MHz 20 MHz 400 1000 mV LVPECL 1.2 VCC-0.9 V LVPECL 2.0 Propagation Delay (static phase 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF=50 MHz and feedback=÷8 Output-to-output Skewg DC Output Duty Cycleh tR, tF Output Rise/Fall Time tPLZ, HZ Output Disable Time tPZL, LZ Output Enable Time tJIT(CC) Cycle-to-cycle jitteri tJIT(PER) Period Jitterj tJIT(∅) I/O Phase Jitter RMS (1 σ)k PLL locked ns 1.0 ns +3 +4 +166 ° ° ps 100 100 100 250 ps ps ps ps (T÷2) +200 ps 1.0 ns 8.0 ns 0.8 to 2.0V PLL locked -3 -4 -166 within QA outputs within QB outputs within QC outputs all outputs (T÷2) - 200 T÷2 0.1 150 ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback 6 Condition 200 offset)f tSK(O) MOTOROLA Max 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 For More Information On This Product, Go to: www.freescale.com 8.0 ns 200 ps 150 ps 11 86 13 88 16 19 21 22 27 30 ps ps ps ps ps ps ps ps ps ps 0.55 to 2.4V (VCO=400 MHz) TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC97H73 Table 10. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)a b Symbol Freescale Semiconductor, Inc... a b c d e f g h i j k l Characteristics BW PLL closed loop bandwidthl tLOCK Maximum PLL Lock Time Min ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback Typ Max 1.20 - 3.50 0.70 - 2.50 0.50 - 1.80 0.45 - 1.20 0.30 - 1.00 0.25 - 0.70 0.20 - 0.55 0.17 - 0.40 0.12 - 0.30 0.11 - 0.28 Unit Condition MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 10 ms AC characteristics apply for parallel output termination of 50Ω to VTT. The input reference frequency must match the VCO lock range divided by the feedback divider ratio: fREF= fVCO ÷ (M ⋅ VCO_SEL). VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% - DCREF, MIN. The MPC97H73 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(∅), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t(∅) [s] = t(∅) [°] ÷ (fREF ⋅ 360°). Excluding QSYNC output. See application section for part-to-part skew calculation. Output duty cycle is DC = (0.5 ± 200 ps ⋅ fOUT) ⋅ 100%. E.g. the DC range at fOUT=100MHz is 48%
**?@.61A MPC97H73 example configuration (feedback of QFB = 33.3 MHz, fVCO=400 MHz, VCO_SEL=÷1, M=12, NA=12, NB=4, NC=2). MPC97H73 example configuration (feedback of QFB = 25 MHz, fVCO=250 MHz, VCO_SEL=÷1, M=10, NA=4, NB=4, NC=2). Frequency range Min Max Frequency range Min Max Input 16.6 MHz 40 MHz Input 20 MHz 48 MHz QA outputs 16.6 MHz 40 MHz QA outputs 50 MHz 120 MHz QB outputs 50 MHz 120 MHz QB outputs 50 MHz 120 MHz QC outputs 100 MHz 240 MHz QC outputs 100 MHz 240 MHz MOTOROLA 8 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC97H73 Individual Output Disable (Clock Stop) Circuitry MPC97H73 writing logic ‘0’ to the respective stop enable bit. Likewise, the user may programmably enable an output clock by writing logic ‘1’ to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would be in normally in logic low state, eliminating the possibility of short or ‘runt’ clock pulses. The user can write to the serial input register through the STOP_DATA input by supplying a logic ‘0’ start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free–running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC97H73 can sample each STOP_DATA bit with the rising edge of the free–running STOP_CLK signal. (see Figure 5. ) The individual clock stop (output enable) control of the MPC97H73 allows designers, under software control, to implement power management into the clock distribution design. A simple serial interface and a clock stop control logic provides a mechanism through which the MPC97H73 clock outputs can be individually stopped in the logic ‘0’ state: The clock stop mechanism allows serial loading of a 12–bit serial input register. This register contains one programmable clock stop bit for 12 of the 14 output clocks. The QC0 and QFB outputs cannot be stopped (disabled) with the serial port. The user can program an output clock to stop (disable) by Freescale Semiconductor, Inc...                   Figure 5. Clock Stop Circuit Programming TIMING SOLUTIONS 9 For More Information On This Product, Go to: www.freescale.com MOTOROLA MPC97H73 Freescale Semiconductor, Inc. SYNC Output Description The MPC97H73 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC97H73 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies. Figure 6. shows various waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs. 0 

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 >÷A >÷A  Figure 6. QSYNC Timing Diagram MOTOROLA 10 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MPC97H73 Power Supply Filtering Using the MPC97H73 in zero–delay applications The MPC97H73 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC97H73 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA_PLL pin for the MPC97H73. Figure 7. illustrates a typical power supply filter scheme. The MPC97H73 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 8 mA (13.5 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 7. “VCC_PLL Power Supply Filter” must have a resistance of 5-10W to meet the voltage drop criteria. Nested clock trees are typical applications for the MPC97H73. Designs using the MPC97H73 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC97H73 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. 
< 7Ω The MPC97H73 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC97H73 are connected together, the maximum overall timing uncertainty from the common CCLKx input to any output is: tSK(PP) = t( ∅) + tSK(O) + tPD, LINE(FB) + tJIT( ∅)
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 SECTION AB–AB ROTATED 90_ CLOCKWISE MOTOROLA 16 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC97H73 Freescale Semiconductor, Inc... NOTES TIMING SOLUTIONS 17 For More Information On This Product, Go to: www.freescale.com MOTOROLA MPC97H73 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES MOTOROLA 18 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC97H73 Freescale Semiconductor, Inc... NOTES TIMING SOLUTIONS 19 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... MPC97H73 Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. E Motorola Inc. 2003 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 TECHNICAL INFORMATION CENTER: 1–800–521–6274 or 480–768–2130 HOME PAGE: http://motorola.com/semiconductors JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu, Minato–ku, Tokyo 106–8573 Japan 81–3–3440–3569 MOTOROLA ◊ 20 For More Information On This Product, Go to: www.freescale.com MPC97H73/D TIMING SOLUTIONS