NX3DV42GU,115

NX3DV42 Dual high-speed USB 2.0 double-pole double-throw analog switch Rev. 3.1 — 20 October 2016 Product data sheet 1. General description The NX3DV42 is a double-pole double-throw analog switch suitable for use as an analog or digital multiplexer/demultiplexer. Its wide bandwidth and low bit-to-bit skew allows the NX3DV42 to pass high-speed differential signals with good signal integrity. Its high channel to channel crosstalk rejection results in minimal noise interference. The bandwidth is wide enough to pass high-speed USB 2.0 differential signals (480 Mb/s). It consist of two switches, each with two independent input/outputs (HSDn+ and HSDn) and a common input/output (D+ or D). One digital input (S) is used to select the switch position. When pin OE is HIGH, the switches are turned off. Schmitt trigger action at the select input (S) and output enable input (OE) makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 3.0 V to 4.3 V. 2. Features and benefits        Supply voltage range from 3.0 V to 4.3 V 4  typical ON resistance 7.3 pF typical ON capacitance 950 MHz typical bandwidth or data frequency Low crosstalk of 30 dB at 240 MHz Break-before-make switching ESD protection:  HBM JESD22-A114F Class 3A exceeds 4000 V  CDM AEC-Q100-011 revision B exceeds 1000 V  HBM exceeds 12000 V for power to GND protection  Latch-up performance exceeds 100 mA per JESD 78 Class II Level A  Specified from 40 C to +125 C 3. Applications  Cell phone, PDA, digital camera and notebook  LCD monitor, TV and set-top box NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version NX3DV42GU 40 C to +125 C XQFN10 plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.40 x 1.80 x 0.50 mm SOT1160-1 NX3DV42GU10 40 C to +125 C XQFN10 plastic extremely thin small outline package; no leads; SOT1337-1 10 terminals; body 1.3 x 1.6 x 0.5 mm NX3DV42GU33 40 C to +125 C X2QFN10 plastic extremely thin small outline package; no leads; SOT1430-1 10 terminals; body 1.3 x 1.6 x 0.33 mm 5. Marking Table 2. Marking Type number Marking code NX3DV42GU x4 NX3DV42GU10 x4 NX3DV42GU33 x4 6. Functional diagram HSD1DHSD2HSD1+ D+ HSD2+ S OE aaa-001356 Fig 1. Logic symbol NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 2 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 7. Pinning information 7.1 Pinning 8 OE terminal 1 index area 9 VCC 10 S NX3DV42 6 HSD2- HSD1+ 5 D- 2 HSD1- 4 7 HSD2+ GND 3 D+ 1 aaa-001357 Transparent top view Fig 2. Pin configuration SOT1160-1(XQFN10), SOT1337-1 (XQFN10) and SOT1430-1(X2QFN10) 7.2 Pin description Table 3. Pin description Symbol SOT1160-1, SOT1337-1, SOT1430-1 Description HSD1, HSD2 4, 6 independent input or output HSD1+, HSD2+ 5, 7 independent input or output D+, D 1, 2 common output or input GND 3 ground (0 V) OE 8 output enable input (active LOW) S 10 select input VCC 9 supply voltage 8. Functional description Table 4. Function table[1] Input Channel on S OE L L HSD1+ and HSD1 H L HSD2+ and HSD2 X H switch off [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 3 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions [1] Max Unit 0.5 +5.5 V 0.5 +5.5 V 0.5 +5.5 V VI input voltage VSW switch voltage IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current VI < 0.5 V 50 - mA ISW switch current - 100 mA ICC supply current - +50 mA Tstg storage temperature 65 +150 C - 250 mW total power dissipation Ptot pins S and OE Min Tamb = 40 C to +125 C [1] The minimum input voltage rating may be exceeded if the input current rating is observed. [2] For XQFN10 package: above 100 C derate linearly with 4 mW/K. [2] 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VSW switch voltage Tamb ambient temperature [1] Conditions pins S and OE [1] Min Max Unit 3.0 4.3 V 0 4.5 V 0 VCC V 40 +125 C To avoid sinking GND current from terminals D+ and D when switch current flows in terminals HSDn+ and HSDn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals D+ and D, no GND current will flow from terminals HSDn+ and HSDn. In this case, there is no limit for the voltage drop across the switch. NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 4 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Min VIH VIL Typ[1] Max Tamb = 40 C to +125 C Unit Min Max HIGH-level input voltage VCC = 3.0 V to 3.6 V 1.3 - - 1.3 - V VCC = 4.3 V 1.7 - - 1.7 - V LOW-level input voltage VCC = 3.0 V to 3.6 V - - 0.5 - 0.5 V VCC = 4.3 V - - 0.7 - 0.7 V VIK input clamping VCC = 3.0 V; II = 18 mA voltage - - 1.2 - 1.2 V II input leakage current pins S and OE; VI = GND to 4.3 V; VCC = 4.3 V; see Figure 4 - - 1 - 10 A IS(OFF) OFF-state leakage current VCC = 4.3 V; see Figure 3 and Figure 6 - - 1 - 2 A IOFF power-off leakage current VI or VO = 0 V to 4.3 V; VCC = 0 V; see Figure 7 - - 1 - 10 A ICC supply current VI = VCC or GND; VCC = 4.3 V; VSW = GND or VCC; see Figure 5 - - 1 - 10 A ICC additional VI = 2.6 V; VCC = 4.3 V; supply current VSW = GND or VCC - - 10 - 10 A VI = 1.8 V; VCC = 4.3 V; VSW = GND or VCC - - 15 - 15 A CI input capacitance pins S and OE - 1.0 - - - pF CS(OFF) OFF-state capacitance pins HSDn+ and HSDn VCC = 3.3 V; VI = 0 V to 3.3 V - 2.8 - - - pF CS(ON) ON-state capacitance pins D+ and DVCC = 3.3 V; VI = 0 V to 3.3 V - 7.3 - - - pF [1] Typical values are measured at Tamb = 25 C and VCC = 3.3 V. NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 5 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 11.1 Test circuit and graphs VCC VIL or VIH S switch S 1 VIL 2 VIH HSD1- 1 D- switch HSD2- 2 IS OE GND VIH VI VO aaa-001365 VI = VCC or GND and VO = GND or VCC. Test circuit also applies for D+, HSD1+ and HSD2+. Fig 3. Test circuit for measuring OFF-state leakage current DDD  ,O Q$ DDD  ,&& —$                 7DPEƒ& VCC = 4.3 V. Fig 4. Product data sheet     7DPEƒ& VCC = 4.3 V. Waveform showing the typical input leakage current versus temperature NX3DV42  Fig 5. Waveform showing the typical supply current versus temperature All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 6 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch DDD  ,62)) Q$                    7DPEƒ& VCC = 4.3 V. Fig 6. DDD  ,2)) Q$ Product data sheet     7DPEƒ& VCC = 4.3 V. Waveform showing the typical OFF-state leakage current versus temperature NX3DV42  Fig 7. Waveform showing the typical power-off leakage current versus temperature All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 7 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 11.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter RON ON resistance Tamb = 40 C to +85 C Conditions Min Max Min - 3.9 6.5 - - 0.65 - - Unit Max VI = 0.4 V; ISW = 8 mA; see Figure 8 VCC = 3.0 V RON Tamb = 40 C to +125 C Typ[1]  10 [2] ON resistance VI = 0.4 V; ISW = 8 mA mismatch between VCC = 3.0 V channels [1] Typical values are measured at Tamb = 25 C. [2] Measured at identical VCC, temperature and input voltage. -  11.3 ON resistance test circuit VCC S VIL or VIH V VSW switch S 1 VIL 2 VIH HSD1- 1 D- switch HSD2- 2 OE VIL GND VI ISW aaa-001366 RON = VSW / ISW. Test circuit also applies for D+, HSD1+ and HSD2+. Fig 8. Test circuit for measuring ON resistance NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 8 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter propagation delay tpd Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - 0.25 - - - - 11.2 30 - 40 ns - 3.9 25 - 30 ns 2.0 5.9 - 2.0 - ns [3] - 20 - - - ps [3] - 200 - - - ps [2][3] HSDn+ to D+ or HSDn to Dor D+ to HSDn+ or D to HSDn; see Figure 9 VCC = 3.3 V ten enable time S or OE to D+ or D; see Figure 10 tdis disable time S or OE to D+ or D; see Figure 10 VCC = 3.0 V to 3.6 V [5] VCC = 3.0 V to 3.6 V break-before-make see Figure 11 time VCC = 3.0 V to 3.6 V tb-m tsk(p) pulse skew time [1] jitter time [3] see Figure 9 VCC = 3.0 V to 3.6 V tjit ns [4] RL = 50 ; CL = 5 pF; tr, tf = 500 ps (10 % to 90 %) at 480 Mbs (PRBS = 215  1) Typical values are measured at Tamb = 25 C, CL = 5 pF and VCC = 3.3 V. [2] tpd is the same as tPLH and tPHL. [3] Guaranteed by design. [4] ten is the same as tPZH. [5] tdis is the same as tPHZ. NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 9 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 12.1 Waveforms and test circuits 400 mV input 50% GND tPLH tPHL VOH 50% output VOL aaa-001359 Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. tsk(p) = |tPHL  tPLH|. Fig 9. The data input to output propagation delay times and pulse skew time VI S, OE input VM GND tPHZ output HIGH to OFF OFF to HIGH VOH tPZH VX VX GND switch enabled switch disabled switch enabled aaa-001361 Measurement points are given in Table 10. Logic level: VOH is the typical output voltage level that occurs with the output load. Fig 10. Enable and disable times Table 10. Measurement points Supply voltage Input VCC VM VI VX 3.0 V to 3.6 V 0.5VCC VCC 0.9VOH NX3DV42 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 10 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch VCC S HSD1- DHSD2OE VIL VI G V VO RL CL VEXT = 0.8 V GND aaa-001364 a. Test circuit. VI 0.5VI 0.9VO 0.9VO VO t b-m 001aag572 b. Input and output measurement points. Test circuit also applies for D+, HSD1+ and HSD2+. Fig 11. Test circuit for measuring break-before-make timing VCC S HSD1- DHSD2OE VIL VI G CL RL VEXT = 0.8 V GND aaa-001363 Test circuit also applies for D+, HSD1+ and HSD2+. Test data is given in Table 11. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. VI may be connected to S or OE. Fig 12. Test circuit for measuring switching times NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 11 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch Table 11. Test data Supply voltage Input Load VCC VI tr, tf CL RL 3.0 V to 3.6 V VCC  2.5 ns 5 pF 50  12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise specified); tr = tf < 2.5 ns. Symbol Parameter f(3dB) Tamb = 25 C Conditions 3 dB frequency response RL = 50 ; see Figure 13 Min Max - 950 - MHz - 450 - MHz - 30 - dB - 30 - [1] CL = 0 pF; VCC = 3.0 V to 3.6 V CL = 5 pF; VCC = 3.0 V to 3.6 V iso isolation (OFF-state) fi = 240 MHz; RL = 50 ; see Figure 14 Xtalk crosstalk between switches; fi = 240 MHz; RL = 50 ; see Figure 15 [1] VCC = 3.0 V to 3.6 V [1] VCC = 3.0 V to 3.6 V [1] fi is biased at 0.5VCC. [2] Typical values are measured at Tamb = 25 C and VCC = 3.3 V. Unit Typ[2] dB 12.3 Test circuits 0.5VCC VCC VIL or VIH S HSD1- 1 D- switch S 1 VIL 2 VIH RL switch HSD2- 2 OE VIL fi CL dB GND aaa-001360 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB. Test circuit also applies for D+, HSD1+ and HSD2+. Fig 13. Test circuit for measuring the frequency response when channel is in ON-state NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 12 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 0.5VCC 0.5VCC VCC RL S VIL or VIH RL switch S 1 VIH 2 VIL HSD1- 1 D- switch HSD2- 2 OE fi GND VIH dB aaa-001367 Adjust fi voltage to obtain 0 dBm level at input. Test circuit also applies for D+, HSD1+ and HSD2+. Fig 14. Test circuit for measuring isolation (OFF-state) 0.5VCC D+ fi 50 Ω VIL RL CHANNEL HSD1+ or ON HSD2+ V VO1 S 0.5VCC Ri 50 Ω RL HSD1 or HSD2 D CHANNEL OFF V VO2 aaa-001362 20 log10 (VO2/VO1) or 20 log10 (VO1/VO2). Fig 15. Test circuit for measuring crosstalk between switches NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 13 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 13. Package outline XQFN10: plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.40 x 1.80 x 0.50 mm SOT1160-1 X A B D terminal 1 index area E A A1 A3 detail X e1 e 3 5 C C A B C v w b y y1 C L 2 6 1 7 e2 terminal 1 index area 10 L1 8 0 1 scale Dimensions Unit(1) mm max nom min 2 mm A A1 0.5 0.05 A3 b 0.25 0.127 0.20 0.15 0.00 D E 1.5 1.4 1.3 1.9 1.8 1.7 e e1 0.4 0.8 e2 0.4 L L1 0.45 0.55 0.40 0.50 0.35 0.45 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1160-1 --- --- --- sot1160-1_po European projection Issue date 09-12-28 09-12-29 Fig 16. Package outline SOT1160-1 (XQFN10) NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 14 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch ;4)1SODVWLFH[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGVWHUPLQDOVERG\[[PP ' % 627 $ $ WHUPLQDO LQGH[DUHD $ $ ( GHWDLO; H & Y Z E   & $ % & \ & \ /     H N WHUPLQDO LQGH[DUHD   ; / /   'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP PD[ QRP PLQ $  $ $ E ' PP VFDOH (              H H   N /  / /          Y  Z \ \    1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627  02  VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH   Fig 17. Package outline SOT1337-1 (XQFN10) NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 15 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch ;4)1SODVWLFH[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGVWHUPLQDOVERG\[[PP ' 627 $ % EDOO$ LQGH[DUHD $ ( $ $ GHWDLO; H & ‘Y ‘Z E    & $ % & \ & \ /   H   N EDOO$ LQGH[DUHD    ; / /  PP VFDOH 'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP $ $ $ E ' ( PD[      QRP     PLQ     H H   N /  / /          Y Z \ \     1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 2XWOLQH YHUVLRQ 5HIHUHQFHV ,(& 627 -('(& -(,7$ VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH   02 Fig 18. Package outline X2QFN10 NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 16 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model LCD Liquid Crystal Display MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes NX3DV42 v.3.1 20161020 Product data sheet - NX3DV42 v.3 - NX3DV42 v.2 Modifications: NX3DV42 v.3 Modifications: NX3DV42 v.2 Modifications: NX3DV42 v.1 NX3DV42 Product data sheet • • Added NX3DV42GU33 Removed NX3DV42GM 20130213 • • • • Values added for Tamb = +125 C throughout the data sheet. Type number NX3DV42GU10 added (Table 1). Marking code for type number NX3DV42GU10 added (Table 2). Package outline drawing SOT1337-1 added (Figure 17). 20120618 • Product data sheet Product data sheet - NX3DV42 v.1 Package outline drawing SOT1049-2 changed to SOT1049-3 (Figure 17). 20120103 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 - © NXP Semiconductors N.V. 2016. All rights reserved. 17 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 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NX3DV42 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 18 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 19 of 20 NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 18. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 11.3 12 12.1 12.2 12.3 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuit and graphs . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ON resistance test circuit . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms and test circuits . . . . . . . . . . . . . . 10 Additional dynamic characteristics . . . . . . . . . 12 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 October 2016 Document identifier: NX3DV42