P1023NSE5BFB

QorIQ Multicore Processor Development P1 Series P1023 and P1017 high-performance QorIQ communications processors Freescale QorIQ communications platforms The P1023 processor includes a performance- The QorIQ P1023 processor integrates a rich are the next-generation evolution of our optimized implementation of the QorIQ Data set of interfaces including SerDes, Gigabit leading PowerQUICC communications Path Acceleration Architecture (DPAA). This Ethernet, three PCI Express® controller and processors. Built using high-performance architecture provides the infrastructure to USB. The two 10/100/1000 Ethernet ports Power Architecture cores, QorIQ platforms support simplified sharing of networking support advanced packet parsing, flow control enable a new era of networking innovation interfaces and accelerators by multiple and quality of service features, as well as IEEE® where the reliability, security and quality of CPU cores. The DPAA significantly reduces 1588 time-stamping—all ideal for managing the service for every connection matters. software overhead associated with high touch data path traffic between the LAN and WAN packet forwarding operations. Examples of interface. Four SerDes lanes can be portioned the types of packet processing services this across three PCI Express ports and two SGMII architecture is optimized to support include ports. The PCI Express ports can provide The P1023 and P1017 processors offer the traditional routing and bridging, firewall, connectivity to IEEE 802.11n and 802.11ac value of extensive integration including a high- VPN termination for IPSec and MACSec (a radio cards for wireless support. USB or SD/ performance data path which can off-load standardized form of Ethernet encapsulation MMC interfaces can be used to support local specific protocol processing from the CPUs. that can be used to provide confidentiality). storage. The P1023 and P1017 are ideally suited for The 256 KB L2 cache offers incremental Target Applications ® QorIQ P1023 and P1017 Communications Processors high-performance enterprise WLAN, fixed routers and security gateway applications. The P1023 device supports 500 MHz in dual core mode or 800 MHz in single core mode, along with advanced security and a rich set of interfaces—all delivered on 45 nm technology for low power implementation. configuration to partition the cache between the two cores or to configure it as SRAM or stashing memory. The integrated security features include support for data integrity and authenticity protection over Ethernet, as well as a security engine which supports cryptographic algorithms commonly used in IPsec, SSL, 3GPP and other networking and wireless security protocols. It also provides header and trailer offload for security protocols such as IPSec, SSL/TLS, SRTP 802.1ae, 802.11i and 802.16e. The memory controller offers future-proofing against memory technology migration with support for DDR3/ DDR3L. The P1023 and P1017 processors serve a wide variety of applications. The devices are well-suited for various combinations of data plane and control plane workloads in networking and telecom applications. With an available junction temperature range of -40ºC to +105ºC, the devices can be used in power-sensitive defense and industrial applications, as well as outdoor environments less protected from the environment. The devices primarily target applications such as networking and telecom linecards. A wireless router or business gateway requires a combination of high performance and a rich QorIQ P1023/17 Communication Processors QorIQ P1023/17 Communication Processors set of peripherals to support the data path Power Architecture® e500-v2 Core throughputs and required system functionality. The P1017 single-core and P1023 dual-core 32 KB D-Cache devices offer a scalable platform to develop a range of products that can support the same feature set. Integrated 10/100/1000 Ethernet controllers with data path offload for classification and QoS capabilities are ideal for managing the data path traffic between the LAN and WAN interface. PCI Express ports USB 2.0 256 KB Frontside Cache 32 KB I-Cache 32-bit DDR3/3L Memory Controller P1017–Single Core Only eLBC Coherent System Bus SD/MMC DUART Frame Manager 2x I2C Security 4.2 SPI, GPIO Queue Mgr. can provide connectivity to IEEE 802.11n and 802.11ac radio cards for wireless support, Buffer Mgr. the USB or SD/MMC interfaces can be used DMA Parse, Classify, Distribute PCIe 1 GE 1 GE PCle PCIe to support local storage, and the integrated 4-Lane 2.5 GHz SerDes security engine can provide encrypted secure communications for remote users with VPN support. Core Complex (CPU and L2 Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements Technical Specifications • Single (P1017) and dual (P1023) highperformance Power Architecture e500 cores 36-bit physical addressing Double-precision floating-point support 32 KB L1 instruction cache and 32 KB L1 data cache for each core • High-speed interfaces (not all available simultaneously) Three PCI Express controllers Two SGMII interfaces Four SerDes to 3.125 GHz multiplexed across controllers • Integrated security engine (SEC 4.2) 400 MHz to 800 MHz core clock Crypto algorithm support includes frequency 3DES, AES, RSA/ECC, MD5/ • 256 KB L2 cache with ECC, also SHA, ARC4, SNOW 3G and FIPS configurable as SRAM and stashing deterministic RNG memory Single pass encryption/message • Two 10/100/1000 Mbps three-speed Ethernet controllers TCP/IP acceleration and classification capabilities authentication for common security protocols (IPsec, SSL, SRTP, DTLS) XOR acceleration • High-Speed USB controllers (USB 2.0) IEEE 1588 support Host and device support Lossless flow control Enhanced host controller interface RGMII, SGMII ULPI interface to PHY MACSec (IEEE 802.1ae) encapsulation • Enhanced secure digital host controller and decapsulation • Serial peripheral interface • 32-bit DDR3/DDR3L SDRAM memory controller • Programmable interrupt controller compliant with OpenPIC standard • Four-channel DMA controller • Two I2C controllers, DUART, timers • Enhanced local bus controller • 16 general-purpose I/O signals • Package: 457-pin wirebond power-BGA (TEPBGA1) Enablement • Green Hills® Software: Complete portfolio of software and hardware development tools, trace tools and real-time operating systems • Mentor Graphics®: Commercial grade Linux® solution • CodeSourcery: GCC and GDB tool chain • Development system For more information, visit freescale.com/QorIQ Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Document Number: QORIQP1023FS REV 1