P82B96
Dual bidirectional bus buffer
Rev. 8.1 — 20 December 2021
1
Product data sheet
General description
The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface
2
2
between the normal I C-bus and a range of other bus configurations. It can interface I Cbus logic signals to similar buses having different voltage and current levels.
For example, it can interface to the 350 μA SMBus, to 3.3 V logic devices, and to 15 V
levels and/or low-impedance lines to improve noise immunity on longer bus lengths.
2
It achieves this interface without any restrictions on the normal I C-bus protocols or clock
2
speed. The IC adds minimal loading to the I C-bus node, and loadings of the new bus or
2
remote I C-bus nodes are not transmitted or transformed to the local node. Restrictions
2
on the number of I C-bus devices in a system, or the physical separation between them,
are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission
lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals may be directly
connected, without causing latching, to provide an alternative bidirectional signal line with
2
I C-bus properties.
2
Features
2
• Bidirectional data transfer of I C-bus signals
• Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side
• Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive
buses
• 400 kHz operation over at least 20 meters of wire (see AN10148)
2
• Supply voltage range of 2 V to 15 V with I C-bus logic levels on Sx/Sy side
independent of supply voltage
2
• Splits I C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with
opto-electrical isolators and similar devices that need unidirectional input and output
signal paths.
• Low power supply current
• ESD protection exceeds 3500 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
• Latch-up free (bipolar process with no latching structures)
• Packages offered: SO8 and TSSOP8
3
Applications
2
• Interface between I C-buses operating at different logic levels (for example, 5 V and
3 V or 15 V)
2
• Interface between I C-bus and SMBus (350 µA) standard
P82B96
NXP Semiconductors
Dual bidirectional bus buffer
2
• Simple conversion of I C-bus SDA or SCL signals to multi-drop differential bus
hardware, for example, via compatible PCA82C250
2
• Interfaces with opto-couplers to provide opto-isolation between I C-bus nodes up to
400 kHz
4
Ordering information
Table 1. Ordering information
Type number
Topside
marking
Package
Name
Description
Version
P82B96DP
82B96
TSSOP8
plastic thin shrink small outline package; 8 leads; body width 3
mm
SOT505-1
P82B96TD
P82B96T
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
P82B96TD/S900
P82B96T
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
4.1 Ordering options
Table 2. Ordering options
[1]
Type number
Orderable part
number
Package
Packing method
P82B96DP
P82B96DPZ
[2]
TSSOP8
REEL 13" Q1/T1 NDP SSB
P82B96TD
P82B96TD/S900
P82B96DP,118
P82B96TD,118
P82B96TD/S900,118
TSSOP8
SO8
SO8
REEL 13" Q1/T1 NDP
REEL 13" Q1/T1 NDP
REEL 13" Q1/T1 NDP
[1]
[2]
[3]
5
[3]
Minimum
order
quantity
Temperature
2500
Tamb = -40 °C to +85 °C
2500
2500
2500
Tamb = -40 °C to +85 °C
Tamb = -40 °C to +85 °C
Tamb = -40 °C to +125 °C
Standard packing quantities and other packaging data are available at www.nxp.com/packages/.
Orderable part number P82B96DPZ is a drop in alternate for P82B96DP,118.
This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in sealed bag between uses.
Block diagram
VCC (2 V to 15 V)
8
Sx (SDA)
1
P82B96
3
2
Sy (SCL)
5
7
6
Tx (TxD, SDA)
Rx (RxD, SDA)
Ty (TxD, SCL)
Ry (RxD, SCL)
4
GND
002aab976
Figure 1. Block diagram of P82B96
P82B96
Product data sheet
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
6
Pinning information
6.1 Pinning
P82B96TD
P82B96TD/S900
Sx
1
8
VCC
Rx
2
7
Sy
Tx
3
6
Ry
GND
4
5
Ty
002aab978
Figure 2. Pin configuration for SO8
Sx
1
8
VCC
Rx
2
7
Sy
Tx
3
6
Ry
GND
4
5
Ty
P82B96DP
002aab979
Figure 3. Pin configuration for TSSOP8
6.2 Pin description
Table 3. Pin description
7
Symbol
Pin
Description
Sx
1
I C-bus (SDA or SCL)
Rx
2
receive signal
Tx
3
transmit signal
GND
4
negative supply
Ty
5
transmit signal
Ry
6
receive signal
Sy
7
I C-bus (SDA or SCL)
VCC
8
positive supply voltage
2
2
Functional description
Refer to Figure 1.
2
The P82B96 has two identical buffers allowing buffering of both of the I C-bus (SDA and
SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the
2
I C-bus interface pin which drives the buffered bus, and a reverse signal path from the
2
buffered bus input to drive the I C-bus interface. Thus these paths are:
2
• sense the voltage state of the I C-bus pin Sx (or Sy) and transmit this state to the pin
Tx (Ty respectively), and
2
• sense the state of the pin Rx (Ry) and pull the I C-bus pin LOW whenever Rx (Ry) is
LOW.
P82B96
Product data sheet
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
The rest of this discussion will address only the ‘x’ side of the buffer; the ‘y’ side is
identical.
2
2
The I C-bus pin (Sx) is designed to interface with a normal I C-bus.
2
The logic threshold voltage levels on the I C-bus are independent of the IC supply VCC.
2
The maximum I C-bus supply voltage is 15 V and the guaranteed static sink current is
3 mA.
The logic level of Rx is determined from the power supply voltage VCC of the chip.
Logic LOW is below 42 % of VCC, and logic HIGH is above 58 % of VCC (with a typical
switching threshold of half VCC).
Tx is an open-collector output without ESD protection diodes to VCC. It may be connected
via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is
2
not exceeded. It has a larger current sinking capability than a normal I C-bus device,
being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic
pull-down capability as well.
2
A logic LOW is only transmitted to Tx when the voltage at the I C-bus pin (Sx) is below
2
0.6 V. A logic LOW at Rx will cause the I C-bus (Sx) to be pulled to a logic LOW level in
2
accordance with I C-bus requirements (maximum 1.5 V in 5 V applications) but not low
enough to be looped back to the Tx output and cause the buffer to latch LOW.
2
The minimum LOW level this chip can achieve on the I C-bus by a LOW at Rx is typically
0.8 V.
2
If the supply voltage VCC fails, then neither the I C-bus nor the Tx output will be held
LOW. Their open-collector configuration allows them to be pulled up to the rated
maximum of 15 V even without VCC present. The input configuration on Sx and Rx also
present no loading of external signals even when VCC is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise
times, is less than 7 pF for all bus voltages and supply voltages including VCC = 0 V.
Remark: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design
2
does not support this configuration. Bidirectional I C-bus signals do not allow any
direction control pin so, instead, slightly different logic low voltage levels are used at
2
Sx/Sy to avoid latching of this buffer. A ‘regular I C-bus LOW’ applied at the Rx/Ry of a
P82B96 will be propagated to Sx/Sy as a ‘buffered LOW’ with a slightly higher voltage
level. If this special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second
2
P82B96 will not recognize it as a ‘regular I C-bus LOW’ and will not propagate it to its
Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that
rely on special logic thresholds for their operation, for example PCA9511, PCA9515, or
2
PCA9518. The Sx/Sy side is only intended for, and compatible with, the normal I C-bus
2
logic voltage levels of I C-bus master and slave chips, or even Tx/Rx signals of a second
2
P82B96 if required. The Tx/Rx and Ty/Ry I/O pins use the standard I C-bus logic voltage
2
levels of all I C-bus parts. There are no restrictions on the interconnection of the Tx/Rx
and Ty/Ry I/O pins to other P82B96s, for example in a star or multipoint configuration
with the Tx/Rx and Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to
the line card slave devices. For more details see Application Note AN255.
P82B96
Product data sheet
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
8
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages with respect to pin
GND.
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
VCC to GND
-0.3
+18
V
VSx
voltage on pin Sx
VTx
I C-bus SDA or SCL
voltage on pin Tx
-0.3
+18
V
buffered output
[1]
-0.3
+18
V
receive input
[1]
-0.3
+18
V
VRx
voltage on pin Rx
In
current on any pin
-
250
mA
Ptot
total power dissipation
-
300
mW
Tj
junction temperature
-40
+125
°C
Tstg
storage temperature
-55
+125
°C
Tamb
ambient temperature
-40
+85
°C
[1]
9
2
operating range
P82B96TD/S900
operating
See also Section 10.2.
Characteristics
Table 5. Characteristics
Tamb = +25 °C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified.
Symbol
Parameter
Conditions
Tamb = +25 °C
Tamb = -40 °C
[1]
to +125 °C
Unit
Min
Typ
Max
Min
Max
2.0
-
15
2.0
15
V
Power supply
VCC
supply voltage
operating
ICC
supply current
buses HIGH
-
0.9
1.8
-
3
mA
VCC = 15 V; buses
HIGH
-
1.1
2.5
-
4
mA
per Tx or Ty LOW
-
1.7
3.5
-
3.5
mA
-
-
15
-
15
V
0.2
-
3
0.2
3
mA
ΔICC
additional quiescent
supply current
Bus pull-up (load) voltages and currents
2
VSx, VSy
maximum input/output
voltage
open-collector; I Cbus and VRx, VRy =
HIGH
ISx, ISy
static output loading on
2
I C-bus
VSx, VSy = 1.0 V; VRx,
VRy = LOW
ISx, ISy
dynamic output sink
2
capability on I C-bus
VSx, VSy = 2 V; VRx,
VRy = LOW
7
18
-
7
-
mA
ISx, ISy
leakage current on I Cbus
2
VSx, VSy = 5 V; VRx,
VRy = HIGH
-
-
1
-
10
μA
P82B96
Product data sheet
[2]
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
Table 5. Characteristics...continued
Tamb = +25 °C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified.
Symbol
Parameter
Conditions
Tamb = +25 °C
VSx, VSy = 15 V; VRx,
VRy = HIGH
Tamb = -40 °C
[1]
to +125 °C
Unit
Min
Typ
Max
Min
Max
-
1
-
-
10
μA
VTx, VTy
maximum output voltage open-collector
level
-
-
15
-
15
V
ITx, ITy
static output loading on
buffered bus
VTx, VTy = 0.4 V; VSx,
2
VSy = LOW on I C-bus
= 0.4 V
-
-
30
-
30
mA
ITx, ITy
dynamic output sink
capability, buffered bus
VTx, VTy > 1 V; VSx,
2
VSy = LOW on I C-bus
= 0.4 V
60
100
-
60
-
mA
ITx, ITy
leakage current on
buffered bus
VTx, VTy = VCC = 15 V;
VSx, VSy = HIGH
-
1
-
-
10
μA
Input currents
2
ISx, ISy
input current from I Cbus
bus LOW; VRx, VRy =
HIGH
-
-1
-
-
-10
μA
IRx, IRy
input current from
buffered bus
bus LOW; VRx, VRy =
0.4 V
-
-1
-
-
-10
μA
IRx, IRy
leakage current on
buffered bus input
VRx, VRy = VCC
-
1
-
-
10
μA
Output logic LOW level
VSx, VSy
dVSx/dT,
dVSy/dT
output logic level LOW
2
on normal I C-bus
temperature coefficient
of output LOW levels
ISx, ISy = 3 mA
[3]
0.8
0.88
1.0
(see Figure 5)
V
ISx, ISy = 0.2 mA
[3]
670
730
790
(see Figure 4)
mV
ISx, ISy = 0.2 mA
[3]
-
-1.8
-
2
[4]
-
640
600
(see Figure 6)
mV
2
[4]
700
650
-
(see Figure 7)
mV
-
-2
-
-
-
mV/K
-
-
mV/K
Input logic switching threshold voltages
VSx, VSy
input logic voltage LOW on normal I C-bus
VSx, VSy
input logic level HIGH
threshold
dVSx/dT,
dVSy/dT
temperature coefficient
of input thresholds
VRx, VRy
input logic HIGH level
fraction of applied VCC
0.58VCC
-
-
0.58VCC
-
V
VRx, VRy
input threshold
fraction of applied VCC
-
0.5VCC
-
-
-
V
VRx, VRy
input logic LOW level
fraction of applied VCC
-
-
0.42VCC
-
50
85
-
50
on normal I C-bus
0.42VCC V
Logic level threshold difference
VSx, VSy
input/output logic level
difference
VSx output LOW at
0.2 mA - VSx input
HIGH maximum
[2]
-
mV
Thermal resistance
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
Table 5. Characteristics...continued
Tamb = +25 °C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified.
Symbol
Rth(j-pcb)
Parameter
Conditions
thermal resistance from SOT96-1 (SO8);
junction to printed-circuit average lead
board
temperature at board
interface
Tamb = +25 °C
Tamb = -40 °C
[1]
to +125 °C
Min
Typ
Max
Min
Max
-
127
-
-
-
Unit
K/W
Bus release on VCC failure
VSx, VSy,
VTx, VTy
VCC voltage at which all
buses are guaranteed to
be released
-
-
1
dV/dT
temperature coefficient
of guaranteed release
voltage
-
-4
-
-
-
mV/K
Buffer response time
(see Figure 8)
V
[5]
Tfall delay
buffer time delay on
VSx to VTx, falling input between
VSy to VTy VSx = input switching
threshold, and VTx
output falling 50 %
RTx pull-up = 160 Ω;
no capacitive load;
VCC = 5 V
-
70
-
-
-
ns
Trise delay
buffer time delay on
VSx to VTx, rising input between
VSy to VTy VSx = input switching
threshold, and VTx
output reaching 50 %
VCC
RTx pull-up = 160 Ω;
no capacitive load;
VCC = 5 V
-
90
-
-
-
ns
Tfall delay
buffer time delay on
VRx to VSx, falling input between
VRy to VSy VRx = input switching
threshold, and VSx
output falling 50 %
RSx pull-up = 1500 Ω;
no capacitive load;
VCC = 5 V
-
250
-
-
-
ns
Trise delay
buffer time delay on
VRx to VSx, rising input between
VRy to VSy VRx = input switching
threshold, and VSx
output reaching 50 %
VCC
RSx pull-up = 1500 Ω;
no capacitive load;
VCC = 5 V
-
270
-
-
-
ns
effective input
capacitance of any
signal pin measured
by incremental bus
rise times
-
-
7
-
7
pF
Input capacitance
Ci
[1]
[2]
[3]
input capacitance
Limit data for +125 °C applies to P82B96TD/S900 version. It is guaranteed by design/characterization, but not by 100 % test.
The minimum value requirement for pull-up current, 200 μA, guarantees that the minimum value for VSx output LOW will always exceed the minimum VSx
input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While the tolerances on absolute
levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal
applications. In any design the Sx pins of different ICs should never be linked because the resulting system would be very susceptible to induced noise
2
and would not support all I C-bus operating modes.
The output logic LOW depends on the sink current. For scaling, see Application Note AN255.
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
[4]
[5]
The input logic threshold is independent of the supply voltage.
The fall time of VTx from 5 V to 2.5 V in the test is approximately 15 ns.
The fall time of VSx from 5 V to 2.5 V in the test is approximately 50 ns.
The rise time of VTx from 0 V to 2.5 V in the test is approximately 20 ns.
The rise time of VSx from 0.9 V to 2.5 V in the test is approximately 70 ns.
002aac069
1000
VOL
(mV)
800
(1)
600
(2)
(3)
400
- 50
- 25
0
25
50
75
100
125
Tj (°C)
VOL at Sx typical and limits over temperature
1. Maximum
2. Typical
3. Minimum
Figure 4. VOL as a function of junction temperature (IOL = 0.2 mA)
002aac070
1200
VOL
(mV)
1000
(1)
800
(2)
(3)
600
400
- 50
- 25
0
25
50
75
100
125
Tj (°C)
VOL at Sx typical and limits over temperature
1. Maximum
2. Typical
3. Minimum
Figure 5. VOL as a function of junction temperature (IOL = 3 mA)
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
002aac071
1000
VIL(max)
(mV)
800
600
400
200
- 50
- 25
0
25
50
75
100
125
Tj (°C)
VIL(max) at Sx changes over temperature range
Figure 6. VIL(max) as a function of junction temperature
002aac072
1000
VIH(min)
(mV)
800
600
400
200
- 50
- 25
0
25
50
75
100
125
Tj (°C)
VIH(min) at Sx changes over temperature range
Figure 7. VIH(min) as a function of junction temperature
002aac075
1400
VCC(max)
(mV)
1200
1000
800
600
400
- 50
- 25
0
25
50
75
100
125
Tj (°C)
Figure 8. VCC(max) that guarantees bus release limit over temperature
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
10 Application information
Refer to AN460 and AN255 for more application detail.
+VCC (2 V to 15 V)
+5 V
Tx
(SDA)
I2C-bus
SDA
Rx
(SDA)
1/
2
R1
'SDA' (new levels)
P82B96
002aab986
2
Figure 9. Interfacing an ‘I C’ type of bus with different logic levels
+VCC
R2
+VCC1
R4
R5
+5 V
R1
I2C-bus
SDA
I2C-bus
SDA
R3
Rx
(SDA)
Tx
(SDA)
1/
2
P82B96
002aab987
2
Figure 10. Galvanic isolation of I C-bus nodes via opto-couplers
main enclosure
3.3 V to 5 V
remote control enclosure
12 V
12 V
3.3 V to 5 V
long cables
SDA
SDA
3.3 V to 5 V
12 V
3.3 V to 5 V
SCL
SCL
P82B96
P82B96
002aab988
2
Figure 11. Long distance I C-bus communications
2
Figure 12 shows how a master I C-bus can be protected against short circuits or failures
in applications that involve plug and socket connections and long cables that may
become damaged. A simple circuit is added to monitor the SDA bus, and if its LOW
time exceeds the design value, then the master bus is disconnected. P82B96 will free
all its I/Os if its supply is removed, so one option is to connect its VCC to the output of a
logic gate from, say, the 74LVC family. The SDA and SCL lines could be timed and VCC
disabled via the gate if one or other lines exceeds a design value of ‘LOW’ period as in
Figure 28 of AN255. If the supply voltage of logic gates restricts the choice of VCC supply
then the low-cost discrete circuit in Figure 12 can be used. If the SDA line is held LOW,
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
the 100 nF capacitor will charge and the Ry input will be pulled towards VCC. When it
exceeds 0.5VCC the Ry input will set the Sy input HIGH, which in practice means simply
releasing it.
In this example the SCL line is made unidirectional by tying the Rx pin to VCC. The state
of the buffered SCL line cannot affect the master clock line which is allowed when clockstretching is not required. It is simple to add an additional transistor or diode to control
the Rx input in the same way as Ry when necessary. The +V cable drive can be any
voltage up to 15 V and the bus may be run at a lower impedance by selecting pull-up
resistors for a static sink current up to 30 mA. VCC1 and VCC2 may be chosen to suit the
connected devices. Because DDC uses relatively low speeds (< 100 kHz), the cable
2
length is not restricted to 20 m by the I C-bus signalling, but it may be limited by the
video signalling.
+V cable drive
VCC1
100 nF
VCC
Rx
SCL
Sx
100
kΩ
3 m to 20 m
cables
BC
847B
Ry
VCC2
VCC
Tx
I2C-bus/DDC
master
SDA
+V cable drive
I2C-bus/DDC
Rx
Tx
Sx
I2C-bus/DDC
slave
Ry
4.7 kΩ
Sy
Ty
P82B96
SCL
Ty
Sy
470 kΩ
SDA
P82B96
BC
847B
GND
470 kΩ
monitor/flat TV
GND
PC/TV receiver/decoder box
R
G
B
video signals
002aab989
Figure 12. Extending a DDC bus
Figure 13 shows that P82B96 can achieve high clock rates over long cables. While
calculating with lumped wiring capacitance yields reasonable approximations to actual
timing, even 25 meters of cable is better treated using transmission line theory. Flat
ribbon cables connected as shown, with the bus signals on the outer edge, will have
a characteristic impedance in the range 100 Ω to 200 Ω. For simplicity they cannot be
terminated in their characteristic impedance but a practical compromise is to use the
minimum pull-up allowed for P82B96 and place half this termination at each end of the
cable. When each pull-up is below 330 Ω, the rising edge waveforms have their first
voltage ‘step’ level above the logic threshold at Rx and cable timing calculations can be
based on the fast rise/fall times of resistive loading plus simple one-way propagation
delays. When the pull-up is larger, but below 750 Ω, the threshold at Rx will be crossed
after one signal reflection. So at the sending end it is crossed after 2 times the one-way
propagation delay and at the receiving end after 3 times that propagation delay. For
flat cables with partial plastic dielectric insulation (by using outer cores) the one-way
propagation delays will be about 5 ns per meter. The 10 % to 90 % rise and fall times on
the cable will be between 20 ns and 50 ns, so their delay contributions are small. There
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
will be ringing on falling edges that can be damped, if required, by using Schottky diodes
as shown.
When the Master SCL HIGH and LOW periods can be programmed separately, for
example using control registers I2SCLH and I2SCLL of 89LPC932, the timings can allow
for bus delays. The LOW period should be programmed to achieve the minimum 1300 ns
plus the net delay in the slave's response data signal caused by bus and buffer delays.
The longest data delay is the sum of the delay of the falling edge of SCL from master to
slave and the delay of the rising edge of SDA from slave data to master. Because the
buffer will ‘stretch’ the programmed SCL LOW period, the actual SCL frequency will be
lower than calculated from the programmed clock periods. In the example for 25 meters
the clock is stretched 400 ns, the falling edge of SCL is delayed 490 ns and the SDA
rising edge is delayed 570 ns. The required additional LOW period is (490 ns + 570 ns)
2
= 1060 ns and the I C-bus specifications already include an allowance for a worst case
bus rise time 0 % to 70 % of 425 ns. (The bus rise time can be 300 ns 30 % to 70 %,
which means it can be 425 ns 0 % to 70 %. The 25 meter cable delay times as quoted
already include all rise and fall times.) Therefore, the microcontroller only needs to be
programmed with an additional (1060 ns - 400 ns - 425 ns) = 235 ns, making a total
programmed LOW period 1535 ns. The programmed LOW will the be stretched by 400
ns to yield an actual bus LOW time of 1935 ns, which, allowing the minimum HIGH period
of 600 ns, yields a cycle period of 2535 ns or 394 kHz.
Note that in both the 100 meter and 250 meter examples, the capacitive loading on the
2
I C-buses at each end is within the maximum allowed Standard mode loading of 400
pF, but exceeds the Fast mode limit. This is an example of a ‘hybrid’ mode because it
relies on the response delays of Fast mode parts but uses (allowable) Standard mode
bus loadings with rise times that contribute significantly to the system delays. The cables
cause large propagation delays, so these systems need to operate well below the 400
kHz limit, but illustrate how they can still exceed the 100 kHz limit provided all parts
are capable of Fast mode operation. The fastest example illustrates how the 400 kHz
limit can be exceeded, provided masters and slaves have the required timings, namely
smaller than the maximum allowed for Fast mode. Many NXP slaves have delays shorter
than 600 ns and all Fm+ devices must be < 450 ns.
+V cable drive
VCC1
R2
SCL
VCC
Rx
Sx
Sy
Rx
R2
Tx
Tx
Sx
Ry
Ry
R1
R1
Ty
R1
R1
GND
SCL
I2C-BUS
SLAVE(S)
Ty
cable
P82B96
C2
R2
VCC
R2
I2C-BUS
MASTER
SDA
VCC2
Sy
SDA
C2
C2
P82B96
propagation
delay ≈ 5 ns/m
C2
BAT54A
BAT54A
GND
002aab990
Figure 13. Driving ribbon or flat telephone cables
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
Table 6. Examples of bus capability
Refer to Figure 13.
+VCC1
+V cable
+VCC2
R1 (Ω)
R2 (Ω)
C2
(pF)
Cable
length
Cable
capacitance
Cable
delay
Set master nominal SCL
HIGH period
LOW period
Effective bus
clock speed
Maximum slave
response delay
5V
12 V
5V
750
2.2 k
400
250 m
n/a (delay based)
1.25 μs
600 ns
4000 ns
120 kHz
Normal spec. 400 kHz
parts
5V
12 V
5V
750
2.2 k
220
100 m
n/a (delay based)
500 ns
600 ns
2600 ns
185 kHz
Normal spec. 400 kHz
parts
3.3 V
5V
3.3 V
330
1k
220
25 m
1 nF
125 ns
600 ns
1500 ns
390 kHz
Normal spec. 400 kHz
parts
3.3 V
5V
3.3 V
330
1k
100
3m
120 pF
15 ns
600 ns
1000 ns
500 kHz
600 ns
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
10.1 Calculating system delays and bus clock frequency for a Fast mode
system
local master bus
buffered expansion bus
VCCM
remote slave bus
VCCB
Rm
SCL
MASTER
VCCS
Rb
Sx
P82B96
Tx/Rx
Rs
Tx/Rx
P82B96
SCL
SLAVE
Sx
I2C-BUS
I2C-BUS
Cm
Cb
master bus
capacitance
Cs
buffered bus
wiring capacitance
slave bus
capacitance
GND (0 V)
002aab991
9
Effective delay of SCL at slave: 255 + 17VCCM + (2.5 + 4 × 10 Cb)VCCB + 10VCCS ns.
C = F; V = volts.
Figure 14. Falling edge of SCL at master is delayed by the buffers and bus fall times
local master bus
buffered expansion bus
VCCM
VCCB
SCL
MASTER
Rm
Rb
Sx
P82B96
Tx/Rx
Tx/Rx
I2C-BUS
Cm
master bus
capacitance
Cb
buffered bus
wiring capacitance
GND (0 V)
002aab992
Effective delay of SCL at master: 270 + RmCm + 0.7RbCb ns.
C = F; R = Ω.
Figure 15. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
local master bus
buffered expansion bus
VCCM
remote slave bus
VCCB
SDA
MASTER
VCCS
Rm
Rb
Sx
P82B96
Tx/Rx
Tx/Rx
Rs
P82B96
SDA
SLAVE
Sx
I2C-BUS
I2C-BUS
Cm
Cb
master bus
capacitance
buffered bus
wiring capacitance
Cs
slave bus
capacitance
GND (0 V)
002aab993
Effective delay of SDA at master = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) ns.
C = F; R = Ω.
Figure 16. Rising edge of SDA at slave is delayed by the buffers and bus rise times
Figure 14, Figure 15, and Figure 16 show the P82B96 used to drive extended bus
2
wiring, with relatively large capacitance, linking two Fast mode I C-bus nodes. It
includes simplified expressions for making the relevant timing calculations for 3.3 V
or 5 V operation. Because the buffers and the wiring introduce timing delays, it may
be necessary to decrease the nominal SCL frequency below 400 kHz. In most cases
the actual bus frequency will be lower than the nominal Master timing due to bit-wise
stretching of the clock periods.
The delay factors involved in calculation of the allowed bus speed are:
A: The propagation delay of the master signal through the buffers and wiring to the slave.
The important delay is that of the falling edge of SCL because this edge ‘requests’ the
data or acknowledge from a slave. See Figure 14.
B: The effective stretching of the nominal LOW period of SCL at the master caused by
the buffer and bus rise times. See Figure 15.
C: The propagation delay of the slave's response signal through the buffers and wiring
back to the master. The important delay is that of a rising edge in the SDA signal. Rising
edges are always slower and are therefore delayed by a longer time than falling edges.
(The rising edges are limited by the passive pull-up while falling edges are actively
driven). See Figure 16.
2
The timing requirement in any I C-bus system is that a slave's data response (which is
provided in response to a falling edge of SCL) must be received at the master before the
end of the corresponding LOW period of SCL as appears on the bus wiring at the master.
Since all slaves will, as a minimum, satisfy the worst case timing requirements of a 400
kHz part, they must provide their response within the minimum allowed clock LOW period
of 1300 ns. Therefore in systems that introduce additional delays it is only necessary to
extend that minimum clock LOW period by any ‘effective’ delay of the slave's response.
The effective delay of the slaves response equals the total delays in SCL falling edge
from the master reaching the slave (Figure 14) minus the effective delay (stretch) of the
SCL rising edge (Figure 15) plus total delays in the slave's response data, carried on
SDA, reaching the master (Figure 16).
The master microcontroller should be programmed to produce a nominal SCL LOW
period = (1300 + A - B + C) ns, and should be programmed to produce the nominal
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle
time is not shorter than the minimum 2500 ns. If found necessary, just increase either
clock period.
Due to clock stretching, the SCL cycle time will always be longer than (600 + 1300 + A +
C) ns.
Example:
The master bus has an RmCm product of 100 ns and VCCM = 5 V.
The buffered bus has a capacitance of 1 nF and a pull-up resistor of 160 Ω to 5 V
giving an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns.
The microcontroller LOW period should be programmed to ≥ (1300 + 372.5 - 482 +
472) ns, that is ≥ 1662.5 ns.
Its HIGH period may be programmed to the minimum 600 ns.
The nominal microcontroller clock period will be ≥ (1662.5 + 600) ns = 2262.5 ns,
equivalent to a frequency of 442 kHz.
The actual bus clock period, including the 482 ns clock stretch effect, will be below
(nominal + stretch) = (2262.5 + 482) ns or ≥ 2745 ns, equivalent to an allowable
frequency of 364 kHz.
12 V
12 V
twitsted-pair telephone wires,
USB, or flat ribbon cables;
up to 15 V logic levels,
include VCC and GND
3.3 V to 5 V
Tx
Sx
SDA
Rx
3.3 V to 5 V
12 V
Ty
Sy
SCL
3.3 V 3.3 V
Ry
P82B96
P82B96
Sx
Sy
SCL/SDA
P82B96
Sx
Sy
SCL/SDA
P82B96
Sx
P82B96
Sy
Sy SDA
Sx SCL
SCL/SDA
no limit to the number of connected bus devices
002aab994
2
Figure 17. I C-bus multipoint application
002aab995
14
V
Tx
10
6
Sx
2
-2
0
400
800
1200
1600
ns
2000
Frequency = 624 kHz
Figure 18. Propagation Sx to Tx (Sx pull-up to 5 V; Tx pull-up to VCC = 10 V)
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
002aab996
14
V
Rx
10
6
Sx
2
-2
0
400
800
1200
1600
ns
2000
Ch1 frequency = 624 kHz
Figure 19. Propagation Rx to Sx (Sx pull-up to 5 V; Rx pull-up to VCC = 10 V)
10.2 Negative undershoot below absolute minimum value
The reason why the IC pin reverse voltage on pins Tx and Rx in Table 4 is specified at
such a low value, -0.3 V, is not that applying larger voltages is likely to cause damage
but that it is expected that, in normal applications, there is no reason why larger DC
voltages will be applied. This ‘absolute maximum’ specification is intended to be a DC
2
or continuous ratings and the nominal DC I C-bus voltage LOW usually does not even
reach 0 V. Inside P82B96 at every pin there is a large protective diode connected to the
GND pin and that diode will start to conduct when the pin voltage is more than about
-0.55 V with respect to GND at 25 °C ambient.
Figure 20 shows the measured characteristic for one of those diodes inside P82B96.
The plot was made using a curve tracer that applies 50 Hz mains voltage via a series
resistor, so the pulse durations are long duration (several milliseconds) and are reaching
peaks of over 2 A when more than -1.5 V is applied. The IC becomes very hot during
this testing but it was not damaged. Whenever there is current flowing in any of these
diodes it is possible that there can be faulty operation of any IC. For that reason we put a
specification on the negative voltage that is allowed to be applied. It is selected so that, at
the highest allowed junction temperature, there will be a big safety factor that guarantees
the diode will not conduct and then we do not need to make any 100 % production tests
to guarantee the published specification.
For the P82B96, in specific applications, there will always be transient overshoot and
ringing on the wiring that can cause these diodes to conduct. Therefore we designed
the IC to withstand those transients and as a part of the qualification procedure we
made tests, using DC currents to more than twice the normal bus sink currents, to be
sure that the IC was not affected by those currents. For example, the Tx/Ty and Rx/Ry
pins were tested to at least -80 mA which, from Figure 20, would be more than -0.8 V.
The correct functioning of the P82B96 is not affected even by those large currents. The
Absolute Maximum (DC) ratings are not intended to apply to transients but to steady
state conditions. This explains why you will never see any problems in practice even if,
during transients, more than -0.3 V is applied to the bus interface pins of P82B96.
Figure 20 also explains how the general Absolute Maximum DC specification was
selected. The current at 25 °C is near zero at -0.55 V. The P82B96 is allowed to operate
with +125 °C junction and that would cause this diode voltage to decrease by 100 × 2 mV
= 200 mV. So for zero current we need to specify -0.35 V and we publish -0.3 V just to
have some extra margin.
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
Remark: You should not be concerned about the transients generated on the wiring by
a P82B96 in normal applications and that is input to the Tx/Rx or Ty/Ry pins of another
P82B96. Because not all ICs that may be driven by P82B96 are designed to tolerate
negative transients, in Section 10.2.1 we show they can be managed if required.
002aaf063
0
diode current
(mA)
- 10- 1
-1
- 10
- 102
- 103
- 104
- 2.0
- 1.5
- 1.0
- 0.5
0
voltage (V)
Figure 20. Diode characteristic curve
10.2.1 Example with questions and answers
Question: On a falling edge of Tx we measure undershoot at -800 mV at the linked
Tx, Rx pins of the P82B96 that is generating the LOW, but the P82B96 data sheet
specifies minimum -0.3 V. Does this mean that we violate the data sheet absolute
value?
Answer: For P82B96 the -0.3 V Absolute Maximum rating is not intended to apply to
transients, it is a DC rating. As shown in Figure 21, there is no theoretical reason for
any undershoot at the IC that is driving the bus LOW and no significant undershoot
should be observed when using reasonable care with the ground connection of the
‘scope. It is more likely that undershoot observed at a driving P82B96 is caused
by local stray inductance and capacitance in the circuit and by the oscilloscope
connections. As shown, undershoot will be generated by PCB traces, wiring, or
2
cables driven by a P82B96 because the allowed value of the I C-bus pull-up resistor
generally is larger than that required to correctly terminate the wiring. In this example,
with no IC connected at the end of the wiring, the undershoot is about 2 V.
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
6
voltage
(V)
4
send
2
receive
0
-2
horizontal scale = 62.5 ns/div
5V
5V
5V
300 Ω
Sx
Rx
Tx
send
P82B96
time (ns)
2 meter
cable
300 Ω
receive
GND
002aaf064
Figure 21. Transients generated by the bus wiring
Question: We have 2 meters of cable in a bus that joins the Tx/Rx sides of two
P82B96 devices. When one Tx drives LOW the other P82B96 Tx/Rx is driven to -0.8
V for over 50 ns. What is the expected value and the theoretically allowed value of
undershoot?
Answer: Because the cable joining the two P82B96s is a ‘transmission line’ that
will have a characteristic impedance around 100 Ω and it will be terminated by pullup resistors that are larger than that characteristic impedance there will always be
negative undershoot generated. The duration of the undershoot is a function of the
cable length and the input impedance of the connected IC. As shown in Figure 22,
the transient undershoot will be limited, by the diodes inside P82B96, to around -0.8
V and that will not cause problems for P82B96. Those transients will not be passed
inside the IC to the Sx/Sy side of the IC.
P82B96
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19 / 32
P82B96
NXP Semiconductors
Dual bidirectional bus buffer
6
voltage
(V)
4
2
receive
send
0
-2
horizontal scale = 62.5 ns/div
5V
5V
time (ns)
5V
300 Ω
Sx
Rx
Tx
send
P82B96
2 meter
cable
5V
300 Ω
receive
Rx
Sx
Tx
GND
002aaf065
Figure 22. Wiring transients limited by the diodes in P82B96
Question: If we input 800 mV undershoot at Tx, Rx pins, what kind of problem is
expected?
Answer: When that undershoot is generated by another P82B96 and is simply the
result of the system wiring, then there will be no problems.
Question: Will we have any functional problem or reliability problem?
Answer: No.
Question: If we add 100 Ω to 200 Ω at signal line, the overshoot becomes slightly
smaller. Is this a good idea?
Answer: No, it is not necessary to add any resistance. When the logic signal
generated by Tx or Ty of P82B96 drives long traces or wiring with ICs other than
P82B96 being driven, then adding a Schottky diode (BAT54A) as shown in Figure 23
will clamp the wiring undershoot to a value that will not cause conduction of the IC’s
internal diodes.
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
6
voltage
(V)
4
2
send
0
receive
-2
horizontal scale = 62.5 ns/div
5V
5V
5V
300 Ω
Sx
Rx
Tx
send
P82B96
time (ns)
2 meter
cable
5V
300 Ω
receive
1/ BAT54A
2
Rx
Sx
Tx
GND
002aaf066
Figure 23. Wiring transients limited by a Schottky diode
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
11 Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
A2
Q
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
inches
0.010 0.057
0.069
0.004 0.049
0.05
0.244
0.039 0.028
0.041
0.228
0.016 0.024
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Figure 24. Package outline SOT96-1 (SO8)
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Figure 25. Package outline SOT505-1 (TSSOP8)
P82B96
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P82B96
NXP Semiconductors
Dual bidirectional bus buffer
12 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
12.4 Reflow soldering
Key characteristics in reflow soldering are:
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• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 26) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with Table 7
and Table 8
Table 7. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 8. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 26.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 26. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
13 Soldering of through-hole mount packages
13.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
13.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds
to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free
respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
13.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
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13.4 Package related soldering information
Table 9. Suitability of through-hole mount IC packages for dipping and wave
soldering
Package
Soldering method
Dipping
Wave
CPGA, HCPGA
-
suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL
suitable
suitable
-
not suitable
PMFP
[1]
[2]
[2]
[1]
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
For PMFP packages hot bar soldering or manual soldering is suitable.
14 Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
Charged Device Model
DDC
Display Data Channel
ESD
ElectroStatic Discharge
HBM
Human Body Model
IC
Integrated Circuit
2
I C-bus
Inter IC bus
SMBus
System Management Bus
15 Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
P82B96 v8.1
20211220
Product data sheet
-
P82B96_8
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors. Legal texts have been adapted to the new company name where
appropriate.
• Removed DIP package
• Added P82B96DPZ orderable part number
P82B96_8
20091110
Product data sheet
-
P82B96_7
P82B96_7
20090212
Product data sheet
-
P82B96_6
P82B96_6
20080131
Product data sheet
-
P82B96_5
P82B96_5
20060127
Product data sheet
-
P82B96_4
P82B96_4 (9397
750 12932)
20040329
Product data
-
P82B96_3
P82B96_3 (9397
750 11351)
20030402
Product data
853-2241 29602 of P82B96_2
2003 Feb 28
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Table 11. Revision history...continued
Document ID
Release date
Data sheet status
Change notice
P82B96_2 (9397
750 11093)
20030220
Product data
853-2241 29410 of P82B96_1
2003 Jan 22
P82B96_1 (9397
750 08122)
20010306
Product data
853-2241 25758 of 2001 Mar 06
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16 Legal information
16.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
P82B96
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use in non-automotive qualified products — Unless
this data sheet expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive
use. It is neither qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts no liability for
inclusion and/or use of non-automotive qualified products in automotive
equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
P82B96
Product data sheet
Security — Customer understands that all NXP products may be subject to
unidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the design
and operation of its applications and products throughout their lifecycles
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or
proprietary technologies supported by NXP products for use in customer’s
applications. NXP accepts no liability for any vulnerability. Customer should
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make the
ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may be
provided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.
16.4 Trademarks
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
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Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Ordering information ..........................................2
Ordering options ................................................2
Pin description ...................................................3
Limiting values .................................................. 5
Characteristics ...................................................5
Examples of bus capability ............................. 13
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
SnPb eutectic process (from J-STD-020D) ..... 25
Lead-free process (from J-STD-020D) ............ 25
Suitability of through-hole mount IC
packages for dipping and wave soldering ....... 27
Abbreviations ...................................................27
Revision history ...............................................27
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Block diagram of P82B96 ................................. 2
Pin configuration for SO8 ..................................3
Pin configuration for TSSOP8 ........................... 3
VOL as a function of junction temperature
(IOL = 0.2 mA) .................................................. 8
VOL as a function of junction temperature
(IOL = 3 mA) ..................................................... 8
VIL(max) as a function of junction
temperature ....................................................... 9
VIH(min) as a function of junction
temperature ....................................................... 9
VCC(max) that guarantees bus release
limit over temperature ....................................... 9
Interfacing an ‘I2C’ type of bus with
different logic levels .........................................10
Galvanic isolation of I2C-bus nodes via
opto-couplers ...................................................10
Long distance I2C-bus communications ..........10
Extending a DDC bus ..................................... 11
Driving ribbon or flat telephone cables ............ 12
P82B96
Product data sheet
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Falling edge of SCL at master is delayed
by the buffers and bus fall times ..................... 14
Rising edge of SCL at master is delayed
(clock stretch) by buffer and bus rise times ..... 14
Rising edge of SDA at slave is delayed by
the buffers and bus rise times .........................15
I2C-bus multipoint application ......................... 16
Propagation Sx to Tx (Sx pull-up to 5 V; Tx
pull-up to VCC = 10 V) ................................... 16
Propagation Rx to Sx (Sx pull-up to 5 V; Rx
pull-up to VCC = 10 V) ................................... 17
Diode characteristic curve ...............................18
Transients generated by the bus wiring ...........19
Wiring transients limited by the diodes in
P82B96 ............................................................20
Wiring transients limited by a Schottky
diode ................................................................21
Package outline SOT96-1 (SO8) .....................22
Package outline SOT505-1 (TSSOP8) ............23
Temperature profiles for large and small
components ..................................................... 26
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Dual bidirectional bus buffer
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
8
9
10
10.1
General description ............................................ 1
Features ............................................................... 1
Applications .........................................................1
Ordering information .......................................... 2
Ordering options ................................................ 2
Block diagram ..................................................... 2
Pinning information ............................................ 3
Pinning ............................................................... 3
Pin description ................................................... 3
Functional description ........................................3
Limiting values .................................................... 5
Characteristics .................................................... 5
Application information .................................... 10
Calculating system delays and bus clock
frequency for a Fast mode system .................. 14
10.2
Negative undershoot below absolute
minimum value ................................................ 17
10.2.1
Example with questions and answers ..............18
11
Package outline .................................................22
12
Soldering of SMD packages .............................24
12.1
Introduction to soldering .................................. 24
12.2
Wave and reflow soldering .............................. 24
12.3
Wave soldering ................................................ 24
12.4
Reflow soldering .............................................. 24
13
Soldering of through-hole mount
packages ............................................................ 26
13.1
Introduction to soldering through-hole
mount packages .............................................. 26
13.2
Soldering by dipping or by solder wave ........... 26
13.3
Manual soldering ............................................. 26
13.4
Package related soldering information .............27
14
Abbreviations .................................................... 27
15
Revision history ................................................ 27
16
Legal information .............................................. 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 December 2021
Document identifier: P82B96