PCA8574D,512

PCA8574; PCA8574A Remote 8-bit I/O expander for I2C-bus with interrupt Rev. 3 — 3 June 2013 Product data sheet 1. General description The PCA8574/74A provides general-purpose remote I/O expansion via the two-wire bidirectional I2C-bus (serial clock (SCL), serial data (SDA)). The devices consist of eight quasi-bidirectional ports, 400 kHz I2C-bus interface, three hardware address inputs and interrupt output operating between 2.3 V and 5.5 V. The quasi-bidirectional port can be independently assigned as an input to monitor interrupt status or keypads, or as an output to activate indicator devices such as LEDs. The system master can read from the input port or write to the output port through a single register. The low current consumption of 4.5 A (typical, static) is great for mobile applications and the latched output ports have 25 mA high current sink drive capability for directly driving LEDs. The PCA8574 and PCA8574A are identical, except for the different fixed portion of the slave address. The three hardware address pins allow eight of each device to be on the same I2C-bus, so there can be up to 16 of these I/O expanders PCA8574/74A together on the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs). The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic of the microcontroller and is activated when any input state differs from its corresponding input port register state. It is used to indicate to the microcontroller that an input state has changed and the device needs to be interrogated without the microcontroller continuously polling the input register via the I2C-bus. The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal pull-up 100 A current source. 2. Features and benefits  I2C-bus to parallel port expander  400 kHz I2C-bus interface (Fast-mode I2C-bus)  Operating supply voltage 2.3 V to 5.5 V with 5.5 V tolerant I/Os held to VDD with 100 A current source  8-bit remote I/O pins that default to inputs at power-up  Latched outputs with 25 mA sink capability for directly driving LEDs  Total package sink capability of 200 mA  Active LOW open-drain interrupt output  Eight programmable slave addresses using three address pins  Low standby current (4.5 A typical)  40 C to +85 C operation PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA  Packages offered: SO16, TSSOP16, SSOP20 3. Applications           LED signs and displays Servers Key pads Industrial control Medical equipment PLCs Cellular telephones Mobile devices Gaming machines Instrumentation and test measurement 4. Ordering information Table 1. Ordering information Type number PCA8574D[1] Topside mark Package PCA8574D PCA8574AD[2] PCA8574AD PCA8574PW PCA8574 PCA8574APW PA8574A PCA8574TS[3] PCA8574 PCA8574ATS[4] PA8574A Name Description Version SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 [1] PCA8574D drop-in replacement for PCF8574T/3. [2] PCA8574AD drop-in replacement for PCF8574AT/3. [3] PCA8574TS drop-in replacement for PCF8574TS/3. [4] PCA8574ATS drop-in replacement for PCF8574ATS/3. PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 2 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 4.1 Ordering options Table 2. Ordering options Type number PCA8574D PCA8574AD PCA8574PW Orderable part number Package Packing method Minimum order quantity Temperature range PCA8574D,512 SO16 Standard marking * tube dry pack 1920 Tamb = 40 C to +85 C PCA8574D,518 SO16 Reel 13” Q1/T1 *standard mark SMD dry pack 1000 Tamb = 40 C to +85 C PCA8574AD,512 SO16 Standard marking * tube dry pack 1920 Tamb = 40 C to +85 C PCA8574AD,518 SO16 Reel 13” Q1/T1 *standard mark SMD dry pack 1000 Tamb = 40 C to +85 C PCA8574PW,112 TSSOP16 Standard marking * IC’s tube - DSC bulk pack 2400 Tamb = 40 C to +85 C PCA8574PW,118 TSSOP16 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C Standard marking * IC’s tube - DSC bulk pack 2400 Tamb = 40 C to +85 C PCA8574APW,118 TSSOP16 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA8574TS,112 SSOP20 Standard marking * IC’s tube - DSC bulk pack 1350 Tamb = 40 C to +85 C PCA8574TS,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA8574ATS,112 SSOP20 Standard marking * IC’s tube - DSC bulk pack 1350 Tamb = 40 C to +85 C PCA8574ATS,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA8574APW PCA8574APW,112 TSSOP16 PCA8574TS PCA8574ATS 5. Block diagram PCA8574 PCA8574A LP FILTER INT INTERRUPT LOGIC A0 A1 A2 SCL SDA I2C-BUS CONTROL INPUT FILTER SHIFT REGISTER 8 BITS I/O PORT P0 to P7 write pulse read pulse VDD VSS POWER-ON RESET 002aac677 Fig 1. PCA8574_PCA8574A Product data sheet Block diagram All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 3 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt VDD IOH write pulse 100 µA Itrt(pu) data from Shift Register D Q FF P0 to P7 IOL CI S power-on reset VSS D Q FF CI read pulse S to interrupt logic data to Shift Register 002aah521 Fig 2. Simplified schematic diagram of P0 to P7 6. Pinning information 6.1 Pinning A0 1 16 VDD A1 2 15 SDA A2 3 14 SCL P0 4 13 INT P1 5 P2 6 11 P6 P3 7 10 P5 VSS 8 9 PCA8574D PCA8574AD 12 P7 P4 002aac678 Fig 3. Pin configuration for SO16 PCA8574_PCA8574A Product data sheet INT 1 20 P7 SCL 2 19 P6 A0 1 16 VDD n.c. 3 18 n.c. A1 2 15 SDA SDA 4 17 P5 A2 3 14 SCL VDD 5 P0 4 13 INT A0 6 P1 5 12 P7 A1 7 14 P3 P2 6 11 P6 n.c. 8 13 n.c. P3 7 10 P5 A2 9 12 P2 VSS 8 P0 10 11 P1 PCA8574PW PCA8574APW 9 P4 PCA8574TS PCA8574ATS 002aac941 002aac680 Fig 4. Pin configuration for TSSOP16 Fig 5. Pin configuration for SSOP20 All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 16 P4 15 VSS © NXP B.V. 2013. All rights reserved. 4 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 6.2 Pin description Table 3. Pin description Symbol Pin Description DIP16, SO16 SSOP20 A0 1 6 address input 0 A1 2 7 address input 1 A2 3 9 address input 2 P0 4 10 quasi-bidirectional I/O 0 P1 5 11 quasi-bidirectional I/O 1 P2 6 12 quasi-bidirectional I/O 2 P3 7 14 quasi-bidirectional I/O 3 VSS 8 15 supply ground P4 9 16 quasi-bidirectional I/O 4 P5 10 17 quasi-bidirectional I/O 5 P6 11 19 quasi-bidirectional I/O 6 P7 12 20 quasi-bidirectional I/O 7 INT 13 1 interrupt output (active LOW) SCL 14 2 serial clock line SDA 15 4 serial data line VDD 16 5 supply voltage n.c. - 3, 8, 13, 18 not connected 7. Functional description Refer to Figure 1 “Block diagram”. 7.1 Device address Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address format of the PCA8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or LOW to choose one of eight slave addresses. To conserve power, no internal pull-up resistors are incorporated on pins A2, A1, or A0 so they must be externally held HIGH or LOW. The address pins (A2, A1, A0) can connect to VDD or VSS directly or through resistors. R/W slave address 0 1 0 fixed 0 A2 A1 A0 0 0 hardware selectable 1 1 fixed 002aah469 a. PCA8574 Fig 6. PCA8574_PCA8574A Product data sheet R/W slave address 1 A2 A1 A0 0 hardware selectable 002aah470 b. PCA8574A PCA8574 and PCA8574A slave addresses All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 5 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation (write operation is shown in Figure 6). 7.1.1 Address maps The PCA8574 and PCA8574A are functionally the same, but have a different fixed portion (A6 to A3) of the slave address. This allows eight of the PCA8574 and eight of the PCA8574A to be on the same I2C-bus without address conflict. Table 4. PCA8574 address map Pin connectivity Address of PCA8574 - 40h 41h 20h 1 - 42h 43h 21h 0 - 44h 45h 22h 1 1 - 46h 47h 23h 1 0 0 - 48h 49h 24h 0 1 0 1 - 4Ah 4Bh 25h 0 1 1 0 - 4Ch 4Dh 26h 0 1 1 1 - 4Eh 4Fh 27h A0 A6 A5 A4 A3 A2 A1 A0 R/W VSS VSS VSS 0 1 0 0 0 0 0 VSS VSS VDD 0 1 0 0 0 0 VSS VDD VSS 0 1 0 0 0 1 VSS VDD VDD 0 1 0 0 0 VDD VSS VSS 0 1 0 0 VDD VSS VDD 0 1 0 VDD VDD VSS 0 1 0 VDD VDD VDD 0 1 0 PCA8574A address map Pin connectivity Product data sheet Read A1 Table 5. PCA8574_PCA8574A Write 7-bit hexadecimal address without R/W A2 Address byte value A0 Address of PCA8574A Write Read 7-bit hexadecimal address without R/W - 70h 71h 38h - 72h 73h 39h 0 - 74h 75h 3Ah 1 1 - 76h 77h 3Bh 1 0 0 - 78h 79h 3Ch 1 0 1 - 7Ah 7Bh 3Dh 1 1 1 0 - 7Ch 7Dh 3Eh 1 1 1 1 - 7Eh 7Fh 3Fh A2 A1 VSS VSS VSS 0 1 1 1 0 0 0 VSS VSS VDD 0 1 1 1 0 0 1 VSS VDD VSS 0 1 1 1 0 1 VSS VDD VDD 0 1 1 1 0 VDD VSS VSS 0 1 1 1 VDD VSS VDD 0 1 1 1 VDD VDD VSS 0 1 1 VDD VDD VDD 0 1 1 Address byte value A6 A5 A4 A3 A2 A1 A0 R/W All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 6 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 8. I/O programming 8.1 Quasi-bidirectional I/Os A quasi-bidirectional I/O is an input or output port without using a direction control register. Whenever the master reads the register, the value returned to master depends on the actual voltage or status of the pin. At power-on, all the ports are HIGH with a weak 100 A internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external signal. The I/O ports are entirely independent of each other, but each I/O octal is controlled by the same read or write data byte. Advantages of the quasi-bidirectional I/O over totem pole I/O include: • Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves die size and therefore cost. LED drive only requires an internal transistor to ground, while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O have both n-channel and p-channel transistors, which allow solid HIGH and LOW output levels without a pull-up resistor — good for logic levels. • Simpler architecture — only a single register and the I/O can be both input and output at the same time. Totem pole I/O have a direction register that specifies the port pin direction and it is always in that configuration unless the direction is explicitly changed. • Does not require a command byte. The simplicity of one register (no need for the pointer register or, technically, the command byte) is an advantage in some embedded systems where every byte counts because of memory or bandwidth limitations. There is only one register to control four possibilities of the port pin: Input HIGH, input LOW, output HIGH, or output LOW. Input HIGH: The master needs to write 1 to the register to set the port as an input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin up to VDD or drives logic 1, then the master will read the value of 1. Input LOW: The master needs to write 1 to the register to set the port to input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin down to VSS or drives logic 0, which sinks the weak 100 A current source, then the master will read the value of 0. Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or strong pull-up current when the master sets the port HIGH. The additional strong pull-up is only active during the HIGH time of the acknowledge clock cycle. This accelerator current helps the port’s 100 A current source make a faster rising edge into a heavily loaded output, but only at the start of the acknowledge clock cycle to avoid bus contention if an external signal is pulling the port LOW to VSS/driving the port with logic 0 at the same time. After the half clock cycle there is only the 100 A current source to hold the port HIGH. Output LOW: The master writes 0 to the register. There is a strong current sink transistor that holds the port pin LOW. A large current may flow into the port, which could potentially damage the part if the master writes a 0 to the register and an external source is pulling the port HIGH at the same time. PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 7 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt VDD input HIGH weak 100 µA current source (inactive when output LOW) pull-up with resistor to VDD or external drive HIGH output HIGH accelerator pull-up P port P7 - P0 pull-down with resistor to VSS or external drive LOW output LOW input LOW VSS 002aah683 Fig 7. Simple quasi-bidirectional I/O 8.2 Writing to the port (Output mode) The master (microcontroller) sends the START condition and slave address setting the last bit of the address byte to logic 0 for the write mode. The PCA8574/74A acknowledges and the master then sends the data byte for P7 to P0 to the port register. As the clock line goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by the PCA8574/74A. If a LOW is written, the strong pull-down turns on and stays on. If a HIGH is written, the strong pull-up turns on for 1⁄2 of the clock cycle, then the line is held HIGH by the weak current source. The master can then send a STOP or ReSTART condition or continue sending data. The number of data bytes that can be sent successively is not limited and the previous data is overwritten every time a data byte has been sent and acknowledged. Ensure a logic 1 is written for any port that is being used as an input to ensure the strong external pull-down is turned off. SCL 1 2 3 4 5 6 7 8 9 slave address data 1 SDA S A6 A5 A4 A3 A2 A1 A0 0 START condition R/W data 2 A P7 P6 1 P4 P3 P2 P1 P0 A P7 P6 0 P4 P3 P2 P1 P0 A P5 acknowledge from slave P5 acknowledge from slave acknowledge from slave write to port tv(Q) data output from port tv(Q) DATA 1 VALID DATA 2 VALID P5 output voltage P5 pull-up output current Itrt(pu) IOH INT trst(INT) Fig 8. 002aah623 Write mode (output) PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 8 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt Simple code WRITE mode: ... Remark: Bold type = generated by slave device. 8.3 Reading from a port (Input mode) The port must have been previously written to logic 1, which is the condition after power-on reset. To enter the Read mode the master (microcontroller) addresses the slave device and sets the last bit of the address byte to logic 1 (address byte read). The slave will acknowledge and then send the data byte to the master. The master will NACK and then send the STOP condition or ACK and read the input register again. The read of any pin being used as an output will indicate HIGH or LOW depending on the actual state of the input pin. If the data on the input port changes faster than the master can read, this data may be lost. The DATA 2 and DATA 3 are lost because these data did not meet the setup time and hold time (see Figure 9). slave address data from port SDA S A6 A5 A4 A3 A2 A1 A0 1 START condition R/W DATA 1 A data from port A acknowledge from slave DATA 4 no acknowledge from master 1 P STOP condition acknowledge from master read from port DATA 2 data at port DATA 1 DATA 3 th(D) DATA 4 tsu(D) INT tv(INT) trst(INT) trst(INT) 002aah383 A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. Fig 9. Read mode (input) Simple code for Read mode: ... Remark: Bold type = generated by slave device. PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 9 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 8.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA8574; PCA8574A in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA8574; PCA8574A registers and I2C-bus/SMBus state machine will initialize to their default states of all I/Os to inputs with weak current source to VDD. Thereafter VDD must be lowered below VPOR and back up to the operation voltage for power-on reset cycle. 8.5 Interrupt output (INT) The PCA8574/74A provides an open-drain output (INT) which can be fed to a corresponding input of the microcontroller (see Figure 10). As soon as a port input is changed, the INT will be active (LOW) and notify the microcontroller. An interrupt is generated at any rising or falling edge of the port inputs. After time tv(Q), the signal INT is valid. The interrupt will reset to HIGH when data on the port is changed to the original setting or data is read or written by the master. In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the acknowledge bit of the data byte and also on the rising edge of the write to port pulse. The interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see Figure 8). The interrupt is reset (HIGH) in the Read mode on the rising edge of the acknowledge of slave address byte and on the rising edge of the read from port pulse (see Figure 9). During the interrupt reset, any I/O change close to the read or write pulse may not generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is reset, any change in I/Os will be detected and transmitted as an INT. At power-on reset all ports are in Input mode and the initial state of the ports is HIGH, therefore, for any port pin that is pulled LOW or driven LOW by external source, the interrupt output will be active (output LOW). VDD device 1 device 2 device 16 PCA8574 PCA8574 PCA8574A INT INT INT MICROCONTROLLER INT 002aac682 Fig 10. Application of multiple PCA8574/74As with interrupt PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 10 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-wire communication between different ICs or modules. The two wires are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 11). SDA SCL data line stable; data valid change of data allowed mba607 Fig 11. Bit transfer 9.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 12). SDA SCL S P START condition STOP condition mba608 Fig 12. Definition of START and STOP conditions 9.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 13). PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 11 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 13. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Figure 14). The acknowledge bit is an active LOW level (generated by the receiving device) that indicates to the transmitter that the data transfer was successful. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that wants to issue an acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge bit related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 S START condition 8 9 clock pulse for acknowledgement 002aaa987 Fig 14. Acknowledgement on the I2C-bus PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 12 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 10. Application design-in information 10.1 Bidirectional I/O expander applications In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and P1) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the ports used as outputs (P2 to P7). If 10 A internal output HIGH is not enough current source, the port needs external pull-up resistor. During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read. The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there has been a change of data on its ports without having to communicate via the I2C-bus. VDD VDD CORE PROCESSOR VDD SDA SCL INT A0 A1 A2 P0 P1 P2 P3 P4 P5 P6 P7 temperature sensor battery status control for latch control for switch control for audio control for camera control for MP3 002aah625 Fig 15. Bidirectional I/O expander application 10.2 How to read and write to I/O expander (example) In the application example of PCA8574 shown in Figure 15, the microcontroller wants to control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes. 1. When the system power on: Core Processor needs to issue an initial command to set P0 and P1 as inputs and P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off, switch off and latch off). 2. Operation: When the temperature changes above the threshold, the temperature sensor signal will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core processor’ that there have been changes on the input pins. Read the input register. If P0 = 0 (temperature sensor has changed), then turn on LED and turn on switch. 3. Software code: //System Power on // write to PCA8574 with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs //Initial setting for PCA8574 PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 13 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt while (INT == 1); //Monitor the interrupt pin. If INT = 1 do nothing //When INT = 0 then read input ports //Read PCA8574 data If (P0 == 0) //Temperature sensor activated { // write to PCA8574 with data 0010 1011b to turn on LED (P7), on Switch (P3) and keep P[1:0] as input ports. // Write to PCA8574 } 10.3 High current-drive load applications The GPIO has a minimum guaranteed sinking current of 25 mA per bit at 4.5 V. In applications requiring additional drive, two port pins may be connected together to sink up to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins can be connected together to drive 200 mA, which is the device recommended total limit. Each pin needs its own limiting resistor as shown in Figure 16 to prevent damage to the device should all ports not be turned on at the same time. VDD VDD P0 P1 P2 P3 P4 P5 P6 P7 SDA SCL INT CORE PROCESSOR VDD A0 A1 A2 LOAD 002aah472 Fig 16. High current-drive load application 10.4 Migration path NXP offers newer, more capable drop-in replacements for the PCF8574/74A in newer space-saving packages. Table 6. Migration path Type number I2C-bus frequency Voltage range Number of addresses per device Interrupt Reset Total package sink current PCF8574/74A 100 kHz 2.5 V to 6 V 8 yes no 80 mA PCA8574/74A 400 kHz 2.3 V to 5.5 V 8 yes no 200 mA PCA9674/74A 1 MHz Fm+ 2.3 V to 5.5 V 64 yes no 200 mA PCA9670 1 MHz Fm+ 2.3 V to 5.5 V 64 no yes 200 mA PCA9672 1 MHz Fm+ 2.3 V to 5.5 V 16 yes yes 200 mA PCA9670 replaces the interrupt output of the PCA9674 with a hardware reset input to retain the maximum number of addresses. The PCA9672 replaces address A2 of the PCA9674 with a hardware reset input to retain the interrupt, but limit the number of addresses. PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 14 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 11. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD supply voltage 0.5 +6 V IDD ISS supply current - 100 mA ground supply current - 400 mA VI input voltage VSS  0.5 5.5 V II input current - 20 mA IO output current - 50 mA Ptot total power dissipation - 400 mW P/out power dissipation per output - 100 mW Tj(max) maximum junction temperature - 125 C Tstg storage temperature Tamb ambient temperature [1] [1] operating 65 +150 C 40 +85 C Total package (maximum) output current is 400 mA. 12. Thermal characteristics Table 8. PCA8574_PCA8574A Product data sheet Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient SO16 package 115 C/W TSSOP16 package 160 C/W SSOP20 package 136 C/W All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 15 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 13. Static characteristics Table 9. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 2.3 - 5.5 V IDD supply current Operating mode; no load; VI = VDD or VSS; fSCL = 400 kHz; A0, A1, A2 = static H or L - 200 500 A Istb standby current Standby mode; no load; VI = VDD or VSS; fSCL = 0 kHz - 4.5 10 A VPOR power-on reset voltage - 1.8 2.0 V [1] Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V; VDD = 2.3 V 20 35 - mA VOL = 0.4 V; VDD = 3.0 V 25 44 - mA VOL = 0.4 V; VDD = 4.5 V 30 57 - mA IL leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 5 10 pF I/Os; P0 to P7 VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.5 V; VDD = 2.3 V [2] 12 26 - mA VOL = 0.5 V; VDD = 3.0 V [2] 17 33 - mA 25 40 - mA - - 200 mA 30 138 300 A VOL = 0.5 V; VDD = 4.5 V [2] IOL(tot) total LOW-level output current VOL = 0.5 V; VDD = 4.5 V [2] IOH HIGH-level output current VOH = VSS Itrt(pu) transient boosted pull-up current VOH = VSS; see Figure 8 Ci input capacitance [3] Co output capacitance [3] 0.5 1.0 - mA - 2.1 10 pF - 2.1 10 pF 3.0 - - mA - 3 5 pF Interrupt INT (see Figure 8 and Figure 9) IOL LOW-level output current Co output capacitance VOL = 0.4 V Inputs A0, A1, A2 VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V ILI input leakage current 1 - +1 A Ci input capacitance - 3.5 5 pF [1] The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and sets all I/Os to logic 1 (with current source to VDD). [2] Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits. [3] The value is not tested, but verified on sampling basis. PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 16 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 14. Dynamic characteristics Table 10. Dynamic characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Limits are for Fast-mode I2C-bus. Symbol Parameter fSCL Conditions Min Typ Max Unit SCL clock frequency 0 - 400 kHz tBUF bus free time between a STOP and START condition 1.3 - - s tHD;STA hold time (repeated) START condition 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tSU;STO set-up time for STOP condition 0.6 - - s tHD;DAT data hold time 0 - - ns tVD;ACK data valid acknowledge time [1] 0.1 - 0.9 s tVD;DAT data valid time [2] 50 - - ns tSU;DAT data set-up time 100 - - ns tLOW LOW period of the SCL clock 1.3 - - s tHIGH HIGH period of the SCL clock - - s - 300 ns 0.6 [3][4] fall time of both SDA and SCL signals tf tr rise time of both SDA and SCL signals tSP pulse width of spikes that must be suppressed by the input filter [6] 20 + 0.1Cb [5] 20 + 0.1Cb [5] - - 300 ns - 50 ns Port timing; CL  100 pF (see Figure 8 and Figure 9) tv(Q) data output valid time - - 4 s tsu(D) data input set-up time 0 - - s th(D) data input hold time 4 - - s Interrupt timing; CL  100 pF (see Figure 8 and Figure 9) tv(INT) valid time on pin INT from port to INT - - 4 s trst(INT) reset time on pin INT from SCL to INT - - 4 s [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL’s falling edge. [4] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [5] Cb = total capacitance of one bus line in pF. [6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns. PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 17 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) acknowledge (A) STOP condition (P) 1 / fSCL 0.7 × VDD SCL 0.3 × VDD tBUF tf tr 0.7 × VDD SDA 0.3 × VDD tSU;DAT tHD;STA tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab175 Rise and fall times refer to VIL and VIH. Fig 17. I2C-bus timing diagram PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 18 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 15. Package outline SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c HE y v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.41 0.40 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT162-1 075E03 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 18. Package outline SOT162-1 (SO16) PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 19 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 19. Package outline SOT403-1 (TSSOP16) PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 20 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm D SOT266-1 E A X c y HE v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0 1.4 1.2 0.25 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 o o 0 Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-152 Fig 20. Package outline SOT266-1 (SSOP20) PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 21 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 22 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 21) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Table 11. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 12. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 21. PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 23 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 24 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 18. Soldering: PCB footprints Footprint information for reflow soldering of SO16 package SOT162-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P2 P1 1.270 Ay 1.320 11.200 By C D1 D2 6.400 2.400 0.700 Gx 0.800 10.040 Gy Hx Hy 8.600 11.900 11.450 sot162-1_fr Fig 22. PCB footprint for SOT162-1 (SO16); reflow soldering PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 25 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt Footprint information for reflow soldering of TSSOP16 package SOT403-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450 sot403-1_fr Fig 23. PCB footprint for SOT403-1 (TSSOP16); reflow soldering PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 26 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt Footprint information for reflow soldering of SSOP20 package SOT266-1 Hx Gx (0.125) P2 Hy (0.125) By Gy Ay C D2 (4x) D1 P1 solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450 sot266-1_fr Fig 24. PCB footprint for SOT266-1 (SSOP20); reflow soldering PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 27 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 19. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged-Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge FF Flip-Flop GPIO General Purpose Input/Output HBM Human Body Model I/O Input/Output I2C-bus Inter-Integrated Circuit bus IC Integrated Circuit LED Light Emitting Diode LP Low-Pass LSB Least Significant Bit MSB Most Significant Bit PLC Programmable Logic Controller POR Power-On Reset SMBus System Management Bus 20. Revision history Table 14. Revision history Document ID Release date PCA8574_PCA8574A v.3 20130603 Modifications: • • Data sheet status Change notice Supersedes Product data sheet - PCA8574_PCA8574A v.2 Section 1 “General description” re-written Section 2 “Features and benefits” – added (new) first bullet item – appended “(Fast-mode I2C-bus)” to second bullet item – added (new) third bullet item – (new) fifth bullet item changed from “50 mA sink capability” to “25 mA sink capability” – deleted (old) eighth bullet item, “Readable device ID (manufacturer, device type, and revision)” – 12th bullet item: deleted phrase “200 V MM per JESD22-A115” – 14th bullet item: deleted “DIP16” • Table 1 “Ordering information”: – deleted discontinued DIP16 package option (PCA8574N, PCA8574AN) – Topside mark for PCA8574ATS corrected from “PCA8574A” to “PA8574A” – added Table note [1], Table note [2], Table note [3] and Table note [4] • • • PCA8574_PCA8574A Product data sheet Added (new) Table 2 “Ordering options” Figure 1 “Block diagram” modified: switched positions of blocks “INTERRUPT LOGIC” and “LP FILTER” Figure 2 “Simplified schematic diagram of P0 to P7” modified: removed diode between “VDD” and “P0 to P7” signal lines All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 28 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt Table 14. Revision history …continued Document ID Modifications: (continued) Release date • Data sheet status Change notice Supersedes Section 6.1 “Pinning”: – deleted (old) Figure 3, “Pin configuration for DIP16” – pin names changed from “AD0, AD1, AD2” to “A0, A1, A2”, respectively • Section 6.2 “Pin description”: (old) Table 3, “Pin description for SO16, TSSOP16” and (old) Table 4, “Pin description for SSOP20” are merged in (new) Table 3 “Pin description” • • • • • Section 7.1 “Device address” re-written • • Section 7.1.1 “Address maps” re-written Section 8.1 “Quasi-bidirectional I/Os” re-written Section 8.2 “Writing to the port (Output mode)” re-written Figure 8 “Write mode (output)”: timing measurement symbol corrected from “td(rst)” to “trst(INT)” Section 8.3 “Reading from a port (Input mode)” re-written Figure 9 “Read mode (input)”: – timing measurement symbol corrected from “tv(D)” to “tv(INT)” – timing measurement symbol corrected from “td(rst)” to “trst(INT)” • • • Section 8.4 “Power-on reset”: second and third sentences re-written • Figure 10 “Application of multiple PCA8574/74As with interrupt” updated (changed from “device 8, PCA8574” to “device 16, PCA8574A”) • • Added (new) Section 10.2 “How to read and write to I/O expander (example)” Figure 9 “Read mode (input)” modified: corrected label from “data into port” to “data at port” Section 8.5 “Interrupt output (INT)”, fourth, fifth and sixth paragraphs re-written; added new seventh paragraph Section 10.3 “High current-drive load applications”: – 1st sentence changed from “maximum sinking current of 25 mA per bit” to “minimum guaranteed sinking current of 25 mA per bit at 4.5 V” – 4th sentence changed from “device total limit” to “device recommended total limit” • Figure 16 “High current-drive load application” modified: added resistor on P6 and P7 signal lines • • • • Added (new) Section 10.4 “Migration path” • Table 7 “Limiting values”: added Tj(max) limits Added Section 12 “Thermal characteristics” Table 9 “Static characteristics”, sub-section “I/Os; P0 to P7”: added VIL and VIH characteristics Table 10 “Dynamic characteristics”, sub-section “Interrupt timing”: – symbol/parameter corrected from “tv(D), data input valid time” to “tv(INT), valid time on pin INT” – symbol/parameter corrected from “td(rst), reset delay time” to “trst(INT), reset time on pin INT” • • • • Figure 17 “I2C-bus timing diagram” updated: added 0.3  VDD and 0.7  VDD reference lines Deleted (old) Figure 18, “Package outline SOT38-1 (DIP16)” Updated soldering information Added Section 18 “Soldering: PCB footprints” PCA8574_PCA8574A v.2 20070514 Product data sheet - PCA8574_PCA8574A v.1 PCA8574_PCA8574A v.1 20070117 Product data sheet - - PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 29 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 21.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA8574_PCA8574A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 30 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 21.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA8574_PCA8574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 June 2013 © NXP B.V. 2013. All rights reserved. 31 of 32 PCA8574; PCA8574A NXP Semiconductors Remote 8-bit I/O expander for I2C-bus with interrupt 23. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.1.1 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.1.1 9.2 9.3 10 10.1 10.2 10.3 10.4 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6 I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7 Quasi-bidirectional I/Os . . . . . . . . . . . . . . . . . . 7 Writing to the port (Output mode) . . . . . . . . . . . 8 Reading from a port (Input mode) . . . . . . . . . . 9 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 10 Characteristics of the I2C-bus . . . . . . . . . . . . 11 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 START and STOP conditions . . . . . . . . . . . . . 11 System configuration . . . . . . . . . . . . . . . . . . . 11 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application design-in information . . . . . . . . . 13 Bidirectional I/O expander applications . . . . . 13 How to read and write to I/O expander (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 High current-drive load applications . . . . . . . . 14 Migration path . . . . . . . . . . . . . . . . . . . . . . . . . 14 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal characteristics . . . . . . . . . . . . . . . . . 15 Static characteristics. . . . . . . . . . . . . . . . . . . . 16 Dynamic characteristics . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Handling information. . . . . . . . . . . . . . . . . . . . 22 Soldering of SMD packages . . . . . . . . . . . . . . 22 Introduction to soldering . . . . . . . . . . . . . . . . . 22 Wave and reflow soldering . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering: PCB footprints. . . . . . . . . . . . . . . . 25 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 21.1 21.2 21.3 21.4 22 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 31 31 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 June 2013 Document identifier: PCA8574_PCA8574A