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PCA9306DP,118

PCA9306DP,118

  • 厂商:

    NXP(恩智浦)

  • 封装:

    TSSOP-8_3X3MM

  • 描述:

    Voltage Level Translator Bidirectional 1 Circuit 2 Channel 8-TSSOP

  • 数据手册
  • 价格&库存
PCA9306DP,118 数据手册
PCA9306 2 Dual bidirectional I C-bus and SMBus voltage-level translator Rev. 9.1 — 31 August 2021 1 Product data sheet General description 2 The PCA9306 is a dual bidirectional I C-bus and SMBus voltage-level translator with an enable (EN) input, and is operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5 V (Vbias(ref)(2)). The PCA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections to be made with minimal propagation delay. When EN is HIGH, the translator switch is on, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level translation and physically isolate the capacitance to either side of the bus when both sides are connected. The PCA9306 only isolates both sides when the device is disabled and provides voltage level translation when active. The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency and the other at 100 kHz operating frequency. If the two buses are operating at different frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other bus is required. If the controller is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the translator. 2 As with the standard I C-bus system, pull-up resistors are required to provide the logic HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector 2 configuration of the I C-bus. The size of these pull-up resistors depends on the system, but each side of the translator must have a pull-up resistor. The device is designed to 2 work with Standard-mode, Fast-mode and Fast-mode Plus I C-bus devices in addition to SMBus devices. The maximum frequency is dependent on the RC time constant, but generally supports > 2 MHz. When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel. All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESD-resistant devices. PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator 2 Features and benefits 2 • 2-bit bidirectional translator for SDA and SCL lines in mixed-mode I C-bus applications 2 • Standard-mode, Fast-mode, and Fast-mode Plus I C-bus and SMBus compatible • Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and 2 Fast-mode I C-bus devices and multiple controllers • Allows voltage level translation between: – 1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2) – 1.2 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2) – 1.8 V Vref(1) and 3.3 V or 5 V Vbias(ref)(2) – 2.5 V Vref(1) and 5 V Vbias(ref)(2) – 3.3 V Vref(1) and 5 V Vbias(ref)(2) • Provides bidirectional voltage translation with no direction pin • Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion 2 • Open-drain I C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2) 2 • 5 V tolerant I C-bus I/O ports to support mixed-mode signal operation • High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW • Lock-up free operation • Flow through pinout for ease of printed-circuit board trace routing • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 • Packages offered: SO8, TSSOP8, VSSOP8, XQFN8, XSON8 3 Ordering information Table 1. Ordering information Type number Topside mark Package Name Description Version PCA9306 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCA9306DC1 P06 VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 PCA9306DC1/ [2] DG P06 VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 PCA9306DP 306P TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 306T TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 06 XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 XQFN8 plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 PCA9306D [1] PCA9306DP1 PCA9306GF [4] [5] PCA9306GM [1] P6X [6] [3] Same footprint and pinout as the Texas Instruments PA9306DCU. VSSOP8 transfers to ASEN in dark green - refer to PCN202103046A. PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 2 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator [2] [3] [4] [5] [6] PCA9306DC1/DG is functionally the same (electrically and mechanically) as the PCA9306DC1 and the Texas Instruments PCA9306DCU. It is produced in dark green (lead-free and halogen/antimony-free) package material, with a unique orderable part number for customers who desire to order and only receive dark green package material. Also known as MSOP8. Same footprint and pinout as the Texas Instruments PCA9306DCT. Device migrates to new drop-in replacement package in the future, because SOT1089 will be phased out. 'X' will change based on date code. 3.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature PCA9306D PCA9306D,118 SO8 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = -40 °C to +105 °C PCA9306DC1 PCA9306DC1,125 VSSOP8 Reel 7” Q3/T4 *standard mark 3000 Tamb = -40 °C to +105 °C VSSOP8 Reel 7” Q3/T4 *standard mark SSB 3000 Tamb = -40 °C to +105 °C [1] PCA9306DC1Z [2] PCA9306DC1/D G PCA9306DC1/ [1] DG,125 VSSOP8 Reel 7” Q3/T4 *standard mark 3000 Tamb = -40 °C to +105 °C PCA9306DP PCA9306DP,118 TSSOP8 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = -40 °C to +105 °C PCA9306DP1 PCA9306DP1,125 TSSOP8 Reel 7” Q3/T4 *standard mark 3000 Tamb = -40 °C to +105 °C PCA9306GF PCA9306GF,115 XSON8 Reel 7” Q1/T1 *standard mark SMD 5000 Tamb = -40 °C to +105 °C PCA9306GM PCA9306GM,125 XQFN8 Reel 7” Q3/T4 *standard mark 4000 Tamb = -40 °C to +105 °C [1] [2] Discontinuation notice 202108009DN - move to PCA9306DC1Z. This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses. 4 Functional diagram VREF1 VREF2 2 7 PCA9306 SCL1 SDA1 3 4 SW SW 8 6 5 EN SCL2 SDA2 1 GND 002aab844 Figure 1. Logic diagram of PCA9306 (positive logic) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 3 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator 5 Pinning information 5.1 Pinning GND 1 8 EN VREF1 2 7 VREF2 SCL1 3 6 SDA1 4 5 PCA9306DP1 GND 1 8 EN VREF1 2 7 VREF2 SCL2 SCL1 3 6 SCL2 SDA2 SDA1 4 5 SDA2 PCA9306DP 002aab842 002aac373 Figure 2. Pin configuration for TSSOP8 (DP1) Figure 3. Pin configuration for TSSOP8 (DP) (MSOP8) PCA9306DC1 PCA9306DC1/DG GND 1 8 EN VREF1 2 7 VREF2 SCL1 3 6 SCL2 SDA1 4 5 SDA2 002aab843 Figure 4. Pin configuration for VSSOP8 (DC1; DC1/DG) 1 VREF1 2 SCL1 3 SDA1 4 PCA9306D 8 EN 7 VREF2 6 SCL2 5 SDA2 002aac372 Figure 5. Pin configuration for SO8 GND 8 EN terminal 1 index area GND 1 7 VREF2 PCA9306GM VREF1 2 GND 6 SCL2 VREF1 1 8 EN 2 7 VREF2 PCA9306GF 4 3 SDA1 SCL1 5 SDA2 002aac375 SCL1 3 SDA1 4 SCL2 5 SDA2 002aaf393 Transparent top view Figure 6. Pin configuration for XQFN8 6 Transparent top view Figure 7. Pin configuration for XSON8 5.2 Pin description Table 3. Pin description Symbol Pin Description SO8, TSSOP8 (MSOP8), TSSOP8, VSSOP8 (DC1), XQFN8, XSON8 PCA9306 Product data sheet GND 1 ground (0 V) VREF1 2 low-voltage side reference supply voltage for SCL1 and SDA1 All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 4 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator Table 3. Pin description...continued Symbol Pin Description SO8, TSSOP8 (MSOP8), TSSOP8, VSSOP8 (DC1), XQFN8, XSON8 6 SCL1 3 serial clock, low-voltage side; connect to VREF1 through a pull-up resistor SDA1 4 serial data, low-voltage side; connect to VREF1 through a pull-up resistor SDA2 5 serial data, high-voltage side; connect to VREF2 through a pull-up resistor SCL2 6 serial clock, high-voltage side; connect to VREF2 through a pull-up resistor VREF2 7 high-voltage side reference supply voltage for SCL2 and SDA2 EN 8 switch enable input; connect to VREF2 and pull-up through a high resistor Functional description Refer to Figure 1. 6.1 Function table Table 4. Function selection (example) H = HIGH level; L = LOW level. [1] Input EN Function H SCL1 = SCL2; SDA1 = SDA2 L disconnect [1] 7 EN is controlled by the Vbias(ref)(2) logic levels and should be at least 1 V higher than Vref(1) for best translator operation. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Over operating free-air temperature range. Symbol Parameter Vref(1) Vbias(ref)(2) VI PCA9306 Product data sheet Conditions Min Max Unit reference voltage (1) -0.5 +6 V reference bias voltage (2) -0.5 input voltage +6 V [1] +6 V [1] -0.5 VI/O voltage on an input/output pin -0.5 +6 V Ich channel current (DC) - 128 mA IIK input clamping current - -50 mA Tstg storage temperature -65 +150 °C VI < 0 V All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 5 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator [1] 8 The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VI/O Min Max Unit voltage on an input/output pin SCL1, SDA1, SCL2, SDA2 0 5 V Vref(1) reference voltage (1) VREF1 0 5 V [1] Vbias(ref)(2) reference bias voltage (2) VREF2 0 5 V VI(EN) input voltage on pin EN 0 5 V Isw(pass) pass switch current - 64 mA Tamb ambient temperature -40 +105 °C [1] [1] 9 Conditions operating in free-air Vref(1) ≤ Vbias(ref)(2) - 1 V for best results in level shifting applications. Static characteristics Table 7. Static characteristics Tamb = -40 °C to +105 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ VIK input clamping voltage II = -18 mA; VI(EN) = 0 V - IIH HIGH-level input current VI = 5 V; VI(EN) = 0 V Ci(EN) input capacitance on pin EN Cio(off) [1] Max Unit - -1.2 V - - 5 μA VI = 3 V or 0 V - 7.1 - pF off-state input/output capacitance SCLn, SDAn; VO = 3 V or 0 V; VI(EN) = 0 V - 4 6 pF Cio(on) on-state input/output capacitance SCLn, SDAn; VO = 3 V or 0 V; VI(EN) = 3 V - 9.3 12.5 pF Ron ON-state resistance VI(EN) = 4.5 V - 2.4 5.0 Ω VI(EN) = 3 V - 3.0 6.0 Ω VI(EN) = 2.3 V - 3.8 8.0 Ω - 15 32 Ω - 32 80 Ω VI(EN) = 4.5 V - 4.8 7.5 Ω VI(EN) = 3 V - 46 80 Ω - 40 80 Ω [2] SCLn, SDAn; VI = 0 V; IO = 64 mA [3] VI(EN) = 1.5 V VI(EN) = 1.5 V [4] VI = 2.4 V; IO = 15 mA VI = 1.7 V; IO = 15 mA VI(EN) = 2.3 V [1] [2] All typical values are at Tamb = 25 °C. Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two terminals. PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 6 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator [3] [4] Guaranteed by design. For DC, DC1 (VSSOP8) and GD1 (XSON8U) packages only. 10 Dynamic characteristics Table 8. Dynamic characteristics (translating down) Tamb = -40 °C to +105 °C, unless otherwise specified. Values guaranteed by design. Symbol Parameter Conditions CL = 50 pF CL = 30 pF CL = 15 pF Min Max Min Max Min Max Unit VI(EN) = 3.3 V; VIH = 3.3 V; VIL = 0 V; VM = 1.15 V (see Figure 8) tPLH LOW to HIGH propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 2.0 0 1.2 0 0.6 ns tPHL HIGH to LOW propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 2.0 0 1.5 0 0.75 ns VI(EN) = 2.5 V; VIH = 2.5 V; VIL = 0 V; VM = 0.75 V (see Figure 8) tPLH LOW to HIGH propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 2.0 0 1.2 0 0.6 ns tPHL HIGH to LOW propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 2.5 0 1.5 0 0.75 ns Table 9. Dynamic characteristics (translating up) Tamb = -40 °C to +105 °C, unless otherwise specified. Values guaranteed by design. Symbol Parameter Conditions CL = 50 pF CL = 30 pF CL = 15 pF Min Min Max Min Max Max Unit VI(EN) = 3.3 V; VIH = 2.3 V; VIL = 0 V; VTT = 3.3 V; VM = 1.15 V; RL = 300 Ω (see Figure 8) tPLH LOW to HIGH propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 1.75 0 1.0 0 0.5 ns tPHL HIGH to LOW propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 2.75 0 1.65 0 0.8 ns VI(EN) = 2.5 V; VIH = 1.5 V; VIL = 0 V; VTT = 2.5 V; VM = 0.75 V; RL = 300 Ω (see Figure 8) tPLH LOW to HIGH propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 1.75 0 1.0 0 0.5 ns tPHL HIGH to LOW propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 3.3 0 2.0 0 1.0 ns PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 7 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator VIH VTT input VM VM VIL RL VOH S1 S2 (open) from output under test output CL VM VM 002aab845 002aab846 a. Load circuit VOL b. Timing diagram S1 = translating up; S2 = translating down. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2 ns; tf ≤ 2 ns. The outputs are measured one at a time, with one transition per measurement. Figure 8. Load circuit for outputs 11 Application information Vpu(D) = 3.3 V(1) 200 kΩ PCA9306 Vref(1) = 1.8 V(1) VREF1 RPU VCC SCL I2 C-BUS CONTROLLER SDA GND 2 8 EN 7 VREF2 RPU SCL1 SDA1 3 4 SW SW 6 5 SCL2 SDA2 1 GND RPU RPU VCC SCL I 2C-BUS DEVICE SDA GND 002aab847 1. The applied voltages at Vref(1) and Vpu(D) should be such that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation. Figure 9. Typical application circuit (switch always enabled) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 8 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator Vpu(D) = 3.3 V 3.3 V enable signal(1) on off PCA9306 Vref(1) = 1.8 V(1) VREF1 RPU VCC 2 200 k 8 EN 7 VREF2 RPU RPU RPU SCL1 SCL I2C-BUS CONTROLLER SDA SDA1 3 4 SW SW 6 VCC SCL2 5 SCL I2C-BUS DEVICE SDA SDA2 1 GND GND GND 002aab848 1. In the Enabled mode, the applied enable voltage and the applied voltage at Vref(1) should be such that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation. Figure 10. Typical application circuit (switch enable control) 11.1 Bidirectional translation For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled to HIGH side Vpu(D) through a pull-up resistor (typically 200 kΩ). This allows 2 VREF2 to regulate the EN input. A filter capacitor on VREF2 is recommended. The I Cbus controller output can be totem pole or open-drain (pull-up resistors may be required) 2 and the I C-bus device output can be totem pole or open-drain (pull-up resistors are required to pull the SCL2 and SDA2 outputs to Vpu(D)). However, if either output is totem pole, data must be unidirectional or the outputs must be 3-stateable and be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no direction control is needed. The reference supply voltage (Vref(1)) is connected to the processor core power supply voltage. When VREF2 is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V Vpu(D) power supply, and Vref(1) is set between 1.0 V and (Vpu(D) - 1 V), the output of each SCL1 and SDA1 has a maximum output voltage equal to VREF1, and the output of each SCL2 and SDA2 has a maximum output voltage equal to Vpu(D). Table 10. Application operating conditions Refer to Figure 9. PCA9306 Product data sheet Symbol Parameter Vbias(ref)(2) Conditions Min Typ reference bias voltage (2) Vref(1) + 0.6 VI(EN) input voltage on pin EN Vref(1) [1] Max Unit 2.1 5 V Vref(1) + 0.6 2.1 5 V reference voltage (1) 0 1.5 4.4 V Isw(pass) pass switch current - 14 - mA Iref reference current transistor - 5 - μA Tamb ambient temperature operating in free-air -40 - +105 °C All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 9 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator [1] All typical values are at Tamb = 25 °C. 11.2 How to size pull-up resistor value Sizing the pull-up resistor on an open-drain bus is specific to the individual application and is dependent on the following driver characteristics: • • • • The driver sink current The VOL of driver The VIL of the driver Frequency of operation The following tables can be used to estimate the pull-up resistor value in different use cases so that the minimum resistance for the pull-up resistor can be found. Table 11, Table 12 and Table 13 contain suggested minimum values of pull-up resistors for the PCA9306 and NVT20xx devices with typical voltage translation levels and drive currents. The calculated values assume that both drive currents are the same. VOL = VIL = 0.1 × VCC and accounts for a ±5 % VCC tolerance of the supplies, ±1 % resistor values. It should be noted that the resistor chosen in the final application should be equal to or larger than the values shown in Table 11, Table 12 and Table 13 to ensure that the pass voltage is less than 10 % of the VCC voltage, and the external driver should be able to sink the total current from both pull-up resistors. When selecting the minimum resistor value in Table 11, Table 12 or Table 13, the drive current strength that should be chosen should be the lowest drive current seen in the application and account for any drive strength current scaling with output voltage. For the GTL devices, the resistance table should be recalculated to account for the difference in ON resistance and bias voltage limitations between VCC(B) and VCC(A). Table 11. Pull-up resistor minimum values, 3 mA driver sink current for PCA9306 and NVT20xx A-side 1.0 V B-side 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V Rpu(A) = 750 Ω Rpu(B) = 750 Ω Rpu(A) = 845 Ω Rpu(B) = 845 Ω Rpu(A) = 976 Ω Rpu(B) = 976 Ω Rpu(A) = none Rpu(B) = 887 Ω Rpu(A) = none Rpu(B) = 1.18 kΩ Rpu(A) = none Rpu(B) = 1.82 kΩ Rpu(A) = 931 Ω Rpu(B) = 931 Ω Rpu(A) = 1.02 kΩ Rpu(B) = 1.02 kΩ Rpu(A) = none Rpu(B) = 887 Ω Rpu(A) = none Rpu(B) = 1.18 kΩ Rpu(A) = none Rpu(B) = 1.82 kΩ Rpu(A) = 1.1 kΩ Rpu(B) = 1.1 kΩ Rpu(A) = none Rpu(B) = 866 Ω Rpu(A) = none Rpu(B) = 1.18 kΩ Rpu(A) = none Rpu(B) = 1.78 kΩ Rpu(A) = 1.47 kΩ Rpu(B) = 1.47 kΩ Rpu(A) = none Rpu(B) = 1.15 kΩ Rpu(A) = none Rpu(B) = 1.78 kΩ Rpu(A) = 1.96 kΩ Rpu(B) = 1.96 kΩ Rpu(A) = none Rpu(B) = 1.78 kΩ 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V PCA9306 Product data sheet Rpu(A) = none Rpu(B) = 1.74 kΩ All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 10 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator Table 12. Pull-up resistor minimum values, 10 mA driver sink current for PCA9306 and NVT20xx A-side 1.0 V B-side 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V Rpu(A) = 221 Ω Rpu(B) = 221 Ω Rpu(A) = 255 Ω Rpu(B) = 255 Ω Rpu(A) = 287 Ω Rpu(B) = 287 Ω Rpu(A) = none Rpu(B) = 267 Ω Rpu(A) = none Rpu(B) = 357 Ω Rpu(A) = none Rpu(B) = 549 Ω Rpu(A) = 274 Ω Rpu(B) = 274 Ω Rpu(A) = 309 Ω Rpu(B) = 309 Ω Rpu(A) = none Rpu(B) = 267 Ω Rpu(A) = none Rpu(B) = 357 Ω Rpu(A) = none Rpu(B) = 549 Ω Rpu(A) = 332 Ω Rpu(B) = 332 Ω Rpu(A) = none Rpu(B) = 261 Ω Rpu(A) = none Rpu(B) = 348 Ω Rpu(A) = none Rpu(B) = 536 Ω Rpu(A) = 442 Ω Rpu(B) = 442 Ω Rpu(A) = none Rpu(B) = 348 Ω Rpu(A) = none Rpu(B) = 536 Ω Rpu(A) = 590 Ω Rpu(B) = 590 Ω Rpu(A) = none Rpu(B) = 523 Ω 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V Rpu(A) = none Rpu(B) = 523 Ω Table 13. Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx A-side 1.0 V B-side 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V Rpu(A) = 147 Ω Rpu(B) = 147 Ω Rpu(A) = 169 Ω Rpu(B) = 169 Ω Rpu(A) = 191 Ω Rpu(B) = 191 Ω Rpu(A) = none Rpu(B) = 178 Ω Rpu(A) = none Rpu(B) = 237 Ω Rpu(A) = none Rpu(B) = 365 Ω Rpu(A) = 182 Ω Rpu(B) = 182 Ω Rpu(A) = 205 Ω Rpu(B) = 205 Ω Rpu(A) = none Rpu(B) = 178 Ω Rpu(A) = none Rpu(B) = 237 Ω Rpu(A) = none Rpu(B) = 365 Ω Rpu(A) = 221 Ω Rpu(B) = 221 Ω Rpu(A) = none Rpu(B) = 174 Ω Rpu(A) = none Rpu(B) = 232 Ω Rpu(A) = none Rpu(B) = 357 Ω Rpu(A) = 294 Ω Rpu(B) = 294 Ω Rpu(A) = none Rpu(B) = 232 Ω Rpu(A) = none Rpu(B) = 357 Ω Rpu(A) = 392 Ω Rpu(B) = 392 Ω Rpu(A) = none Rpu(B) = 357 Ω 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V Rpu(A) = none Rpu(B) = 348 Ω 11.3 How to design for maximum frequency operation The maximum frequency is limited by the minimum pulse width LOW and HIGH as well as rise time and fall time. See Equation 1 as an example of the maximum frequency. The rise and fall times are shown in Figure 11. (1) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 11 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator tr(actual) VIH VIL VCC tf(actual) tHIGH(min) 0.9 × VCC tLOW(min) VOL GND 1 / fmax 0.1 × VCC 002aag912 Figure 11. An example waveform for maximum frequency The rise and fall times are dependent upon translation voltages, the drive strength, the total node capacitance (CL(tot)) and the pull-up resistors (RPU) that are present on the bus. The node capacitance is the addition of the PCB trace capacitance and the device capacitance that exists on the bus. Because of the dependency of the external components, PCB layout and the different device operating states the calculation of rise and fall times is complex and has several inflection points along the curve. The main component of the rise and fall times is the RC time constant of the bus line when the device is in its two primary operating states: when device is in the ON state and it is low-impedance, the other is when the device is OFF isolating the A-side from the Bside. A description of the fall time applied to either An or Bn output going from HIGH to LOW is as follows. Whichever side is asserted first, the B-side down must discharge to the VCC(A) voltage. The time is determined by the pull-up resistor, pull-down driver strength and the capacitance. As the level moves below the VCC(A) voltage, the channel resistance drops so that both A and B sides equal. The capacitance on both sides is connected to form the total capacitance and the pull-up resistors on both sides combine to the parallel equivalent resistance. The Ron of the device is small compared to the pull-up resistor values, so its effect on the pull-up resistance can be neglected and the fall is determined by the driver pulling the combined capacitance and pull-up resistor currents. An estimation of the actual fall time seen by the device is equal to the time it takes for the B-side to fall to the VCC(A) voltage and the time it takes for both sides to fall from the VCC(A) voltage to the VIL level. A description of the rise time applied to either An or Bn output going from LOW to HIGH is as follows. When the signal level is LOW, the Ron is at its minimum, so the A and B sides are essentially one node. They will rise together with an RC time constant that is the sum of all the capacitance from both sides and the parallel of the resistance from both sides. As the signal approaches the VCC(A) voltage, the channel resistance goes up and the waveforms separate, with the B side finishing its rise with the RC time constant of the B side. The rise to VCC(A) is essentially the same for both sides. There are some basic guidelines to follow that will help maximize the performance of the device: • Keep trace length to a minimum by placing the NVT device close to the processor. • The signal round trip time on trace should be shorter than the rise or fall time of signal to reduce reflections. • The faster the edge of the signal, the higher the chance for ringing. • The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher the frequency the device can use. The system designer must design the pull-up resistor value based on external current drive strength and limit the node capacitance (minimize the wire, stub, connector and trace length) to get the desired operation frequency result. PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 12 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator 12 Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.20 0.014 0.0075 0.19 0.16 0.15 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Figure 12. Package outline SOT96-1 (SO8) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 13 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Figure 13. Package outline SOT505-1 (TSSOP8) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 14 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 pin 1 index (A3) A1 θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Figure 14. Package outline SOT505-2 (TSSOP8) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 15 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D SOT765-1 E A X c y HE v A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 detail X 4 e L w bp 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A max. max nom min 1 A1 A2 0.15 0.85 0.00 0.60 A3 0.12 D(1) E(2) 0.27 0.23 2.1 2.4 0.17 0.08 1.9 2.2 bp c e HE 0.5 3.2 3.0 L 0.4 Lp Q 0.40 0.21 0.15 0.19 v 0.2 w 0.08 y 0.1 Z(1) θ 0.4 8° 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version SOT765-1 References IEC JEDEC JEITA sot765-1_po European projection Issue date 07-06-02 16-05-31 MO-187 Figure 15. Package outline SOT765-1 (VSSOP8) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 16 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 X D B A terminal 1 index area E A A1 detail X e v w b 4 3 C C A B C y1 C y 5 e1 terminal 1 index area 2 6 L 1 7 k 8 L2 L k metal area not for soldering L3 L1 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A 0.5 A1 b D E e e1 0.05 0.25 1.65 1.65 0.20 1.60 1.60 0.55 0.00 0.15 1.55 1.55 0.5 k 0.2 L L1 L2 L3 0.35 0.15 0.25 0.35 0.30 0.10 0.20 0.30 0.25 0.05 0.15 0.25 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT902-2 --- MO-255 --- sot902-2_po European projection Issue date 16-07-14 16-11-08 Figure 16. Package outline SOT902-2 (XQFN8) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 17 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Figure 17. Package outline SOT1089 (XSON8) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 18 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm D SOT996-2 B A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y1 C y L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A 0.5 A1 b D E 0.05 0.35 2.1 3.1 0.00 0.15 1.9 2.9 e e1 0.5 1.5 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.05 0.05 y1 0.1 sot996-2_po Outline version References IEC JEDEC JEITA European projection Issue date 07-12-21 12-11-20 SOT996-2 Figure 18. Package outline SOT996-2 (XSON8U) PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 19 / 32 NXP Semiconductors 2 PCA9306 Dual bidirectional I C-bus and SMBus voltage-level translator 13 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 13.4 Reflow soldering Key characteristics in reflow soldering are: PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 20 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and Table 15 Table 14. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 15. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 21 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14 Soldering: PCB footprints 5.50 0.60 (8×) 1.30 4.00 6.60 7.00 1.27 (6×) solder lands occupied area placement accuracy ± 0.25 Dimensions in mm sot096-1_fr Figure 20. PCB footprint for SOT96-1 (SO8); reflow soldering PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 22 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator 1.20 (2×) 0.60 (6×) enlarged solder land 0.3 (2×) 1.30 4.00 6.60 7.00 1.27 (6×) 5.50 board direction solder lands occupied area solder resist placement accurracy ± 0.25 Dimensions in mm sot096-1_fw Figure 21. PCB footprint for SOT96-1 (SO8); wave soldering 3.600 2.950 0.725 0.125 0.125 5.750 3.600 3.200 5.500 1.150 0.600 0.450 0.650 solder lands occupied area Dimensions in mm sot505-1_fr Figure 22. PCB footprint for SOT505-1 (TSSOP8); reflow soldering PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 23 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator Footprint information for reflow soldering of TSSOP8 package SOT505-2 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.700 4.400 2.700 0.850 0.400 0.500 2.800 3.600 3.600 4.650 sot505-2_fr Figure 23. PCB footprint for SOT505-2 (TSSOP8); reflow soldering PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 24 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator Footprint information for reflow soldering of VSSOP8 package SOT765-1 Hx Gx P2 Hy D1 (0.125) Gy By Ay C (0.125) (0.175) D2 (4x) P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.500 0.550 3.500 2.000 0.750 0.300 0.400 2.250 1.750 3.075 3.750 sot765-1_fr Figure 24. PCB footprint for SOT765-1 (VSSOP8); reflow soldering PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 25 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator Footprint information for reflow soldering of XSON8 package 0.15 (8×) SOT1089 0.25 (8×) 0.5 (8×) 0.7 1.4 0.6 (8×) Dimensions in mm solder paste = solder land 0.35 (3×) 1.4 solder resist occupied area sot1089_fr Figure 25. PCB footprint for SOT1089 (XSON8); reflow soldering PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 26 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator 2.400 pa + oa 2.000 0.500 0.500 0.250 0.025 0.025 4.250 3.400 pa + oa 2.000 4.000 0.900 solder lands placement area solder paste occupied area Dimensions in mm sot996-2_fr Figure 26. PCB footprint for SOT996-2 (XSON8U); reflow soldering PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 27 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator Footprint information for reflow soldering of XQFN8 package SOT902-2 1.9 0. 27 (8x) 0.45 (8x) 0.24 0. 22 (7x) 0.4 (8x) 0.29 1.9 1.75 1.37 0.65 1 1.2 0.11 0.32 0.37 0.65 1.2 1.75 occupied area solder resist solder land solder paste deposit solder land plus solder Dimensions in mm Issue date 15-06-19 15-06-23 sot902-2_fr Figure 27. PCB footprint for SOT902-2 (XQFN8); reflow soldering PCA9306 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 28 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator 15 Abbreviations Table 16. Abbreviations Acronym Description CDM Charged-Device Model ESD ElectroStatic Discharge GTL Gunning Transceiver Logic HBM Human Body Model 2 I C-bus Inter-Integrated Circuit bus I/O Input/Output LVTTL Low Voltage Transistor-Transistor Logic MIPI (Obsolete) Mobile Industry Processor Interface PLL Phase-Locked Loop PRR Pulse Repetition Rate RC Resistor-Capacitor network SMBus System Management Bus 16 Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9306 v9.1 20210831 Product data sheet PCN202103046A PCA9306 v.9 Modifications • Updated ordering information for PCA9306DC1 assembly site transfer from Hana to ASEN. – Removed these types, since they are withdrawn: PCA9306DC and PCA9306GD1. • The terms "master" and "slave" changed to "controller" and "target" to comply with NXP inclusive language policy. PCA9306 v.9 20191206 Modifications: • Updated ordering information • Removed PCA9306D,112 • Improved temperature range from "-40 °C to +85 °C" to "-40 °C to +105 °C" PCA9306 v.8 20140122 Modifications: • deleted (old) Section 11.2, "Sizing pull-up resistor" • added (new) Section 11.2 • added (new) Section 11.3 PCA9306 v.7 20130517 PCA9306 v.6 Product data sheet PCA9306 v.8 - PCA9306 v.7 Product data sheet - PCA9306 v.6 20101125 Product data sheet - PCA9306 v.5 PCA9306 v.5 20100319 Product data sheet - PCA9306 v.4 PCA9306 v.4 20091026 Product data sheet - PCA9306 v.3 PCA9306 v.3 20080804 Product data sheet - PCA9306 v.2 PCA9306 v.2 20070221 Product data sheet - PCA9306 v.1 PCA9306 v.1 20061020 Product data sheet - - PCA9306 Product data sheet Product data sheet 201912004I All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 29 / 32 NXP Semiconductors 2 PCA9306 Dual bidirectional I C-bus and SMBus voltage-level translator 17 Legal information 17.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. PCA9306 Product data sheet Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 30 / 32 PCA9306 NXP Semiconductors 2 Dual bidirectional I C-bus and SMBus voltage-level translator Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Ordering information ..........................................2 Ordering options ................................................3 Pin description ...................................................4 Function selection (example) ............................ 5 Limiting values .................................................. 5 Operating conditions ......................................... 6 Static characteristics ......................................... 6 Dynamic characteristics (translating down) ....... 7 Dynamic characteristics (translating up) ............7 Application operating conditions ........................9 Pull-up resistor minimum values, 3 mA driver sink current for PCA9306 and NVT20xx ..........................................................10 Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Pull-up resistor minimum values, 10 mA driver sink current for PCA9306 and NVT20xx ..........................................................11 Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx ..........................................................11 SnPb eutectic process (from J-STD-020D) ..... 21 Lead-free process (from J-STD-020D) ............ 21 Abbreviations ...................................................29 Revision history ...............................................29 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Fig. 16. Logic diagram of PCA9306 (positive logic) ........3 Pin configuration for TSSOP8 (DP1) .................4 Pin configuration for TSSOP8 (DP) (MSOP8) ............................................................4 Pin configuration for VSSOP8 (DC1; DC1/ DG) .................................................................... 4 Pin configuration for SO8 ..................................4 Pin configuration for XQFN8 ............................. 4 Pin configuration for XSON8 ............................. 4 Load circuit for outputs ..................................... 8 Typical application circuit (switch always enabled) .............................................................8 Typical application circuit (switch enable control) ...............................................................9 An example waveform for maximum frequency .........................................................12 Package outline SOT96-1 (SO8) .....................13 Package outline SOT505-1 (TSSOP8) ............14 Package outline SOT505-2 (TSSOP8) ............15 Package outline SOT765-1 (VSSOP8) ............16 Package outline SOT902-2 (XQFN8) .............. 17 PCA9306 Product data sheet Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Fig. 26. Fig. 27. Package outline SOT1089 (XSON8) ............... 18 Package outline SOT996-2 (XSON8U) ........... 19 Temperature profiles for large and small components ..................................................... 22 PCB footprint for SOT96-1 (SO8); reflow soldering .......................................................... 22 PCB footprint for SOT96-1 (SO8); wave soldering .......................................................... 23 PCB footprint for SOT505-1 (TSSOP8); reflow soldering ............................................... 23 PCB footprint for SOT505-2 (TSSOP8); reflow soldering ............................................... 24 PCB footprint for SOT765-1 (VSSOP8); reflow soldering ............................................... 25 PCB footprint for SOT1089 (XSON8); reflow soldering ............................................... 26 PCB footprint for SOT996-2 (XSON8U); reflow soldering ............................................... 27 PCB footprint for SOT902-2 (XQFN8); reflow soldering ............................................... 28 All information provided in this document is subject to legal disclaimers. Rev. 9.1 — 31 August 2021 © NXP B.V. 2021. All rights reserved. 31 / 32 NXP Semiconductors 2 PCA9306 Dual bidirectional I C-bus and SMBus voltage-level translator Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 7 8 9 10 11 11.1 11.2 11.3 12 13 13.1 13.2 13.3 13.4 14 15 16 17 General description ............................................ 1 Features and benefits .........................................2 Ordering information .......................................... 2 Ordering options ................................................ 3 Functional diagram ............................................. 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 4 Functional description ........................................5 Function table .................................................... 5 Limiting values .................................................... 5 Recommended operating conditions ................ 6 Static characteristics .......................................... 6 Dynamic characteristics .....................................7 Application information ......................................8 Bidirectional translation ......................................9 How to size pull-up resistor value ....................10 How to design for maximum frequency operation .......................................................... 11 Package outline .................................................13 Soldering of SMD packages .............................20 Introduction to soldering .................................. 20 Wave and reflow soldering .............................. 20 Wave soldering ................................................ 20 Reflow soldering .............................................. 20 Soldering: PCB footprints ................................ 22 Abbreviations .................................................... 29 Revision history ................................................ 29 Legal information .............................................. 30 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 31 August 2021 Document identifier: PCA9306
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