PCA9521
Fast dual bidirectional bus buffer
Rev. 2 — 19 March 2013
Product data sheet
1. General description
The PCA9521 is a monolithic bipolar integrated circuit for bus buffering in applications
including I2C-bus, SMBus, PMBus, and other systems based on similar principles.
The buffer extends the bus load limit by buffering both the SCL and SDA lines. It supports
up to 400 pF loads on each side of the buffer at 400 kHz. Higher capacitance is supported
at lower speeds, and lower capacitance at higher speeds up to 1 MHz.
The enable function allows sections of the bus to be isolated. Individual parts of the
system can be brought on-line successively. This means a controlled start-up using a
diverse range of components, operating speeds and loads is easily achieved. Systems
employing removable components on a back-plane (for example, telecommunications
racks) can use the enable pin and the high-impedance ports on power-down to safely
install and remove components in active systems.
Bus level translation between a very wide range of bus voltages, from 1.8 V to 10 V, is
supported. This feature provides enormous flexibility in interfacing systems of different
technologies.
The unique operation of the PCA9521 provides one of the fastest response times of such
bidirectional buffers, ensuring any glitches (common to other buffers) are kept well within
the 50 ns I2C-bus specification. Additionally, it does this without the need for ‘rise-time
accelerators’ which, combined with low noise margins, may cause glitches outside of the
I2C-bus specification.
2. Features and benefits
Dual, bidirectional unity gain buffer
Fast switching times allow operation in excess of 1 MHz
Supports I2C-bus (Standard-mode and Fast-mode), SMBus (standard and high power
mode), PMBus and IPMB
Enable allows bus segments to be disconnected
Low standby current when not enabled
Application/removal of power to IC will not interfere with other bus activity
6 mA (static) pull-down capability supports a wide range of bus standards
Low noise susceptibility
Low input-output offset voltage
Threshold and offset parameters allow the connection of several devices in series
Bus levels independent of supply voltage
Operating voltages from 2.7 V to 5.5 V
Wide range of bus voltages from 1.8 V to 10 V
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
Level shifting between different bus voltages
Achieves superior response times without the need for rise time accelerators
ESD protection exceeds 2 kV HBM per JESD22-A114 and 500 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
3. Applications
Power management systems
Telecommunications systems including ATCA
Desktop and portable computers including RAID
Building automation
TV/projector/monitor interconnection
Game consoles/boxes
CompactPCI
Medical systems
Gaming machine networks
Backplane management/interconnect
4. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCA9521D
PCA9521
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
PCA9521DP
9521
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature range
PCA9521D
PCA9521D,118
SO8
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9521DP
PCA9521DP,118
TSSOP8
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9521
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
2 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
5. Block diagram
1.8 V to 10 V
1.8 V to 10 V
R1
2.7 V to 5.5 V
R2
1.8 V to 10 V
1.8 V to 10 V
R3
VCC
R4
8
EN 1
enable
(up to 10 V)
SCL
SDA
PCA9521
SA1 2
3 SA2
SB1 7
6 SB2
SCL
SDA
4
GND
002aaf280
Fig 1.
Block diagram
6. Pinning information
6.1 Pinning
EN
1
8
VCC
SA1
2
7
SB1
SA2
3
6
GND
4
5
EN
1
8
VCC
SA1
2
7
SB1
SB2
SA2
3
6
SB2
n.c.
GND
4
5
n.c.
PCA9521D
002aaf279
002aaf278
Fig 2.
Pin configuration for SO8
PCA9521DP
Fig 3.
Pin configuration for TSSOP8
6.2 Pin description
Table 3.
Symbol
Pin
Description
EN
1
enable
SA1
2
buffer A, port 1 (SCL output[1])
SA2
3
buffer A, port 2 (SCL input[1])
GND
4
supply ground
n.c.
5
not connected
SB2
6
buffer B, port 2 (SDA input[1])
SB1
7
buffer B, port 1 (SDA output[1])
VCC
8
positive supply
[1]
PCA9521
Product data sheet
Pin description
Recommended I2C-bus orientation for device family compatibility.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
3 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
7. Functional description
Refer to Figure 1 “Block diagram”.
7.1 VCC, GND — supply pins
The power supply voltage for the PCA9521 may be any voltage in the range 2.7 V to
5.5 V. The threshold level below which the output will begin to match the input is 33 % of
VCC. Hence, the operating voltage should be chosen with the required bus voltage,
switching threshold, and noise margins, in mind.
7.2 SA1, SA2, SB1, SB2 — buffer inputs/outputs
The two buffers (SA and SB) are identical and symmetrical. The buffers can be driven
from either direction, with the same response. When port 1 of the buffer is being driven
LOW (< 0.3VCC) by another device on the bus, port 2 will be driven LOW by the IC to
provide the buffered output.
The ‘input’ side is determined by the lowest externally driven signal. Therefore if port 1 is
externally pulled to VSx1 = 250 mV, and port 2 is externally pulled to VSx2 = 500 mV, the
buffer will pull port 2 down further such that it becomes VSx2 = VSx1 + Voffset. Should port 2
subsequently become lower than port 1 by the amount of the offset voltage
(VSx2 + Voffset < VSx1) by means of an external device pulling it LOW, control of the
buffering operation will switch, and port 2 will become the ‘input’. The voltage at port 1 will
then become VSx1 = VSx2 + Voffset. When both ports are being held almost equal (less than
an offset voltage) the external devices are effectively in control.
7.3 EN — enable; activate buffer operations
The enable input, EN, is used to disable the buffer, for the purpose of isolating sections of
the bus. The IC should only be disabled when the bus is idle. This prevents truncation of
commands which may confuse other devices on the bus.
Enable may also be used to progressively activate sections of the bus during system
start-up. Bus sections slow to respond on power-up can be kept isolated from the main
system to avoid interference and collisions.
The EN pin may be pulled up higher than the VCC of the buffer, further enhancing the
capability of the PCA9521 in a level shifting role. For example, a microprocessor could
drive EN, SA1 and SB1 at 5 V, while the buffer VCC, SA2 and SB2 ports are at 3.3 V.
Similarly, the threshold level of the EN pin allows a 1.8 V device to disable a PCA9521
with a VCC of 3.3 V.
The EN pin includes an internal 2 A pull-down current, which will act to disable the
device should the pin be left floating.
PCA9521
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
4 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Min
Max
Unit
supply voltage
[1]
0.3
+7
V
Vn
voltage on any other pin
[1]
0.3
+12
V
VI(EN)
input voltage on pin EN
[1]
0.3
+12
V
IIO
input/output current
-
20
mA
Ptot
total power dissipation
-
300
mW
Tstg
storage temperature
55
+125
C
Tamb
ambient temperature
40
+85
C
VCC
[1]
Parameter
Conditions
SA1, SA2, SB1, SB2
any pin
operating
Voltages are specified with respect to pin 4 (GND).
9. Characteristics
Table 5.
Characteristics
Tamb = 40 C to +85 C; voltages are specified with respect to ground (GND).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Power supply
VCC
supply voltage
operating
2.7
-
5.5
V
ICC
supply current
operating; VCC = VI(EN) = 5.5 V
-
6
-
mA
standby; VCC = 5.5 V; VI(EN) = 0 V
-
670
900
A
Buffer ports (SA1, SA2, SB1, SB2)
Vbus
bus voltage
1.8
-
10
V
Vth(IL)
LOW-level input threshold
voltage
-
-
0.3VCC
V
Vth(IH)
HIGH-level input threshold
voltage
0.41VCC
-
-
V
IIL
LOW-level input current
drive current; Vbus < VCC
-
6
20
A
IO(sink)
output sink current
LOW-level; Vbus(out) = 0.4 V
6
-
-
mA
Voffset
offset voltage
input/output; VCC = 5 V
IOL = 5 mA; Vbus(in) = 50 mV
-
230
300
mV
IOL = 500 A; Vbus(in) = 50 mV
-
90
125
mV
IOL = 1.2 mA; Vbus(in) = 200 mV
IL
leakage current
Cio
input/output capacitance
Vbus VCC
[1]
-
90
125
mV
-
-
5
A
-
-
10
pF
Enable (EN)
Ven
enable voltage
active
1.3
-
-
V
Vdis
disable voltage
standby
-
-
0.7
V
II
input current
Ven > 1.2 V
0.7
-
5
A
PCA9521
Product data sheet
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Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
5 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
Table 5.
Characteristics …continued
Tamb = 40 C to +85 C; voltages are specified with respect to ground (GND).
Symbol
Timing
Parameter
Conditions
Min
Typ
Max
Unit
characteristics[1]
td
delay time
VCC = 5 V; Vbus = 5 V; Rpu(bus) = 1 k;
CL(ext) = 120 pF; Figure 4
-
45
-
ns
tf
fall time
VCC = 5 V; Vbus = 5 V; Rpu(bus) = 1 k;
CL(ext) = 120 pF; Figure 4
-
40
-
ns
foper(I2C)
I2C operating frequency
0
-
1000
kHz
td(en-act)
enable to active delay time
EN HIGH to Sxx active
-
1.5
-
s
td(dis-stb)
disable to standby delay time
EN LOW to Sxx disabled
-
0.4
-
s
[1]
Guaranteed by design (not subject to test).
Vbus
70 % VSx2
VSx2
VCC = Vpu = 5 V
75
VSx1
33 %
VCC
002aaf325
125
Voffset
(mV)
100
30 % VSx2
50
Sx2
td
25
Sx1
tf
0
time
0
2
4
6
002aaf281
8
10
RPU (kΩ)
Tamb = 25 C; Vbus(in) = 200 mV.
Fig 4.
Timing parameters
002aaf283
9.2
Offset voltage, VO VI
Fig 5.
002aaf284
15
IOL
(mA)
ICC
(mA)
14
8.4
VCC = 5.0 V
3.3 V
13
7.6
12
6.8
−50
0
50
11
−50
100
150
Tamb (°C)
0
50
100
150
Tamb (°C)
Vbus(out) = 500 mV; VCC = 2.7 V.
Fig 6.
Supply current versus ambient temperature
PCA9521
Product data sheet
Fig 7.
LOW-level output current versus
ambient temperature
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
6 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
002aaf285
4.5
002aaf286
4.5
voltage
(V)
voltage
(V)
3.5
3.5
(2)
(2)
2.5
2.5
(1)
(1)
1.5
1.5
0.5
0.5
−0.5
−0.5
horizontal scale = 40 ns/div
horizontal scale = 40 ns/div
time (ns)
time (ns)
(1) Input 33 pF
(1) Input 33 pF
(2) Output 120 pF
(2) Output 120 pF
Fig 8.
Rise time (4 mA pull-up)
PCA9521
Product data sheet
Fig 9.
Fall time (4 mA pull-up)
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Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
7 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
10. Application information
10.1 Design considerations
Figure 10 shows the PCA9521 level shifting signals from 1.8 V to 3.3 V at 1 MHz clock
speed. The PCA9521 has excellent application to extending loads and providing
interfaces to connectors on high-speed microprocessor cards, well in excess of the
Fast-mode 400 kHz I2C-bus specification. Rise times are determined simply by the side of
the buffer with the slowest RC time constant.
002aaf287
4.5
voltage
(V)
3.5
(1)
2.5
(2)
1.5
0.5
−0.5
horizontal scale = 200 ns/div
time (ns)
(1) Input 33 pF
(2) Output 120 pF
Fig 10. 1.8 V to 3.3 V level shifting at 1 MHz
Figure 11 shows a typical application for the PCA9521. The IC can level shift between
different bus voltages without the need for external components. Higher bus voltages and
currents outside the range of the Standard-mode I2C-bus specification can be catered for,
providing a longer range capability and higher noise immunity.
The enable pin (EN) can be used to interface buses of different operating frequencies.
When certain bus sections are enabled, the system frequency may be limited by a bus
section having a slave device specified only to 100 kHz. When that bus section is
disabled, the slow slave is isolated and the remaining bus can be run at 400 kHz. The
timing performance and current sinking capability will allow the PCA9521 to run well in
excess of the 400 kHz maximum limit of the Fast-mode I2C-bus.
PCA9521
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
8 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
1.8 V
3.3 V
R1
600 Ω
VCC
C1
0.01 μF
R2
600 Ω
SCL
SA1
SDA
SB1
BUS MASTER
400 kHz
10 V
VCC
5V
10 V
R3
3.9 kΩ
R4
3.9 kΩ
C2
0.01 μF
R5
1.1 kΩ
SA2
SA1
SB2
SB1
VCC
R6
1.1 kΩ
SA2
SCL
SB2
SDA
EN
backplane
or cable run
U2
VCC
SLAVE
100 kHz
PCA9521
PCA9521
U1
3.3 V
EN
U3
U4
002aaf288
Fig 11. PCA9521 typical buffer application
Figure 12 shows the PCA9521 used in a radial (star) configuration on an AdvancedTCA
Shelf Management Controller board (ShMC). The PCA9521 is highly suited to this and
other backplane applications, providing excellent noise margins and I2C-bus compliant
switching levels.
fully bused compliant plug-in
(hot-insert) ShMC module (e.g., AMC)
enables
R
R
VI
R
RRA
VOL = VI + 0.08 V
µP
I2C-bus
to ShMC #2
total 12 FET switches (4 / pkg.),
giving 24 bus outputs
R
PCA9522
FET
switches
PCA9521
Rd
alternate
implementations
R
Rd
(1)
PCA9522
µP
BACKPLANE
FRU with switching levels compliant
with the I2C-bus standard
PCA9521
12 × PCA9521
isolating
bus buffers
Rd
µP
required VIL = 0.3VCC (max.) = 0.99 V
Vmax = 0.5 V
(PICMG3.0)
example of existing FRUs
built to PICMG3.0 R2.0
PCA9521
enables
R
Rd
R
PCA9521
BUFFER
WITH RTA
FET
switches
ShMC1
to ShMC #2
IPMB (× 24)
ShMC2
µP
required VIL = 0.6 V (typ.)
etc.
002aaf289
The system shown here uses FET switches, however a valid alternative is to simply use 24 PCA9521’s without FET switches.
Long track runs on the ShMC board and backplane can sometimes result in high frequency tuned circuits on either side of the
PCA9521. If your layout is prone to forming such tuned circuits, it is perfectly acceptable to use a ‘traditional’ damping resistor
(Rd) across the PCA9521.
(1) RRA = Rise Rate Accelerator.
Fig 12. AdvancedTCA style backplane application using PCA9521 in a radial Shelf Manager configuration
PCA9521
Product data sheet
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Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
9 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
Peripheral cards (or FRU (Field Replaceable Units)) and backplanes operating at a range
of voltages can be interfaced together using a minimum of components. The PCA9521
can be teamed with the PCA9522 to achieve substantial noise margin gains across a
system.
Multiplexers such as the PCA9544A are simple analog switches which provide no
capacitive load isolation between connected branches. Figure 14 shows the PCA9521
enhancing an I2C-bus multiplexer application, by isolating the load capacitance of each
branch. Figure 15 and Figure 16 show alternate forms of bus multiplexing.
Similarly, the P82B715 I2C-bus extender, which is commonly used for line driver
applications, provides a ‘10 impedance transformation’ but does not isolate either side of
the buffer. Figure 13 shows the PCA9521 used to isolate the bus loading due to the
P82B715. This greatly simplifies calculation of the pull-ups, increases the total system
loading capability in extender applications, will meet the Fast-mode release requirement
(when PCA9521 and P82B715 VCC’s share a common supply), and ensures the 300 ns
rise time requirement can easily be met even if the cable bus rise is relatively slow.
Buffers are intended to extend total system capacitance above 400 pF, so anticipate high
capacitance on each side. When loading on one side is small, adding 47 pF is suggested
to avoid any waveform ripple, should it occur.
3.3 V
R1
1.1 kΩ
5V
R2
1.1 kΩ
R3
SCL
SA1
SDA
SB1
isolated
I2C-bus
VCC
SA2
no pull-up
required
SB2
Sx
VCC
Sy
PCA9521
R4
Lx
Ly
P82B715
long
cable run
EN
U1
U2
002aaf290
PCA9521 provides bus isolation and simplifies calculation of bus RC components.
Fig 13. PCA9521 isolating the Standard-mode I2C-bus from a P82B715 used as a
line driver
PCA9521
Product data sheet
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Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
10 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
5V
R1
1.5 kΩ
VCC
3.3 V
R2
1.5 kΩ
R3
1.1 kΩ
SCL
SA1
SDA
SB1
VCC
R4
1.1 kΩ
SA2
SCL
SB2
SDA
VDD
SD0
SC1
PCA9521
BUS MASTER
INT[3:0]
EN
U1
SC0
SD1
SC2
U2
A0
SD2
A1
SC3
A2
SD3
Using the PCA9521,
up to 400 pF may be
connected to each
and every bus 0
through bus 3.
PCA9544A
U3
002aaf291
Alternately, using the PCA9546A (which allows multiple outputs to be selected) you would simply
place a PCA9521 on each output on the right-hand side, rather than a single PCA9521 on the
left-hand side
Fig 14. PCA9521 multiplexer isolation application
5V
R1
1.5 kΩ
R2
1.5 kΩ
SCL
SA1
SDA
SB1
VCC
SA2
SB2
PCA9521
A
B
C
VCC
74LS137
3-to-8
demultiplexer
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U1
EN
U2
multiple isolated buses with
400 pF load capacitance each
5V
SA1
SB1
VCC
SA2
SB2
PCA9521
EN
U3
002aaf292
Fig 15. PCA9521 bus multiplexer application driven from a simple logic device
PCA9521
Product data sheet
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Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
11 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
3.3 V
R1
1.1 kΩ
R2
1.1 kΩ
SCL
SA1
SDA
SB1
VCC
SA2
SB2
PCA9521
VDD
SCL
SDA
IO0
IO1
IO2
IO3
PCA9536
I2C-BUS
I/O EXPANDER
EN
U2
multiple isolated buses with
400 pF load capacitance each
3.3 V
SA1
VCC
SB1
SA2
SB2
PCA9521
U1
EN
U3
002aaf293
Fig 16. PCA9521 bus multiplexer application driven from an I2C-bus I/O expander
10.2 Input to output offset voltage calculation
The offset voltage between the side acting as the output (Sxx(out)) and the side acting as
the input (Sxx(in)) of the PCA9521 can be calculated using the relationship given in
Equation 1:
V BUS
V offset = V i + 50 mV + ------------ 11
R
(1)
This calculation is valid for Vbus(in) 200 mV, as below this point the saturation voltage of
the open-collector output drive transistor will begin to affect the characteristic. Input and
output voltages are shown in millivolts, VBUS (the supply voltage to the bus) is in volts, and
R is in ohms.
An example calculation for VBUS = 3.3 V, VSA1 = 200 mV, the resistance R pulling up SA2
is 2 k, then the voltage on SA2 is typically:
3.3
V SA2 = 200 mV + 50 mV + ------------ 11 = 268 mV
2000
(2)
This can be compared with the offset characteristic shown in Figure 5.
PCA9521
Product data sheet
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Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
12 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
11. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 17. Package outline SOT96-1 (SO8)
PCA9521
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
13 of 23
PCA9521
NXP Semiconductors
Fast dual bidirectional bus buffer
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
detail X
e
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Fig 18. Package outline SOT505-1 (TSSOP8)
PCA9521
Product data sheet
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12. Handling information
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
PCA9521
Product data sheet
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
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PCA9521
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Fast dual bidirectional bus buffer
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 6 and 7
Table 6.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 7.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
PCA9521
Product data sheet
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Rev. 2 — 19 March 2013
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PCA9521
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Fast dual bidirectional bus buffer
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Soldering: PCB footprints
5.50
0.60 (8×)
1.30
4.00
6.60
7.00
1.27 (6×)
solder lands
occupied area
placement accuracy ± 0.25
Dimensions in mm
sot096-1_fr
Fig 20. PCB footprint for SOT96-1 (SO8); reflow soldering
PCA9521
Product data sheet
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Rev. 2 — 19 March 2013
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PCA9521
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Fast dual bidirectional bus buffer
1.20 (2×)
0.60 (6×)
enlarged solder land
0.3 (2×)
1.30
4.00
6.60
7.00
1.27 (6×)
5.50
board direction
solder lands
occupied area
solder resist
placement accurracy ± 0.25
Dimensions in mm
sot096-1_fw
Fig 21. PCB footprint for SOT96-1 (SO8); wave soldering
3.600
2.950
0.125
0.725
0.125
5.750
3.200
3.600
5.500
1.150
0.600
0.450
0.650
solder lands
occupied area
Dimensions in mm
sot505-1_fr
Fig 22. PCB footprint for SOT505-1 (TSSOP8); reflow soldering
PCA9521
Product data sheet
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15. Abbreviations
Table 8.
PCA9521
Product data sheet
Abbreviations
Acronym
Description
ATCA
Advanced Telecommunications Computing Architecture
CDM
Charged-Device Model
cPCI
compact Peripheral Component Interconnect
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
IC
Integrated Circuit
IPMB
Intelligent Platform Management Bus
PICMG
PCI Industrial Computer Manufacturers Group
PMBus
Power Management Bus
RAID
Redundant Array of Independent Discs
SMBus
System Management Bus
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
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Fast dual bidirectional bus buffer
16. Revision history
Table 9.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9521 v.2
20130319
Product data sheet
-
PCA9521 v.1
Modifications:
•
•
Added Section 4.1 “Ordering options”
Table 5 “Characteristics”, sub-section “Power supply”:
– ICC Typ value (operating) changed from “9 mA” to “6 mA”
– ICC Typ value (standby) changed from “295 A” to “670 A”
– ICC Max value (standby) changed from “350 A” to “900 A”
•
Table 5 “Characteristics”, sub-section “Buffer ports (SA1, SA2, SB1, SB2)”:
– VSxx Min value changed from “-” to “1.8 V”
– IIL Typ value changed from “12 A” to “6 A”
– IIL Max value changed from “30 A” to “20 A”
– Voffset Condition changed from “VCC = 3.3 V” to “VCC = 5 V”
– Voffset (sub) Condition changed from “IOL = 4 mA” to “IOL = 5 mA”
– Voffset (Condition IOL = 5 mA): Typ value changed from “165 mV” to “230 mV”;
Max value changed from “200 mV” to “300 mV”
– Voffset (Condition IOL = 500 A): Typ value changed from “55 mV” to “90 mV”;
Max value changed from “100 mV” to “125 mV”
– Voffset (Condition IOL = 1.2 mA): Typ value changed from “60 mV” to “90 mV”;
Max value changed from “100 mV” to “125 mV”
•
Table 5 “Characteristics”, sub-section “Enable (EN)”:
– Ven Min value changed from “1.2 V” to “1.3 V”
– II Min value changed from “1” to “0.7 A”
•
Table 5 “Characteristics”, sub-section “Timing characteristics”:
– td Typ value changed from “30 ns” to “45 ns”
– tf Typ value changed from “15 ns” to “40 ns”
– td(en-act) Typ value changed from “1 s” to “1.5 s”
– td(dis-stb) Typ value changed from “1.1 s” to “0.4 s”
– foper(I2C) Max value changed from “400 kHz” to “1000 kHz”
– deleted foper(max) characteristic
•
PCA9521 v.1
PCA9521
Product data sheet
Added Section 14 “Soldering: PCB footprints”
20110822
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
-
© NXP B.V. 2013. All rights reserved.
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17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9521
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
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Fast dual bidirectional bus buffer
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9521
Product data sheet
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PCA9521
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19. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
8
9
10
10.1
10.2
11
12
13
13.1
13.2
13.3
13.4
14
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
VCC, GND — supply pins . . . . . . . . . . . . . . . . . 4
SA1, SA2, SB1, SB2 — buffer inputs/outputs . 4
EN — enable; activate buffer operations . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Application information. . . . . . . . . . . . . . . . . . . 8
Design considerations . . . . . . . . . . . . . . . . . . . 8
Input to output offset voltage calculation . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Handling information. . . . . . . . . . . . . . . . . . . . 15
Soldering of SMD packages . . . . . . . . . . . . . . 15
Introduction to soldering . . . . . . . . . . . . . . . . . 15
Wave and reflow soldering . . . . . . . . . . . . . . . 15
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
Soldering: PCB footprints. . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 March 2013
Document identifier: PCA9521
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