PCA9536D,118

PCA9536 4-bit I2C-bus and SMBus I/O port Rev. 6 — 7 November 2017 Product data sheet 1. General description The PCA9536 is an 8-pin CMOS device that provides 4 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9536 consists of a 4-bit Configuration register (input or output selection), 4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The power-on reset sets the registers to their default values and initializes the device state machine. The I2C-bus address is fixed and allows only one device on the same I2C-bus/SMBus. 2. Features and benefits            4-bit I2C-bus GPIO Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity Inversion register Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 4 I/O pins which default to 4 inputs with 100 k internal pull-up resistor 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  Packages offered: SO8, TSSOP8 (MSOP8), HVSON8 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 3. Ordering information Table 1. Ordering information Tamb = 40 C to +85 C Type number Topside mark Package Name Description Version PCA9536D PCA9536 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCA9536DP 9536 TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 PCA9536TK 9536 HVSON8 SOT908-1 [1] plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3  3  0.85 mm Also known as MSOP8. 3.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature PCA9536D PCA9536D,112 SO8 STANDARD MARKING * IC'S TUBE - DSC BULK PACK 2000 Tamb = 40 C to +85 C PCA9536D,118 SO8 REEL 13" Q1/T1 2500 *STANDARD MARK SMD Tamb = 40 C to +85 C PCA9536DP PCA9536DP,118 TSSOP8[1] REEL 13" Q1/T1 2500 *STANDARD MARK SMD Tamb = 40 C to +85 C PCA9536TK PCA9536TK,118 HVSON8 REEL 13" Q1/T1 6000 *STANDARD MARK SMD Tamb = 40 C to +85 C PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 2 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 4. Block diagram PCA9536 SCL SDA INPUT FILTER IO0 4-bit I2C-BUS/SMBus CONTROL write pulse VDD INPUT/ OUTPUT PORTS read pulse IO1 IO2 IO3 POWER-ON RESET VSS 002aab851 All I/Os are set to inputs at reset. Fig 1. PCA9536 Product data sheet Block diagram of PCA9536 All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 3 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 5. Pinning information 5.1 Pinning IO0 1 8 VDD IO1 2 7 SDA IO2 3 6 VSS 4 5 IO0 1 8 VDD IO1 2 7 SDA SCL IO2 3 6 SCL IO3 VSS 4 5 IO3 PCA9536D PCA9536DP 002aab850 002aab849 Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8 terminal 1 index area IO0 1 IO1 2 8 VDD 7 SDA PCA9536TK IO2 3 6 SCL VSS 4 5 IO3 002aac459 Transparent top view Fig 4. Pin configuration for HVSON8 5.2 Pin description Table 3. PCA9536 Product data sheet Pin description Symbol Pin Description IO0 1 input/output 0 IO1 2 input/output 1 IO2 3 input/output 2 VSS 4 supply ground IO3 5 input/output 3 SCL 6 serial clock line SDA 7 serial data line VDD 8 supply voltage All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 4 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 6. Functional description Refer to Figure 1 “Block diagram of PCA9536”. 6.1 Registers 6.1.1 Command byte Table 4. Command byte Command Protocol Function 0 read byte Input Port register 1 read/write byte Output Port register 2 read/write byte Polarity Inversion register 3 read/write byte Configuration register The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. 6.1.2 Register 0 - Input Port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default ‘X’ is determined by the externally applied logic level, normally logic 1 when no external signal externally applied because of the internal pull-up resistors. Table 5. Register 0 - Input Port register bit description Legend: * default value PCA9536 Product data sheet Bit Symbol Access Value Description 7 I7 read only 1* not used 6 I6 read only 1* 5 I5 read only 1* 4 I4 read only 1* 3 I3 read only X 2 I2 read only X 1 I1 read only X 0 I0 read only X determined by externally applied logic level All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 5 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 6.1.3 Register 1 - Output Port register This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value. ‘Not used’ bits can be programmed with either logic 0 or logic 1. Table 6. Register 1 - Output Port register bit description Legend: * default value Bit Symbol Access Value Description 7 O7 R 1* not used 6 O6 R 1* 5 O5 R 1* 4 O4 R 1* 3 O3 R 1* 2 O2 R 1* 1 O1 R 1* 0 O0 R 1* reflects outgoing logic levels of pins defined as outputs by Register 3 6.1.4 Register 2 - Polarity Inversion register This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. ‘Not used’ bits can be programmed with either logic 0 or logic 1. Table 7. Register 2 - Polarity Inversion register bit description Legend: * default value PCA9536 Product data sheet Bit Symbol Access Value Description 7 N7 6 N6 R/W 0* not used R/W 0* 5 N5 R/W 0* 4 N4 R/W 0* 3 N3 R/W 0* 2 N2 R/W 0* 1 N1 R/W 0* 0 N0 R/W 0* inverts polarity of Input Port register data 0 = Input Port register data retained (default value) 1 = Input Port register data inverted All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 6 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 6.1.5 Register 3 - Configuration register This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VDD. ‘Not used’ bits can be programmed with either logic 0 or logic 1. Table 8. Register 3 - Configuration register bit description Legend: * default value Bit Symbol Access Value Description 7 C7 6 C6 R/W 1* not used R/W 1* 5 C5 R/W 1* 4 C4 R/W 1* 3 C3 R/W 1* 2 C2 R/W 1* configures the directions of the I/O pins 0 = corresponding port pin enabled as an output 1 C1 R/W 1* 0 C0 R/W 1* 1 = corresponding port pin configured as input (default value) 6.2 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9536 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9536 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. 6.3 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up (100 k typical) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 7 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port data from shift register output port register data configuration register data from shift register D VDD Q1 Q 100 kΩ FF write configuration pulse CK D Q Q FF IO0 to IO3 write pulse CK Q2 output port register VSS input port register D Q input port register data FF read pulse CK polarity inversion register data from shift register D polarity inversion register data Q FF write polarity pulse CK 002aab852 Remark: At power-on reset, all registers return to default values. Fig 5. Simplified schematic of IO0 to IO3 6.4 Device address slave address 1 0 0 0 0 0 fixed Fig 6. 1 R/W 002aab853 PCA9536 device address 6.5 Bus transactions Data is transmitted to the PCA9536 registers using the Write mode as shown in Figure 7 and Figure 8. Data is read from the PCA9536 registers using the Read mode as shown in Figure 9 and Figure 10. These devices do not implement an auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 8 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 1 0 0 0 0 data to port command byte 0 1 START condition 0 A 0 0 0 0 0 0 R/W 0 1 A P STOP condition acknowledge from slave acknowledge from slave acknowledge from slave A DATA 1 write to port tv(Q) data out from port data 1 valid 002aab854 Fig 7. Write to Output Port register SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 1 0 0 0 0 data to register command byte 0 1 START condition 0 A 0 0 0 0 0 R/W 0 0 1/0 A acknowledge from slave acknowledge from slave A DATA P STOP condition acknowledge from slave data to register 002aab855 Fig 8. Write to Configuration register or Polarity Inversion register slave address SDA S 1 0 0 0 0 0 1 START condition 0 A R/W acknowledge from slave acknowledge from slave data from register slave address (cont.) S 1 0 0 0 (repeated) START condition Fig 9. 0 (cont.) A command byte 0 1 1 A R/W acknowledge from slave DATA (first byte) data from register A acknowledge from master DATA (last byte) NA no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter P STOP condition 002aab856 Read from register PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 9 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 1 0 0 0 0 START condition data from port data from port 0 1 1 DATA 1 A R/W A STOP condition no acknowledge from master acknowledge from master acknowledge from slave NA P DATA 4 read from port tsu(D) th(D) data into port DATA 2 DATA 3 DATA 4 002aab857 This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. Fig 10. Read Input Port register 7. Application design-in information VDD 2 kΩ VDD 10 kΩ 10 kΩ VDD SDA SDA SCL SCL IO0 SUBSYSTEM 1 (e.g. temp. sensor) IO1 INT PCA9536 MASTER CONTROLLER IO2 RESET IO3 SUBSYSTEM 2 (e.g. counter) VSS A VSS controlled switch (e.g. CBT device) enable B 002aab858 Device address is 1000 001X; IO0, IO2, IO3 configured as outputs; IO1 configured as input. Fig 11. Typical application PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 10 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). PCA9536 Product data sheet Symbol Parameter VDD II Conditions Min Max Unit supply voltage 0.5 +6.0 V input current - 20 mA VI/O voltage on an input/output pin VSS  0.5 5.5 V IO(IOn) output current on pin IOn - 50 mA IDD supply current - 85 mA ISS ground supply current - 100 mA Ptot total power dissipation - 200 mW Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C Tj(max) maximum junction temperature - +125 C All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 11 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 9. Static characteristics Table 10. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.3 - 5.5 V Supplies VDD supply voltage IDD supply current operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz - 290 400 A Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs - 225 350 A Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs - 0.25 1 A - 1.7 2.2 V VPOR [1] power-on reset voltage Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V 3 6 - mA IL leakage current VI = VDD = VSS 1 - +1 A Ci input capacitance VI = VSS - 6 10 pF I/Os VIL LOW-level input voltage 0.5 - +0.8 V VIH HIGH-level input voltage 2.0 - 5.5 V IOL LOW-level output current VOH HIGH-level output voltage VOL = 0.5 V; VDD = 2.3 V [2] 8 10 - mA VOL = 0.7 V; VDD = 2.3 V [2] 10 13 - mA VOL = 0.5 V; VDD = 3.0 V [2] 8 14 - mA VOL = 0.7 V; VDD = 3.0 V [2] 10 19 - mA VOL = 0.5 V; VDD = 4.5 V [2] 8 17 - mA VOL = 0.7 V; VDD = 4.5 V [2] 10 24 - mA IOH = 8 mA; VDD = 2.3 V [3] 1.8 - - V IOH = 10 mA; VDD = 2.3 V [3] 1.7 - - V IOH = 8 mA; VDD = 3.0 V [3] 2.6 - - V IOH = 10 mA; VDD = 3.0 V [3] 2.5 - - V IOH = 8 mA; VDD = 4.75 V [3] 4.1 - - V IOH = 10 mA; VDD = 4.75 V [3] 4.0 - - V ILIH HIGH-level input leakage current VDD = 3.6 V; VI = VDD - - 1 A ILIL LOW-level input leakage current VDD = 5.5 V; VI = VSS - - 100 A Ci input capacitance - 3.7 5 pF Co output capacitance - 3.7 5 pF [1] VDD must be lowered to 0.2 V in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. [3] The total current sourced by all I/Os must be limited to 85 mA. PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 12 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 10. Dynamic characteristics Table 11. Dynamic characteristics Symbol Parameter Conditions fSCL SCL clock frequency tBUF Standard-mode I2C-bus Fast-mode I2C-bus Unit Min Max Min Max 0 100 0 400 bus free time between a STOP and START condition 4.7 - 1.3 - s tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - s tHD;DAT data hold time 0 - 0 - s tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s tVD;DAT data valid time [2] 300 - 50 - ns tSU;DAT data set-up time 250 - 100 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s 20 + 0.1Cb [3] 300 ns 20 + 0.1Cb [3] 300 ns rise time of both SDA and SCL signals tr - 1000 kHz tf fall time of both SDA and SCL signals - 300 tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tv(Q) data output valid time - 200 - 200 ns tsu(D) data input set-up time 100 - 100 - ns th(D) data input hold time 1 - 1 - s Port timing [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. 0.7 × VDD SDA 0.3 × VDD tr tBUF tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P 002aaa986 Fig 12. Definition of timing PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 13 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) STOP condition (P) acknowledge (A) 1 / fSCL 0.7 × VDD SCL 0.3 × VDD tBUF tr tf 0.7 × VDD SDA 0.3 × VDD tSU;DAT tHD;STA tVD;ACK tVD;DAT tHD;DAT tSU;STO 002aab175 Rise and fall times refer to VIL and VIH Fig 13. I2C-bus timing diagram 11. Test information VDD PULSE GENERATOR VI RL 500 Ω VO VDD open VSS DUT CL 50 pF RT 002aab880 RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 14. Test circuitry for switching times 500 Ω from output under test CL 50 pF S1 2VDD open VSS 500 Ω 002aab881 Fig 15. Test circuit Table 12. Test tv(Q) PCA9536 Product data sheet Test data Load Switch CL RL 50 pF 500  All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 2VDD © NXP Semiconductors N.V. 2017. All rights reserved. 14 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 12. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 16. Package outline SOT96-1 (SO8) PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 15 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 17. Package outline SOT505-1 (TSSOP8) PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 16 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm SOT908-1 0 1 2 mm scale X B D A E A A1 c detail X terminal 1 index area e1 terminal 1 index area e v w b 1 4 M M C C A B C y1 C y L exposed tie bar (4×) Eh exposed tie bar (4×) 8 5 Dh DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.3 0.2 0.2 3.1 2.9 2.25 1.95 3.1 2.9 1.65 1.35 0.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT908-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-09-26 05-10-05 MO-229 Fig 18. Package outline SOT908-1 (HVSON8) PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 17 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 13. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 18 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 and 14 Table 13. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3)  350 < 350 < 2.5 235 220  2.5 220 220 Table 14. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 19 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 15. PCA9536 Product data sheet Abbreviations Acronym Description ACPI Advanced Configuration and Power Interface CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge FET Field-Effect Transistor GPIO General Purpose Input/Output HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light-Emitting Diode MM Machine Model POR Power-On Reset SMBus System Management Bus All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 20 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 16. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9536 v.6 20171107 Product data sheet 201710002I PCA9536_5 Modifications: PCA9536_5 Modifications: • • Table 10 “Static characteristics”: Corrected VPOR typ and max limit Added Section 3.1 “Ordering options” 20100125 • Product data sheet - PCA9536_4 Table 10 “Static characteristics”, sub-section “Supplies”: – IDD Typical value changed from “104 A” to “290 A” – IDD Maximum value changed from “175 A” to “400 A” • Table 11 “Dynamic characteristics”: Unit for “tf, fall time of both SDA and SCL signals” changed from “s” to “ns” Remark: The changes made in this revision are to correct typographical errors only. There is no change in the performance of the device. PCA9536_4 20070911 Product data sheet - PCA9536_3 PCA9536_3 20061009 Product data sheet - PCA9536_2 PCA9536_2 (9397 750 14124) 20040930 Objective data sheet - PCA9536_1 PCA9536_1 (9397 750 12895) 20040820 Objective data sheet - - PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 21 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA9536 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 22 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 7 November 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 23 of 24 PCA9536 NXP Semiconductors 4-bit I2C-bus and SMBus I/O port 19. Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 6.5 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 5 Register 0 - Input Port register . . . . . . . . . . . . . 5 Register 1 - Output Port register. . . . . . . . . . . . 6 Register 2 - Polarity Inversion register . . . . . . . 6 Register 3 - Configuration register . . . . . . . . . . 7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 8 Application design-in information . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Handling information. . . . . . . . . . . . . . . . . . . . 18 Soldering of SMD packages . . . . . . . . . . . . . . 18 Introduction to soldering . . . . . . . . . . . . . . . . . 18 Wave and reflow soldering . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 November 2017 Document identifier: PCA9536