PCA9537DP

PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 05 — 7 May 2009 Product data sheet 1. General description The PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push-buttons, LEDs, fans, etc. The PCA9537 consists of a 4-bit Configuration register (input or output selection), 4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The PCA9537 open-drain interrupt output (INT) is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without de-powering the device. The I2C-bus address is fixed and allows only one device on the same I2C-bus/SMBus. 2. Features I I I I I I I I I I I I I 4-bit I2C-bus GPIO with interrupt and reset Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Active LOW reset input Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 4 I/O pins that default to 4 inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Offered in TSSOP10 package 3. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C Type number PCA9537DP Topside mark 9537 Package Name TSSOP10 Description plastic thin shrink small outline package; 10 leads; body width 3 mm Version SOT552-1 4. Block diagram PCA9537 IO0 SCL SDA INPUT FILTER I2C-BUS/SMBus CONTROL write pulse VDD RESET POWER-ON RESET read pulse VDD IO1 4-bit INPUT/ OUTPUT PORTS IO2 IO3 VSS LP FILTER 002aae634 INT Remark: All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9537 PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 2 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 5. Pinning information 5.1 Pinning IO0 IO1 IO2 IO3 VSS 1 2 3 4 5 002aae633 10 VDD 9 SDA PCA9537DP 8 7 6 SCL INT RESET Fig 2. Pin configuration for TSSOP10 5.2 Pin description Table 2. Symbol IO0 IO1 IO2 IO3 VSS RESET INT SCL SDA VDD Pin description Pin 1 2 3 4 5 6 7 8 9 10 Description input/output 0 input/output 1 input/output 2 input/output 3 supply ground active LOW reset input interrupt output (open-drain) serial clock line serial data line supply voltage PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 3 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6. Functional description Refer to Figure 1 “Block diagram of PCA9537”. 6.1 Device address slave address 1 0 0 1 fixed 002aae635 0 0 1 R/W Fig 3. PCA9537 address 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the registers will be written or read. Table 3. Command 0 1 2 3 Command byte Protocol read byte read/write byte read/write byte read/write byte Function Input Port register Output Port register Polarity Inversion register Configuration register 6.2.2 Register 0 - Input Port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. Table 4. Register 0 - Input Port register bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol I7 I6 I5 I4 I3 I2 I1 I0 Access read only read only read only read only read only read only read only read only Value 1* 1* 1* 1* X* X* X* X* value ‘X’ is determined by externally applied logic level Description not used PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 4 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.3 Register 1 - Output Port register This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 5. Register 1 - Output Port register bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol O7 O6 O5 O4 O3 O2 O1 O0 Access R R R R R R R R Value 1* 1* 1* 1* 1* 1* 1* 1* reflects outgoing logic levels of pins defined as outputs by Register 3 Description not used 6.2.4 Register 2 - Polarity Inversion register This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a 0), the Input Port data polarity is retained. Table 6. Register 2 - Polarity Inversion register bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol N7 N6 N5 N4 N3 N2 N1 N0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0* 0* 0* 0* 0* 0* 0* 0* inverts polarity of Input Port register data 0 = Input Port register data retained (default value) 1 = Input Port register data inverted Description not used PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 5 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.5 Register 3 - Configuration register This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs. Table 7. Register 3 - Configuration register bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol C7 C6 C5 C4 C3 C2 C1 C0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* configures the directions of the I/O pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin configured as an input (default value) Description not used 6.3 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9537 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9537 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. 6.4 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9537 registers and SMBus/I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used. 6.5 Interrupt output The open-drain interrupt output (INT) is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is de-activated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 6 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.6 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. data from shift register configuration register data from shift register write configuration pulse write pulse D FF CK Q D FF CK output port register input port register D FF read pulse CK Q Q2 output port register data VDD Q1 Q Q I/O pin VSS input port register data to INT polarity inversion register data from shift register write polarity pulse D FF CK 002aad723 Q polarity inversion register data Remark: At power-on reset, all registers return to default values. Fig 4. Simplified schematic of IO0 to IO3 PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 7 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.7 Bus transactions Data is transmitted to the PCA9537 registers using the write mode as shown in Figure 5 and Figure 6. Data is read from the PCA9537 registers using the read mode as shown in Figure 7 and Figure 8. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. SCL 1 2 3 4 5 6 7 8 9 command byte data to port 0 1 A acknowledge from slave DATA 1 A STOP condition slave address SDA S 1 0 0 1 0 0 1 0 R/W A 0 0 0 0 0 0 P START condition write to port acknowledge from slave acknowledge from slave tv(Q) data out from port DATA 1 VALID 002aae636 Expanded diagram is shown in Figure 16. Fig 5. Write to output port register SCL 1 2 3 4 5 6 7 8 9 command byte data to register 1 1/0 A acknowledge from slave DATA 1 A STOP condition slave address SDA S 1 0 0 1 0 0 1 0 R/W A 0 0 0 0 0 0 P START condition data to register acknowledge from slave acknowledge from slave 002aae637 Fig 6. Write to configuration or polarity inversion registers PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 8 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset slave address SDA S 1 0 0 1 0 0 1 0 R/W acknowledge from slave slave address (cont.) S 1 0 0 1 0 0 1 1 R/W acknowledge from slave A A COMMAND BYTE A (cont.) START condition acknowledge from slave data from register DATA (first byte) A acknowledge from master data from register DATA (last byte) NA P STOP condition (repeated) START condition no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter 002aae638 Fig 7. Read from register SCL 1 2 3 4 5 6 7 8 9 data from port data from port A acknowledge from master DATA 4 no acknowledge from master 1 P STOP condition slave address SDA S 1 0 0 1 0 0 1 1 R/W A DATA 1 START condition read from port data into port INT tv(INT) DATA 1 acknowledge from slave DATA 2 th(D) DATA 3 tsu(D) DATA 4 trst(INT) 002aae639 This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. Expanded diagram is shown in Figure 15. Fig 8. Read input port register PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 9 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 7. Application design-in information VDD (5 V) VDD MASTER CONTROLLER SCL SDA INT RESET VSS 10 kΩ 10 kΩ 10 kΩ 10 kΩ 2 kΩ 100 kΩ SUB-SYSTEM 1 (e.g., temp sensor) INT VDD PCA9537 SCL SDA INT RESET IO0 IO1 IO2 IO3 VSS enable SUB-SYSTEM 2 (e.g., counter) RESET A controlled switch (e.g., CBT device) B 002aae640 Device address is 1001 001x for this example. IO0, IO2, IO3 configured as outputs. IO1 configured as input. Fig 9. Typical application 7.1 Minimizing IDD when the I/Os are used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 9. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 10 shows a high value resistor in parallel with the LED. Figure 11 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. VDD 3.3 V 5V VDD LED 100 kΩ VDD LED IOn IOn 002aac660 002aac661 Fig 10. High value resistor in parallel with the LED Fig 11. Device supplied by a lower voltage PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 10 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 8. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD II VI/O IO(IOn) IDD ISS Ptot Tstg Tamb Tj(max) Parameter supply voltage input current voltage on an input/output pin output current on pin IOn supply current ground supply current total power dissipation storage temperature ambient temperature maximum junction temperature operating Conditions Min −0.5 VSS − 0.5 −65 −40 Max +6.0 ±20 5.5 ±50 85 100 200 +150 +85 +125 Unit V mA V mA mA mA mW °C °C °C 9. Static characteristics Table 9. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Supplies VDD IDD IstbL supply voltage supply current LOW-level standby current operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs no load; VI = VDD or VSS [1] Parameter Conditions Min 2.3 - Typ 104 0.25 Max 5.5 175 1 Unit V µA µA IstbH HIGH-level standby current - 0.25 1 µA VPOR VIL VIH IOL IL Ci power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance −0.5 0.7VDD 1.5 7 5 1.65 +0.3VDD 5.5 +1 10 V V V mA µA pF Input SCL; input/output SDA VOL = 0.4 V VI = VDD = VSS VI = VSS 3 −1 - PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 11 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 9. Static characteristics …continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol I/Os VIL VIH IOL LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.5 V VDD = 2.3 V VDD = 3.0 V VDD = 4.5 V VOL = 0.7 V VDD = 2.3 V VDD = 3.0 V VDD = 4.5 V VOH HIGH-level output voltage IOH = −8 mA VDD = 2.3 V VDD = 3.0 V VDD = 4.5 V IOH = −10 mA VDD = 2.3 V VDD = 3.0 V VDD = 4.5 V IL Ci IOL IOH VIL VIH IL [1] [2] [3] [3] [3] [3] [3] [3] [3] [2] [2] [2] [2] [2] [2] Parameter Conditions Min −0.5 2.0 8 8 8 10 10 10 1.8 2.6 4.1 1.7 2.5 4.0 −1 - Typ 10 14 17 13 19 24 5 13 - Max +0.8 5.5 +1 10 +1 +0.8 5.5 +1 Unit V V mA mA mA mA mA mA V V V V V V µA pF mA µA V V µA leakage current input capacitance LOW-level output current HIGH-level output current LOW-level input voltage HIGH-level input voltage leakage current VI = VDD = VSS Interrupt INT VOL = 0.4 V VOL = 0.4 V 3 −1 −0.5 2.0 VI = VDD = VSS −1 Select input RESET VDD must be lowered to 0.2 V in order to reset part. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. The total current sourced by all I/Os must be limited to 85 mA. PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 12 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 10. Dynamic characteristics Table 10. Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tr tf tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock rise time of both SDA and SCL signals fall time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter data output valid time data input set-up time data input hold time valid time on pin INT reset time on pin INT reset pulse width reset recovery time reset time tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for the SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF. [1] [2] Fast-mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1Cb[3] 20 + 0.1Cb[3] Max 400 0.9 300 300 50 Unit Max 100 3.45 1000 300 50 0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 - kHz µs µs µs µs ns µs ns ns µs µs ns ns ns Port timing tv(Q) tsu(D) th(D) tv(INT) trst(INT) RESET tw(rst) trec(rst) trst [1] [2] [3] 100 1 4 0 400 200 4 4 - 100 1 4 0 400 200 4 4 - ns ns µs µs µs ns ns ns Interrupt timing PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 13 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset SDA tBUF tLOW SCL tr tf tHD;STA tSP tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P 002aaa986 Fig 12. Definition of timing protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW tHIGH bit 6 (A6) bit 1 (D1) bit 0 (D0) acknowledge (A) STOP condition (P) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab285 Rise and fall times refer to VIL and VIH. Fig 13. I2C-bus timing diagram START SCL ACK or read cycle SDA 30 % trst RESET 50 % trec(rst) 50 % tw(rst) trst IOn 50 % after reset, I/Os reconfigured as inputs 002aad732 50 % Fig 14. Definition of RESET timing PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 14 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset SCL 2 1 0 A P 70 % 30 % SDA tsu(D) th(D) input tv(INT) INT 002aae641 50 % trst(INT) Fig 15. Expanded view of read input port register SCL 2 1 0 A P 70 % SDA tv(Q) output 002aad735 50 % Fig 16. Expanded view of write to output port register PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 15 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 11. Test information 6.0 V open VSS VDD PULSE GENERATOR VI DUT RT VO RL 500 Ω CL 50 pF 002aab393 RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 17. Test circuitry for switching times RL S1 from output under test CL 50 pF 500 Ω RL 500 Ω 2VDD open GND 002aac226 Fig 18. Test circuit Table 11. Test tv(Q) Test data Load RL 500 Ω CL 50 pF 2 × VDD Switch PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 16 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 12. Package outline TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1 D E A X c y HE vMA Z 10 6 A2 pin 1 index A1 (A3) A θ Lp L 1 e bp 5 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.15 c 0.23 0.15 D (1) 3.1 2.9 E (2) 3.1 2.9 e 0.5 HE 5.0 4.8 L 0.95 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z (1) 0.67 0.34 θ 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT552-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-07-29 03-02-18 Fig 19. Package outline SOT552-1 (TSSOP10) PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 17 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 13. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 18 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 20) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 20. PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 19 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 14. Acronym ACPI CBT CDM CMOS DUT ESD FET FF GPIO HBM I2C-bus I/O LED LP MM POR SMBus Abbreviations Description Advanced Configuration and Power Interface Cross-Bar Technology Charged-Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Field-Effect Transistor Flip-Flop General Purpose Input/Output Human Body Model Inter-Integrated Circuit bus Input/Output Light Emitting Diode Low-Pass Machine Model Power-On Reset System Management Bus PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 20 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 16. Revision history Table 15. Revision history Release date 20090507 Data sheet status Product data sheet Change notice Supersedes PCA9537_4 Document ID PCA9537_5 Modifications: • • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Pin names changed from “I/O0, I/O1, I/O2, I/O3” to “IO0, IO1, IO2, IO3”, respectively Section 6.4 “RESET input”, 1st sentence: changed symbol from “tW” to “tw(rst)” Figure 5 “Write to output por t register”: changed symbol from “tpv” to “tv(Q)” Figure 8 “Read input por t register”: – changed symbol from “tph” to “th(D)” – changed symbol from “tps” to “tsu(D)” – changed symbol from “tiv” to “tv(INT)” – changed symbol from “tir” to “trst(INT)” • Table 8 “Limiting values”: – parameter description for symbol VI/O changed from “DC voltage on an I/O” to “voltage on an input/output pin” – parameter description for symbol ISS changed from “supply current” to “ground supply current” – symbol/parameter changed from “II/O, DC output current on an I/O” to “IO(IOn), output current on pin IOn” • Table 9 “Static characteristics”, sub-section “Supplies”: – symbol/parameter changed from “Istbl, Standby current” to “IstbL, LOW-level standby current” – symbol/parameter changed from “Istbh, Standby current” to “IstbH, HIGH-level standby current” • Table 10 “Dynamic characteristics”, sub-section “Port timing”: – symbol/parameter changed from “tPV, Output data valid” to “tv(Q), data output valid time” – symbol/parameter changed from “tPS, Input data setup time” to “tsu(D), data input set-up time” – symbol/parameter changed from “tPH, Input data hold time” to “th(D), data input hold time” • Table 10 “Dynamic characteristics”, sub-section “Interrupt timing”: – symbol/parameter changed from “tIV, Interrupt valid” to “tv(INT), valid time on pin INT” – symbol/parameter changed from “tIR, Interrupt reset” to “trst(INT), reset time on pin INT” • Table 10 “Dynamic characteristics”, sub-section “RESET”: – symbol changed from “tW” to “tw(rst)” – symbol changed from “tREC” to “trec(rst)” – symbol/parameter changed from “tRESET, Time to reset” to “trst, reset time” • Figure 14 “Definition of RESET timing”: – symbol changed from “tW” to “tw(rst)” – symbol changed from “tREC” to “trec(rst)” – symbol changed from “tRESET” to “trst” • Figure 15 “Expanded view of read input por t register”: – changed symbol from “tPH” to “th(D)” – changed symbol from “tPS” to “tsu(D)” – changed symbol from “tIV” to “tv(INT)” – changed symbol from “tIR” to “trst(INT)” PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 21 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 15. Revision history …continued Release date Data sheet status Change notice Supersedes Document ID Modifications (continued): • • • • Figure 16 “Expanded view of write to output por t register”: changed symbol from “tPV” to “tv(Q)” (Old) Figure 18, “Test circuit” split into Figure 18 “Test circuit” and Table 11 “Test data” – symbol changed from “tpv” to “tv(Q)” Added soldering information Added Table 14 “Abbreviations” Product data sheet Product data sheet Objective data sheet Objective data sheet PCA9537_3 PCA9537_2 PCA9537_1 - PCA9537_4 PCA9537_3 (9397 750 14259) PCA9537_2 (9397 750 14052) PCA9537_1 (9397 750 12894) 20060921 20041129 20040930 20040820 PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 22 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9537_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 23 of 24 NXP Semiconductors PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 19. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.4 6.5 6.6 6.7 7 7.1 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4 Register 0 - Input Port register . . . . . . . . . . . . . 4 Register 1 - Output Port register. . . . . . . . . . . . 5 Register 2 - Polarity Inversion register . . . . . . . 5 Register 3 - Configuration register . . . . . . . . . . 6 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 6 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 8 Application design-in information . . . . . . . . . 10 Minimizing IDD when the I/Os are used to control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Handling information. . . . . . . . . . . . . . . . . . . . 18 Soldering of SMD packages . . . . . . . . . . . . . . 18 Introduction to soldering . . . . . . . . . . . . . . . . . 18 Wave and reflow soldering . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 May 2009 Document identifier: PCA9537_5