PCA9554PW,118

INTEGRATED CIRCUITS PCA9554/PCA9554A 8-bit I2C and SMBus I/O port with interrupt Product data sheet Supersedes data of 2002 Jul 26 
   2004 Sep 30 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A DESCRIPTION The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C/SMBus applications and were developed to enhance the Philips family of I@C I/O expanders. The improvements include higher drive capability, 5V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc. FEATURES The PCA9554/54A consist of an 8-bit Configuration register (Input or Output selection); 8-bit Input register, 8-bit Output register and an 8-bit Polarity inversion register (Active-HIGH or Active-LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion Register. All registers can be read by the system master. Although pin to pin and I2C address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in Application Note AN469. • Operating power supply voltage range of 2.3 to 5.5 V • 5 V tolerant I/Os • Polarity inversion register • Active-LOW interrupt output • Low stand-by current • Noise filter on SCL/SDA inputs • No glitch on power-up • Internal power-on reset • 8 I/O pins which default to 8 inputs • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, The PCA9554/54A open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Three hardware pins (A0, A1, A2) vary the fixed I2C address and allow up to eight devices to share the same I2C/SMBus. The PCA9554A is identical to the PCA9554 except that the fixed I2C address is different allowing up to sixteen of these devices (eight of each) on the same I2C/SMBus. • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA • Six packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16, and HVQFN16 ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER 16-Pin Plastic DIP –40 °C to +85 °C PCA9554N PCA9554N SOT38-1 16-Pin Plastic SO (wide) –40 °C to +85 °C PCA9554D PCA9554D SOT162-1 16-Pin Plastic SSOP –40 °C to +85 °C PCA9554DB 9554DB SOT338-1 20-Pin Plastic SSOP –40 °C to +85 °C PCA9554TS PCA9554 SOT266-1 16-Pin Plastic TSSOP –40 °C to +85 °C PCA9554PW 9554DH SOT403-1 16-Pin Plastic HVQFN –40 °C to +85 °C PCA9554BS 9554 SOT629-1 16-Pin Plastic DIP –40 °C to +85 °C PCA9554AN PCA9554AN SOT38-1 16-Pin Plastic SO (wide) –40 °C to +85 °C PCA9554AD PCA9554AD SOT162-1 16-Pin Plastic SSOP –40 °C to +85 °C PCA9554ADB 9554A SOT338-1 20-Pin Plastic SSOP –40 °C to +85 °C PCA9554ATS PA9554A SOT266-1 16-Pin Plastic TSSOP –40 °C to +85 °C PCA9554APW 9554ADH SOT403-1 16-Pin Plastic HVQFN –40 °C to +85 °C PCA9554ABS 554A SOT629-1 PACKAGES Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. I2C is a trademark of Philips Semiconductors Corporation. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent. 2004 Sep 30 2 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt 16 VDD 2 15 SDA A2 3 A0 VDD 15 14 SDA 13 A1 12 SCL 14 SCL I/O0 2 11 INT I/O0 4 13 INT I/O1 3 10 I/O7 I/O1 5 12 I/O7 I/O2 6 11 I/O6 I/O2 4 9 I/O3 7 10 I/O5 VSS 8 9 I/O4 I/O3 VSS I/O4 I/O6 8 7 1 A1 6 A2 5 A0 1 PIN CONFIGURATION — HVQFN 16 PIN CONFIGURATION — 16-pin DIP, SO, SSOP, TSSOP PCA9554/PCA9554A I/O5 TOP VIEW su01670 su01410 Figure 1. Pin configuration — 16-pin DIP, SO, SSOP, TSSOP Figure 2. Pin Configuration — HVQFN PIN CONFIGURATION — 20-pin SSOP INT 1 20 I/O7 SCL 2 19 I/O6 n.c. 3 18 n.c. SDA 4 17 I/O5 VDD 5 16 I/O4 A0 6 15 VSS A1 7 14 I/O3 n.c. 8 13 n.c. A2 9 12 I/O2 I/O0 10 11 I/O1 SW02269 Figure 1. Pin configuration — 20-pin SSOP PIN DESCRIPTION DIP16, SO16, SSOP16, TSSOP16 PIN NUMBER HVQFN16 PIN NUMBER SSOP20 PIN NUMBER SYMBOL 1 15 6 A0 Address input 0 2 16 7 A1 Address input 1 3 1 9 A2 Address input 2 4–7 2–5 10–12, 14 I/O0 to I/O3 8 6 15 VSS 2004 Sep 30 FUNCTION I/O0 to I/O3 Supply ground 9 7–10 16, 17, 19, 20 I/O4 to I/O7 13 11 1 INT Interrupt output (open drain) 14 12 2 SCL Serial clock line 15 13 4 SDA Serial data line 16 14 5 VDD Supply voltage – – 3, 8, 13, 18 n.c. not connected 3 I/O4 to I/O7 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A BLOCK DIAGRAM A0 A1 I/O0 A2 I/O1 SCL SDA I/O2 INPUT FILTER 8-BIT I2C/SMBUS CONTROL INPUT/ OUTPUT PORTS I/O3 I/O4 WRITE pulse I/O5 READ pulse I/O6 I/O7 VDD VCC POWER-ON RESET LP FILTER VSS INT NOTE: ALL I/Os ARE SET TO INPUTS AT RESET SU01411 Figure 3. Block diagram 2004 Sep 30 4 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt REGISTERS Command Byte Command PCA9554/PCA9554A Register 2 – Polarity Inversion Register Protocol Function 0 Read byte Input port register 1 Read/write byte Output port register 2 Read/write byte Polarity inversion register 3 Read/write byte Configuration register bit N7 N6 N5 N4 N3 N2 N1 N0 default 0 0 0 0 0 0 0 0 This register allows the user to invert the polarity of the Input Port Register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. Register 3 – Configuration Register Register 0 – Input Port Register bit I7 I6 I5 I4 I3 I2 I1 I0 default X X X X X X X X O5 O4 O3 O2 O1 O0 default 1 1 1 1 1 1 1 1 C5 C4 C3 C2 C1 C0 1 1 1 1 1 1 1 When power is applied to VDD, an internal power-on reset holds the PCA9554 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9554 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. Register 1 – Output Port Register O6 C6 1 Power-on Reset The default value ‘X’ is determined by the externally applied logic level, normally ‘1’ when no external signal externally applied because of the internal pull-up resistors. O7 C7 This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VDD. This register is a read only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. bit bit default For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. Interrupt Output This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, NOT the actual pin value. The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the input port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. 2004 Sep 30 5 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7 DATA FROM SHIFT REGISTER OUTPUT PORT REGISTER DATA CONFIGURATION REGISTER DATA FROM SHIFT REGISTER VDD Q D Q1 FF WRITE CONFIGURATION PULSE CK 100 kΩ Q D Q FF I/O0 TO I/O7 WRITE PULSE CK Q Q2 OUTPUT PORT REGISTER INPUT PORT REGISTER D Q VSS INPUT PORT REGISTER DATA FF READ PULSE Q CK DATA FROM SHIFT REGISTER TO INT D Q POLARITY REGISTER DATA FF WRITE POLARITY PULSE CK Q POLARITY INVERSION REGISTER SU01472 NOTE: At Power-on Reset, all registers return to default values. Figure 4. Simplified schematic of I/O0 to I/O7 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up (100 kΩ typ.) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and either VDD or VSS. 2004 Sep 30 6 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A Device address SLAVE ADDRESS 0 1 0 0 FIXED A2 A1 slave address A0 R/W 0 1 HARDWARE SELECTABLE 1 1 fixed A2 A1 A0 R/W programmable su01418 su01669 Figure 5. PCA9554 address Figure 6. PCA9554A address Bus transactions Data is transmitted to the PCA9554/PCA9554A registers using the write mode as shown in Figures 7 and 8. Data is read from the PCA9554/PCA9554A registers using the read mode as shown in Figures 9 and 10. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. 1 SCL 2 3 4 5 6 7 8 9 command byte slave address SDA S 0 1 0 0 A2 A1 A0 start condition 0 A R/W 0 0 0 0 0 data to port 0 0 1 acknowledge from slave DATA 1 A A acknowledge from slave P acknowledge from slave WRITE TO PORT DATA 1 VALID DATA OUT FROM PORT tpv su01421 Figure 7. WRITE to output port register 1 SCL 2 3 4 5 6 7 8 9 command byte slave address SDA S 0 1 start condition 0 0 A2 A1 A0 0 R/W A 0 0 0 0 0 acknowledge from slave data to register 0 1 1/0 A DATA acknowledge from slave A P acknowledge from slave DATA TO REGISTER su01422 Figure 8. WRITE to configuration or polarity inversion registers 2004 Sep 30 7 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt acknowledge from slave slave address S 0 1 0 0 A2 A1 A0 0 PCA9554/PCA9554A acknowledge from slave COMMAND BYTE A A S acknowledge from slave slave address 0 1 0 0 A2 A1 A0 R/W 1 acknowledge from master data from register DATA A A first byte R/W at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from register no acknowledge from master NA DATA P last byte su01424 Figure 9. READ from register 1 SCL 2 3 4 5 6 7 8 9 slave address SDA S 0 1 start condition 0 0 A2 data from port A1 A0 1 R/W data from port DATA 1 A A acknowledge from slave DATA 4 acknowledge from master NA no acknowledge from master P stop condition READ FROM PORT DATA INTO PORT DATA 2 DATA 3 tph DATA 4 tps INT tiv tir su01465 NOTES: 1. This figure assumes the command byte has previously been programmed with 00h. 2. Transfer of data can be stopped at any moment by a stop condition. Figure 10. READ input port register 2004 Sep 30 8 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A TYPICAL APPLICATION VDD (5 V) 2 kΩ VDD 10 kΩ 10 kΩ 10 kΩ 10 kΩ VDD SCL MASTER CONTROLLER SDA INT I/O1 INT INT I/O2 RESET GND I/O3 PCA9554/ PCA9554A SUBSYSTEM 2 (e.g. counter) I/O4 I/O5 A2 A Controlled Switch (e.g. CBT device) I/O6 ENABLE A1 I/O7 B A0 VSS ALARM SUBSYSTEM 3 (e.g. alarm system) NOTE: Device address configured as 0100100 for this example I/O0, I/O1, I/O2, configured as outputs I/O3, I/O4, I/O5, configured as inputs I/O06, I/O7, are not used and have to be configured as outputs VDD SW2288 Figure 11. Typcial application. 2004 Sep 30 9 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD II PARAMETER CONDITIONS Supply voltage DC input current VI/O DC voltage on an I/O MIN MAX –0.5 6.0 UNIT V — ±20 mA VSS – 0.5 5.5 V II/O DC output current on an I/O — ±50 mA IDD Supply current — 85 mA ISS Supply current — 100 mA Ptot Total power dissipation — 200 mW Tstg Storage temperature range –65 +150 °C Tamb Operating ambient temperature –40 +85 °C 2004 Sep 30 10 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”. DC CHARACTERISTICS VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supplies VDD Supply voltage 2.3 — 5.5 V — 104 175 µA IDD Supply current Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz Istbl Standby current Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs — 550 700 µA Istbh Standby current Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs — 0.25 1 µA Power-on reset voltage (Note 1) No load; VI = VDD or VSS — 1.5 1.65 V V VPOR Input SCL; input/output SDA VIL LOW level input voltage –0.5 — 0.3VDD VIH HIGH level input voltage 0.7VDD — 5.5 V IOL LOW level output current VOL = 0.4 V 3 — — mA IL Leakage current VI = VDD = VSS –1 — +1 µA CI Input capacitance VI = VSS — 6 10 pF VIL LOW level input voltage –0.5 — 0.8 V VIH HIGH level input voltage 2.0 — 5.5 V VOL = 0.5 V; VDD = 2.3 V; Note 2 8 10 — mA VOL = 0.7 V; VDD = 2.3 V; Note 2 10 13 — mA VOL = 0.5 V; VDD = 4.5 V; Note 2 8 17 — mA VOL = 0.7 V; VDD = 4.5 V; Note 2 10 24 — mA VOL = 0.5 V; VDD = 3.0 V; Note 2 8 14 — mA VOL = 0.7 V; VDD = 3.0 V; Note 2 10 19 — mA IOH = –8 mA; VDD = 2.3 V; Note 3 1.8 — — V IOH = –10 mA; VDD = 2.3 V; Note 3 1.7 — — V IOH = –8 mA; VDD = 3.0 V; Note 3 2.6 — — V IOH = –10 mA; VDD = 3.0 V; Note 3 2.5 — — V IOH = –8 mA; VDD = 4.75 V; Note 3 4.1 — — V IOH = –10 mA; VDD = 4.75 V; Note 3 4.0 — — V I/Os IOL O VOH O LOW level output current HIGH level output voltage IIH Input leakage current VDD = 3.6 V; VI = VDD — — 1 µA IIL Input leakage current VDD = 5.5 V; VI = VSS — — –100 µA CI Input capacitance — 3.7 5 pF CO Output capacitance — 3.7 5 pF 3 — — mA V Interrupt INT IOL LOW level output current VOL = 0.4 V Select Inputs A0, A1, A2 VIL LOW level input voltage –0.5 — 0.8 VIH HIGH level input voltage 2.0 — 5.5 V ILI Input leakage current –1 — 1 µA NOTES: 1. VDD must be lowered to 0.2 V in order to reset part. 2. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. 3. The total current sourced by all I/Os must be limited to 85 mA. 2004 Sep 30 11 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A SDA tLOW tF tF tSU;DAT tR tHD;STA tR tSP tBUF SCL S tHD;STA tSU;STA tHD;DAT tHIGH tSU;STD SR P S SU01469 Figure 12. Definition of timing AC SPECIFICATIONS SYMBOL STANDARD MODE I2C-BUS PARAMETER MIN MAX FAST MODE I2C-BUS UNITS MIN MAX fSCL Operating frequency 0 100 0 400 kHz tBUF Bus free time between STOP and START conditions 4.7 — 1.3 — µs tHD;STA Hold time after (repeated) START condition 4.0 — 0.6 — µs tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs tSU;STO Setup time for STOP condition 4.0 — 0.6 — µs tHD;DAT Data in hold time 0 — 0 — ns tVD;ACK Valid time for ACK condition2 0.3 3.45 0.1 0.9 µs tVD;DAT Data out valid time3 300 — 50 — ns tSU;DAT Data setup time 250 — 100 — ns tLOW Clock LOW period 4.7 — 1.3 — µs tHIGH Clock HIGH period 4.0 — 0.6 — µs tF Clock/Data fall time — 300 20 + 0.1 Cb1 300 ns tR Clock/Data rise time — 1000 20 + 0.1 Cb1 300 ns tSP Pulse width of spikes that must be suppressed by the input filters — 50 — 50 ns ns Port Timing tPV Output data valid — 200 — 200 tPS Input data setup time 100 — 100 — ns tPH Input data hold time 1 — 1 — µs Interrupt Timing tIV Interrupt valid — 4 — 4 µs tIR Interrupt reset — 4 — 4 µs NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. 2004 Sep 30 12 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt DIP16: plastic dual in-line package; 16 leads (300 mil); long body 2004 Sep 30 13 PCA9554/PCA9554A SOT38-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt SO16: plastic small outline package; 16 leads; body width 7.5 mm 2004 Sep 30 14 PCA9554/PCA9554A SOT162-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 2004 Sep 30 15 SOT338-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm 2004 Sep 30 16 SOT266-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 2004 Sep 30 17 SOT403-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm 2004 Sep 30 18 SOT629-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A REVISION HISTORY Rev Date Description _6 20040930 Product data (9397 750 13289). Supersedes data of 2002 Jul 26 (9397 750 10163). Modifications: • Add DIP16 and SSOP20 packages to Features, Ordering information, Pin configuration, Pin description, and package outline drawings. • Section “Register 0—Input Port Register” on page 4: change default values to ‘XXXXXXXX’ and add second paragraph. • “Power-on Reset” section on page 5 modified. • Add new “Typical application” section on page 9. • DC Characteristics table on page 11: – add (new) Note 1, and its reference at VPOR. – Note 2 re-written. _5 20020726 Product data (9397 750 10163). ECN 853-2243 28672 of 26 July 2002. Supersedes data of 2002 May 13 (9397 750 09817). _4 20020513 Product specification (9397 750 09817) _3 Product specification (9397 750 08342) _2 Product specification (9397 750 08209) _1 Product specification (9397 750 08159) 2004 Sep 30 19 Philips Semiconductors Product data sheet 8-bit I2C and SMBus I/O port with interrupt PCA9554/PCA9554A Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data sheet Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data sheet Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data sheet Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Koninklijke Philips Electronics N.V. 2004 All rights reserved. Published in the U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 09-04 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document number: 
   2004 Sep 30 20 9397 750 13289