PCA9646D

PCA9646 Buffered 4-channel 2-wire bus switch Rev. 1 — 1 March 2011 Product data sheet 1. General description The PCA9646 is a monolithic CMOS integrated circuit for 2-wire bus buffering and switching in applications including I2C-bus, SMBus, PMBus, and other systems based on similar principles. Each of the four outputs may be independently enabled in any combination as determined by the contents of the programmable control register. Each I/O is impedance isolated from all others, thus allowing a total of five branches of 2-wire bus with the maximum specified load (e.g., 5  400 pF for Fm+ I2C-bus at 1 MHz, or 5  4 nF at lower frequencies) (Ref. 1). More than one PCA9646 may be used in series, providing a substantial fan-out capability. As per the PCA9525 and PCA9605 simple bus buffers, the PCA9646 includes a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. The direction of the clock signal may also be set by the contents of the programmable control register. Clock stretching and timing must always be under control of the master device. The PCA9646 has excellent application to 2-wire bus address expansion and increasing of maximum load capacitance. Very large LED displays are a perfect example. 2. Features and benefits  Drop-in pin compatible with PCA9546A, etc.  Each I/O is impedance isolated from all others allowing maximum capacitance on all branches  30 mA static sink capability on all ports  Works with I2C-bus (Standard-mode, Fast-mode, and Fast-mode Plus (Fm+)), SMBus (standard and high power mode), and PMBus  Fast switching times allow operation in excess of 1 MHz  Allows driving of large loads (e.g., 5  4 nF)  Hysteresis on I/O increases noise immunity  Operating voltages from 2.7 V to 5.5 V  Uncomplicated characteristics suitable for quick implementation in most common 2-wire bus applications 3. Applications  Large arrays of I2C-bus components, e.g., LED displays  Power management systems  Game consoles, computers, RAID systems NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 4. Ordering information Table 1. Ordering information Topside mark PCA9646 PCA9646 Package Name SO16 TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT403-1 Type number PCA9646D PCA9646PW 5. Block diagram 2.7 V to 5.5 V VDD R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 16 PCA9646 5 SC0 7 SC1 10 SC2 SCL 14 12 SC3 4 SD0 6 SD1 9 SD2 SDA 15 11 SD3 1 FILTER RESET 3 8 VSS I2C-BUS CONTROL 2 13 A0 A1 A2 002aaf367 Fig 1. Simplified block diagram of PCA9646 PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 2 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 6. Pinning information 6.1 Pinning A0 A1 RESET SD0 SC0 SD1 SC1 VSS 1 2 3 4 16 VDD 15 SDA 14 SCL 13 A2 A0 A1 RESET SD0 SC0 SD1 SC1 VSS 1 2 3 4 5 6 7 8 002aaf366 16 VDD 15 SDA 14 SCL 13 A2 12 SC3 11 SD3 10 SC2 9 SD2 PCA9646D 5 6 7 8 002aaf364 12 SC3 11 SD3 10 SC2 9 SD2 PCA9646PW Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16 6.2 Pin description Table 2. Symbol A0 A1 RESET SD0 SC0 SD1 SC1 VSS SD2 SC2 SD3 SC3 A2 SCL SDA VDD Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description address input 0 address input 1 active LOW reset input serial data 0 serial clock 0 serial data 1 serial clock 1 negative supply (ground) serial data 2 serial clock 2 serial data 3 serial clock 3 address input 2 serial clock line (normally input) serial data line positive supply PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 3 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 7. Functional description Refer to Figure 1 “Simplified block diagram of PCA9646”. 7.1 VDD, VSS — DC supply pins The power supply voltage for the PCA9646 may be any voltage in the range 2.7 V to 5.5 V. The IC supply must be common with the supply for the bus. Hysteresis on the ports are a percentage of the IC’s power supply, hence noise margin considerations should be taken into account when selecting an operating voltage. 7.2 SCL — clock signal input The clock signal buffer is unidirectional, with this pin acting as the default input. However, the clock signal direction may be reversed by setting the MSB of the Control register HIGH. In normal I2C-bus operations the master device generates a unidirectional clock signal to the slave. For lowest cost the PCA9646 combines unidirectional buffering of the clock signal with a bidirectional buffer for the data signal. Clock stretching is therefore not supported and slave devices that may require clock stretching must be accommodated by the master adopting an appropriate clocking when communicating with them. The buffer includes hysteresis to ensure clean switching signals are output, especially with slow rise times on high capacitively loaded buses. 7.3 SC0, SC1, SC2, SC3 — clock signal outputs The clock signal from SCL is buffered through four independent buffers, and the signal is presented at the four SC0 to SC3 ports. Ports are open-drain type and require external pull-up resistors. When the MSB of the control register is set HIGH, the port direction is reversed. The ANDed result of the selected SC0 to SC3 lines is then used to drive the open-drain output of the SCL pin. 7.4 SDA, SD0, SD1, SD2, SD3 — data signal inputs/outputs The data signal buffers are bidirectional. The port (SDA, or any one of SD0 to SD3) which first falls LOW, will decide the direction of this buffer and ‘lock out’ signals coming from the opposite side. As the ‘input’ signal continues to fall, it will then drive the open-drain of the ‘output’ side LOW. Again, hysteresis is applied to the buffer to minimize the effects of noise. Ports are open-drain type and require external pull-up resistors. At some points during the communication, the data direction will reverse—for example, when the slave transmits an acknowledge (ACK) or responds with its register contents. During these times, the controlling ‘input’ side will have to rise to Vunlock before it releases the ‘lock’, which then allows the ‘output’ side to gain control, and pull (what was) the ‘input’ side LOW again. This will cause a ‘pulse’ on the ‘input’ side, which can be quite long duration in high capacitance buses. However, this pulse will not interfere with the actual data transmission, as it should not occur during times of clock line transition (during normal I2C-bus and SMBus protocols), and thus data signal set-up time requirements are still met. PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 4 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 7.5 RESET — reset IC to default state The active LOW RESET input is used to disable the buffer, and reset it to its default state. The IC should only be disabled when the bus is idle to avoid truncation of commands which may confuse other devices on the bus. The RESET signal will clear the contents of the Control register, which has the effect of disabling all output lines SC[0:3] and SD[0:3]. It is the nature of the I2C-bus protocol that devices may become ‘stuck’. To help in the clearing of this condition, the PCA9646 can be reset, and each port brought on-line successively to find the component holding the bus LOW. 7.6 Power-On Reset (POR) During power-on, the PCA9646 is internally held in the reset condition for a maximum of trst = 500 ns. The default condition after reset is for the Control register to be erased (all zeros), resulting in all output channels being disabled. 7.7 A0, A1, A2 — address lines The slave address of the PCA9646 is shown in Figure 4. The address pins (A2, A1, A0) must be driven to a HIGH or LOW level—they are not internally pulled to a default state. 1 1 fixed 1 0 A2 A1 A0 R/W read = 1 write = 0 002aaf368 externally selectable Fig 4. Slave address The read/write bit must be set LOW to enable a write to the Control register, or HIGH to read from the Control register. 7.8 Control register The Control register of the PCA9646 is shown in Figure 5. Each of the four output channels (SCn/SDn pairs) can be enabled independently, and the direction of the clock signal can be reversed. output channel enable bits MSB B7 X X X B3 B2 B1 B0 LSB SC0/SD0 enable SC1/SD1 enable SC2/SD2 enable SC3/SD3 enable SCL direction 0: SCL → SC0 to SC3 1: SC0 to SC3 → SCL 002aaf369 Fig 5. PCA9646 Control register All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 5 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch A LOW or ‘zero’ bit (B[3:0]) indicates that the respective channel (SC[3:0], SD[3:0]) is disabled. The default reset condition of the register is all zeros, all channels disabled, forward direction. A HIGH or ‘one’ bit indicates the respective channel is enabled. Example: B3 = 1, B2 = 0, B1 = 1, B0 = 0 means channel 3 (SC3/SD3) and channel 1 (SC1/SD1) are enabled, and channel 2 (SC2/SD2) and channel 0 (SC0/SD0) are disabled. As each channel is individually buffered, the loads on each are isolated, and therefore there is no special requirement to keep the sum of the collective capacitances below the maximum bus capacitance. Instead, each line may have up to the maximum bus capacitance and be enabled or disabled without affecting the performance of the other channels. The Most Significant Bit (MSB) B7 is used to set the direction of the SCL (clock) signal. The default state is LOW (zero). In this state, the SCL port will act as the input, and the IC will supply a buffered signal to any of the four output channels (SC0 to SC3) which are enabled. When B7 is set HIGH (one), the clock signal direction is reversed. The ports SC0 to SC3 act as inputs, the ANDed combination of the selected signals is buffered and output on the SCL pin. The PCA9646 is always addressable from the SCL/SDA side, regardless of the state of B7. Any device which can communicate data to the SCL/SDA pins, either by being directly attached to those pins or by transmitting through the PCA9646 (when B7 = 1), may address the device and change the control register’s contents. The Control register is only updated upon receipt of the STOP condition. 8. Bus transaction A typical I2C-bus write transaction to the PCA9646 is shown in Figure 6. A typical read transaction is shown in Figure 7. slave address S 1 1 1 0 A2 A1 A0 0 A B7 X Control register X X B3 B2 B1 B0 A P START condition R/W acknowledge from slave acknowledge from slave STOP condition 002aaf370 Fig 6. PCA9646 write transaction to Control register slave address S 1 1 1 0 A2 A1 A0 1 A B7 0 Control register 0 0 B3 B2 B1 B0 NA P START condition R/W acknowledge from slave not acknowledge from master STOP condition 002aaf371 Fig 7. PCA9646 PCA9646 read transaction from Control register All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 6 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 9. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI/O VI II ISS Ptot Tstg Tamb [1] Parameter supply voltage voltage on an input/output pin input voltage input current ground supply current total power dissipation storage temperature ambient temperature Conditions [1] Min 0.3 VSS  0.5 VSS  0.5 VSS  0.5 55 [1] [1] [1] Max +7 +7 VDD + 0.5 VDD + 0.5 20 40 280 300 +125 +85 Unit V V V V mA mA mA mW C C pins SDx, SCx RESET pin address pins A2, A1, A0 pins other than SCx/SDx all SCx and SDx operating 40 Voltages are specified with respect to pin 8 (VSS). 10. Characteristics Table 4. Characteristics Tamb = 40 C to +85 C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified. Symbol VDD IDD I2C-bus VI2C-bus VIL VIH VI(hys) ILI IO(sink) VOL Parameter supply voltage supply current I2C-bus voltage LOW-level input voltage HIGH-level input voltage hysteresis of input voltage input leakage current output sink current LOW-level output voltage Conditions operating quiescent; VI (RESET pin) = 0 V SDx, SCx VDD = 2.7 V VDD = 5.5 V VDD = 2.7 V VDD = 5.5 V VDD = 2.7 V VDD = 5.5 V pin at VDD or VSS LOW-level; VSxx input < VIL IOL = 30 mA; VDD = 2.7 V IOL = 30 mA; VDD = 5.5 V Pins SDA, SD0, SD1, SD2, SD3 Vlock Vunlock direction lock voltage direction unlock voltage VDD = 2.7 V VDD = 5.5 V VDD = 2.7 V VDD = 5.5 V [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] Min 2.7 1.2 2.0 80 200 1 30 2.0 4.8 Typ 260 140 - Max 5.5 1 5.5 0.4 0.5 +1 450 275 1.3 3.0 - Unit V A V V V V V mV mV A mA mV mV V V V V Power supply ports (SCL, SDA, SC[3:0], SD[3:0]) PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 7 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch Table 4. Characteristics …continued Tamb = 40 C to +85 C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified. Symbol RESET VIH VIL Vhys ILI tw(rst)L trst tPOR VIH VIL ILI td tf [1] [2] Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage input leakage current LOW-level reset time reset time power-on reset pulse time HIGH-level input voltage LOW-level input voltage input leakage current delay time fall time Conditions VDD = 2.7 V VDD = 5.5 V VDD = 2.7 V VDD = 5.5 V VDD = 2.7 V VDD = 5.5 V pin at VDD or VSS VI < VIL RESET pin; from VI > VIH RESET pin; from VI > VIH VDD = 2.7 V VDD = 5.5 V VDD = 2.7 V VDD = 5.5 V pin at VDD or VSS RPU = 200 ; VDD = 2.7 V RPU = 200 ; VDD = 5.5 V RPU = 200  [2] Min 2.0 4.8 100 200 1 1.7 3.5 1 - Typ 25 250 250 100 70 16 Max 650 900 +1 500 500 0.7 1.5 +1 - Unit V V mV mV mV mV A ns ns ns V V V V A ns ns ns Address pins (A0, A1, A2) Timing characteristics (Figure 8) Supply voltage dependent; refer to graphs (Figure 9 through Figure 12) for typical trend. Guaranteed by design, not subject to test. VI2C-bus 70 % VDD VIL 30 % VDD SDx, SCx input SDx, SCx output td tf time 002aaf438 Fig 8. Timing diagram PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 8 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 5 VI (V) 4 002aaf333 1000 VI(hys) (V) 800 Tamb = +85 °C +25 °C −40 °C 002aaf334 3 Vlock 2 VIH 1 VIL 0 2 3 4 5 VDD (V) 6 600 400 200 0 2 3 4 5 VDD (V) 6 Tamb = 25 C Fig 9. Typical input levels versus supply voltage Fig 10. Typical VIH  VIL hysteresis versus supply voltage 002aaf373 250 VOL (mV) 200 002aaf372 400 VOL (mV) 300 VDD = 2.7 V 150 200 100 VDD = 5.5 V 50 2.7 V 0 0 200 400 600 800 1000 RPU (Ω) 0 −50 0 50 100 Tamb (C) 150 5.5 V 100 Tamb = 25 C IOL = 30 mA Fig 11. Typical LOW-level output voltage versus pull-up resistance Fig 12. Typical LOW-level output voltage versus ambient temperature PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 9 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 11. Application information Figure 13 shows a typical data transfer through the PCA9646. The PCA9646 has excellent application to extending loads and expanding the address space of slave devices. Rise times are determined simply by the side of the buffer with the slowest RC time constant. SCL (clock) SDA (data) S START sequence A0 (master) A1 (master) A2 (master) A3 (master) A4 (master) A5 (master) A6 (master) W (master) ACK (slave) P SDA direction 'hand over' pulses upon change of device asserting the data line STOP sequence purpose of bit (address bit 5) device asserting data line (master/slave) master side of PCA9646 slave side of PCA9646 002aaf374 Remark: Input to output delay exaggerated for clarity. Fig 13. Typical communication sequence through the PCA9646 Figure 14 shows a typical application for the PCA9646. Each channel can support up to the maximum permissible capacitance load, thus the maximum loading of the system can be 5 times that which could be achieved without buffering. The channel enable function can be used to interface buses of different operating frequencies. When certain bus sections are enabled, the system frequency may be limited by a bus section having a slave device specified only to 100 kHz. When that bus section is disabled, the slow slave is isolated and the remaining bus can be run at 400 kHz. The timing performance and current sinking capability will allow the PCA9646 to run in excess of the 1 MHz maximum limit of the I2C-bus Fast-mode Plus (Fm+), or to run a huge 4 nF load at 100 kHz. Figure 15 shows the PCA9646 used as a line driver. Four such lines (only one shown) can be run from the same device. The receiving end may then again be used as a 4-way bus switch, radiating out into another four lines. Using the address pins, this entire structure may be repeated. Thus a total of eight PCA9646 ‘line drivers’ may be connected to a single bus master (U1), allowing for 32 (8  4) long distance bus pairs to be driven from the one I2C-bus port. PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 10 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 3.3 V VDD R1 1.1 kΩ R2 1.1 kΩ VDD SCL SDA RESET SC0 SD0 R7 1.1 kΩ R8 1.1 kΩ SCL SDA SC0 SD0 SCL SDA SCL SDA VDD VDD SC1 SD1 VDD 002aaf375 SCL SDA VDD BUS MASTER U3 400 pF load at 1 MHz or 4 nF load at 100 kHz PCA9646 MASTER/ SLAVE U4 R3 1.1 kΩ R4 1.1 kΩ SLAVE U5 SLAVE U6 400 pF load at 1 MHz or 4 nF load at 100 kHz SC2 SD2 400 pF load at 1 MHz or 4 nF load at 100 kHz SC3 SD3 400 pF load at 1 MHz or 4 nF load at 100 kHz R5 1.1 kΩ R6 1.1 kΩ SC2 SD2 R9 1.1 kΩ R10 1.1 kΩ SC1 SC3 SD3 A0 SDA A1 A2 VSS U1 U7 SDA SCL SCL VDD SD1 SLAVE SLAVE U8 400 pF load at 1 MHz or 4 nF load at 100 kHz Fig 14. PCA9646 typical buffer application 5V R1 R2 VDD VDD SCL SDA SCL SDA etc. SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 R3 180 Ω R4 180 Ω R5 R6 VDD SCL SDA SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 SCL SDA VDD BUS MASTER U1 e.g., PC/TV receiver or decoder box SLAVE U4 e.g., monitor, flat TV, LED array RESET A0 A1 A2 U2 RESET A0 A1 A2 U3 address address PCA9646 backplane or long cable run with 30 mA pull-up current PCA9646 002aaf376 Fig 15. PCA9646 as a 30 mA line driver PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 11 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch Figure 16 shows how PCA9646 can be used to combine or extend existing long cable systems using P82B715 I2C-bus extenders when they have reached their maximum capacitance limit. P82B715 alone provides a ‘10 impedance transformation’ (Ref. 2) but no isolation of the loadings on either side. P82B715 systems have a finite capacitance limit and its system calculations can be relatively complex. The buffering action of PCA9646 simplifies calculations and allows the isolated bus rise time to meet the Fast-mode requirement even when that is not possible on the long cable section. Of course it is possible to create a much larger system by connecting existing long P82B715 cable systems to each of the four channels and driving all of them from one isolated Master. 5V no pull-up required VDD SCL SDA SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 SX SY VCC LX LY R1 1.8 kΩ R2 1.8 kΩ R3 R4 SCL SDA P82B715 U2 long cable run RESET isolated I2C-bus 3 A[2:0] PCA9646 U1 002aaf377 PCA9646 provides bus isolation and simplifies calculation of bus RC components. Fig 16. PCA9646 isolating the standard I2C-bus from a P82B715 used as a line driver PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 12 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch The PCA9646 may also be driven in series. Figure 17 shows this configuration. In this scenario, each of the four outputs of the first device (U2) has six more PCA9646’s connected to it. Each of those six devices has four outputs, thus giving 4  7  4 = 112 outputs. If the RESET pin on U2 was also driven from the master, it would be possible to reproduce this entire structure multiple times, giving a truly massive address space capability. Such a configuration may be applied to situations such as display drivers. 5V R1 180 Ω R2 180 Ω VDD VDD SCL SDA SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 R3 180 Ω R4 180 Ω VDD SCL SDA SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 SCL SDA BUS MASTER RESET U1 000b RESET 3 A[2:0] 001b 3 A[2:0] PCA9646 U2 up to seven PCA9646s on each output pair (address: 001b to 111b) structure in dashed box repeated U3 PCA9646 5V VDD SCL SDA SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 total output of 4 × 7 × 4 = 112 individually enabled fully isolated buses, each with full capacitance load (e.g., 400 pF at 1 MHz) etc. 3 RESET 010b A[2:0] PCA9646 U4 connect, for example, 8 LED driver ICs, each with 8 LED outputs = 7168 LEDs up to seven devices (address: 001b to 111b) 002aaf378 Fig 17. PCA9646 series implementation for large I/O fan-out PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 13 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 A1 pin 1 index θ Lp 1 8 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 8o o 0 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 18. Package outline SOT109-1 (SO16) PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 14 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 19. Package outline SOT403-1 (TSSOP16) PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 15 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 13. Handling information CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • PCA9646 Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 16 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 20) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 5 and 6 Table 5. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5  2.5 Table 6. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245  350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 20. PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 17 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 7. Acronym CMOS I2C-bus I/O IC LED MSB PMBus RAID RC SMBus Abbreviations Description Complementary Metal-Oxide Semiconductor Inter-Integrated Circuit bus Input/Output Integrated Circuit Light-Emitting Diode Most Significant Bit Power Management Bus Redundant Array of Independent Discs Resistor-Capacitor network System Management Bus 16. References [1] [2] UM10204, “I2C-bus specification and user manual” — NXP Semiconductors; www.nxp.com/documents/user_manual/UM10204.pdf P82B715, I2C-bus extender — NXP Semiconductors; Product data sheet; www.nxp.com/documents/data_sheet/P82B715.pdf PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 18 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 17. Revision history Table 8. Revision history Release date 20110301 Data sheet status Product data sheet Change notice Supersedes Document ID PCA9646 v.1 PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 19 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2011. All rights reserved. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or PCA9646 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 1 — 1 March 2011 20 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 1 March 2011 21 of 22 NXP Semiconductors PCA9646 Buffered 4-channel 2-wire bus switch 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 VDD, VSS — DC supply pins . . . . . . . . . . . . . . . 4 SCL — clock signal input . . . . . . . . . . . . . . . . . 4 SC0, SC1, SC2, SC3 — clock signal outputs. . 4 SDA, SD0, SD1, SD2, SD3 — data signal inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 4 RESET — reset IC to default state . . . . . . . . . . 5 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 5 A0, A1, A2 — address lines . . . . . . . . . . . . . . . 5 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 Bus transaction . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Handling information. . . . . . . . . . . . . . . . . . . . 16 Soldering of SMD packages . . . . . . . . . . . . . . 16 Introduction to soldering . . . . . . . . . . . . . . . . . 16 Wave and reflow soldering . . . . . . . . . . . . . . . 16 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 March 2011 Document identifier: PCA9646