PCAL9539A
Low-voltage 16-bit I2C-bus and SMBus low power I/O port with
interrupt and reset
Rev. 1 — 3 October 2012
Product data sheet
1. General description
The PCAL9539A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander
with interrupt and reset for I2C-bus/SMBus applications. NXP I/O expanders provide a
simple solution when additional I/Os are needed while keeping interconnections to a
minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control,
etc.
In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V
allows the PCAL9539A to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCAL9539A contains the PCA9539 register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers, and additionally, the PCAL9539A has
Agile I/O, which are additional features specifically designed to enhance the I/O. These
additional features are: programmable output drive strength, latchable inputs,
programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,
programmable open-drain or push-pull outputs.
The PCAL9539A is a pin-to-pin replacement to the PCA9539 and PCA9539A, however,
the PCAL9539A powers up with all I/O interrupts masked. This mask default allows for a
board bring-up free of spurious interrupts at power-up.
The PCAL9539A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the PCAL9539A can
remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine. In the PCAL9539A, the RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device, holding the registers and I2C-bus
state machine in their default state until the RESET input is once again HIGH. This input
requires a pull-up to VDD.
Two hardware pins (A0, A1) select the fixed I2C-bus address and allow up to four devices
to share the same I2C-bus/SMBus.
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
2. Features and benefits
I2C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
1.5 A (typical at 5 V VDD)
1.0 A (typical at 3.3 V VDD)
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
Vhys = 0.10 VDD (typical)
5 V tolerant I/Os
Active LOW reset input (RESET)
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I2C-bus
Internal power-on reset
Power-up with all channels configured as inputs
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection exceeds JESD22
2000 V Human Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP24, HVQFN24
2.1 Agile I/O features
Pin to pin replacement for PCA9539 and PCA9539A with interrupts disabled at
power-up
Software backward compatible with PCA9539 and PCA9539A
Output port configuration: bank selectable push-pull or open-drain output stages
Interrupt status: read-only register identifies the source of an interrupt
Bit-wise I/O programming features:
Output drive strength: four programmable drive strengths to reduce rise and fall
times in low capacitance applications
Input latch: Input Port register values changes are kept until the Input Port register
is read
Pull-up/pull-down enable: floating input or pull-up/down resistor enable
Pull-up/pull-down selection: 100 k pull-up/down resistor selection
Interrupt mask: mask prevents the generation of the interrupt when input changes
state
PCAL9539A
Product data sheet
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
2 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
3. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCAL9539AHF
L39A
HWQFN24
plastic thermal enhanced very very thin quad flat package;
no leads; 24 terminals; body 4 4 0.75 mm
SOT994-1
PCAL9539APW
PCAL9539A
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature range
PCAL9539AHF
PCAL9539AHF,128
HWQFN24
Reel pack, SMD,
13-inch, Turned
6000
Tamb = 40 C to +85 C
PCAL9539APW
PCAL9539APW,118
TSSOP24
Reel pack, SMD,
13-inch
2500
Tamb = 40 C to +85 C
4. Block diagram
PCAL9539A
P1_0
P1_1
8-bit
A0
A1
write pulse
P1_2
INPUT/
OUTPUT
PORTS
P1_3
P1_4
P1_5
P1_6
read pulse
P1_7
I2C-BUS/SMBus
CONTROL
SCL
SDA
P0_0
INPUT
FILTER
P0_1
8-bit
write pulse
VDD
RESET
P0_2
INPUT/
OUTPUT
PORTS
P0_3
P0_4
P0_5
P0_6
read pulse
P0_7
POWER-ON
RESET
VSS
VDD
INT
LP
FILTER
002aag167
Remark: All I/Os are set to inputs at reset.
Fig 1.
PCAL9539A
Product data sheet
Block diagram of PCAL9539A
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
3 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
5. Pinning information
5.1 Pinning
24 RESET
PCAL9539AHF
RESET
3
22 SCL
P0_0
4
21 A0
P0_0
1
18 A0
P0_1
5
20 P1_7
P0_1
2
17 P1_7
P0_2
6
19 P1_6
P0_2
3
16 P1_6
P0_3
7
18 P1_5
P0_3
4
15 P1_5
P0_4
8
17 P1_4
P0_4
5
14 P1_4
P0_5
9
16 P1_3
P0_5
6
13 P1_3
P0_6 10
15 P1_2
P0_7 11
14 P1_1
VSS 12
13 P1_0
P1_2 12
9
VSS
P1_1 11
8
P1_0 10
7
P0_7
002aag169
Transparent top view
002aag168
Fig 2.
P0_6
PCAL9539APW
terminal 1
index area
19 SCL
23 SDA
21 VDD
20 SDA
24 VDD
2
22 INT
1
A1
23 A1
INT
Pin configuration for TSSOP24
Fig 3.
Pin configuration for HWQFN24
5.2 Pin description
PCAL9539A
Product data sheet
Table 3.
Pin description
Symbol
Pin
Type
Description
TSSOP24
HWQFN24
INT
1
22
O
Interrupt output. Connect to VDD through a
pull-up resistor.
A1
2
23
I
Address input 1. Connect directly to VDD or VSS.
RESET
3
24
I
Active LOW reset input. Connect to VDD through
a pull-up resistor if no active connection is used.
P0_0[2]
4
1
I/O
Port 0 input/output 0.
P0_1[2]
5
2
I/O
Port 0 input/output 1.
P0_2[2]
6
3
I/O
Port 0 input/output 2.
P0_3[2]
7
4
I/O
Port 0 input/output 3.
P0_4[2]
8
5
I/O
Port 0 input/output 4.
P0_5[2]
9
6
I/O
Port 0 input/output 5.
P0_6[2]
10
7
I/O
Port 0 input/output 6.
P0_7[2]
11
8
I/O
Port 0 input/output 7.
VSS
12
9[1]
power
Ground.
P1_0[3]
13
10
I/O
Port 1 input/output 0.
P1_1[3]
14
11
I/O
Port 1 input/output 1.
P1_2[3]
15
12
I/O
Port 1 input/output 2.
P1_3[3]
16
13
I/O
Port 1 input/output 3.
P1_4[3]
17
14
I/O
Port 1 input/output 4.
P1_5[3]
18
15
I/O
Port 1 input/output 5.
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Rev. 1 — 3 October 2012
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4 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
16
I/O
Port 1 input/output 6.
17
I/O
Port 1 input/output 7.
TSSOP24
HWQFN24
P1_6[3]
19
P1_7[3]
20
A0
21
18
I
Address input 0. Connect directly to VDD or VSS.
SCL
22
19
I
Serial clock bus. Connect to VDD through a
pull-up resistor.
SDA
23
20
I/O
Serial data bus. Connect to VDD through a
pull-up resistor.
VDD
24
21
power
Supply voltage.
[1]
HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
[2]
Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
[3]
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
6. Functional description
Refer to Figure 1 “Block diagram of PCAL9539A”.
6.1 Device address
slave address
1
1
1
0
fixed
1
A1
A0 R/W
hardware
selectable
002aah062
Fig 4. PCAL9539A device address
A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1)
or LOW (logic 0) to assign one of the four possible slave addresses. The last bit of the
slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCAL9539A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
PCAL9539A
Product data sheet
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
5 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
(Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in
conjunction with the lower four bits of the Command byte are used to point to the
extended features of the device (Agile I/O). This register is write only.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig 5.
Table 4.
Pointer register bits
Command byte
Pointer register bits
Command byte Register
(hexadecimal)
Protocol
Power-up
default
read byte
xxxx xxxx[1]
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
00h
Input port 0
0
0
0
0
0
0
0
1
01h
Input port 1
read byte
xxxx xxxx
0
0
0
0
0
0
1
0
02h
Output port 0
read/write byte
1111 1111
0
0
0
0
0
0
1
1
03h
Output port 1
read/write byte
1111 1111
0
0
0
0
0
1
0
0
04h
Polarity Inversion port 0
read/write byte
0000 0000
0
0
0
0
0
1
0
1
05h
Polarity Inversion port 1
read/write byte
0000 0000
0
0
0
0
0
1
1
0
06h
Configuration port 0
read/write byte
1111 1111
0
0
0
0
0
1
1
1
07h
Configuration port 1
read/write byte
1111 1111
0
1
0
0
0
0
0
0
40h
Output drive strength
register 0
read/write byte
1111 1111
0
1
0
0
0
0
0
1
41h
Output drive strength
register 0
read/write byte
1111 1111
0
1
0
0
0
0
1
0
42h
Output drive strength
register 1
read/write byte
1111 1111
0
1
0
0
0
0
1
1
43h
Output drive strength
register 1
read/write byte
1111 1111
0
1
0
0
0
1
0
0
44h
Input latch register 0
read/write byte
0000 0000
0
1
0
0
0
1
0
1
45h
Input latch register 1
read/write byte
0000 0000
0
1
0
0
0
1
1
0
46h
Pull-up/pull-down enable
register 0
read/write byte
0000 0000
0
1
0
0
0
1
1
1
47h
Pull-up/pull-down enable
register 1
read/write byte
0000 0000
0
1
0
0
1
0
0
0
48h
Pull-up/pull-down
selection register 0
read/write byte
1111 1111
0
1
0
0
1
0
0
1
49h
Pull-up/pull-down
selection register 1
read/write byte
1111 1111
0
1
0
0
1
0
1
0
4Ah
Interrupt mask register 0
read/write byte
1111 1111
0
1
0
0
1
0
1
1
4Bh
Interrupt mask register 1
read/write byte
1111 1111
0
1
0
0
1
1
0
0
4Ch
Interrupt status register 0
read byte
0000 0000
0
1
0
0
1
1
0
1
4Dh
Interrupt status register 1
read byte
0000 0000
0
1
0
0
1
1
1
1
4Fh
Output port configuration
register
read/write byte
0000 0000
[1]
Undefined.
PCAL9539A
Product data sheet
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6 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.2 Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration
register. The Input port registers are read only; writes to these registers have no effect.
The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 7.2 “Reading the port
registers”.
Table 5.
Bit
Input port 0 register (address 00h)
7
6
5
4
3
2
1
0
Symbol
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 6.
Bit
Input port 1 register (address 01h)
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
6.2.3 Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not the actual pin value. A register pair write is described in
Section 7.1 and a register pair read is described in Section 7.2.
Table 7.
Bit
7
6
5
4
3
2
1
0
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
1
1
1
1
1
1
1
1
Table 8.
Bit
PCAL9539A
Product data sheet
Output port 0 register (address 02h)
Output port 1 register (address 03h)
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
1
1
1
1
1
1
1
1
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PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.4 Polarity inversion register pair (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the
corresponding port pin’s polarity is inverted in the Input register. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair
write is described in Section 7.1 and a register pair read is described in Section 7.2.
Table 9.
Bit
Polarity inversion port 0 register (address 04h)
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 10.
Bit
Polarity inversion port 1 register (address 05h)
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
6.2.5 Configuration register pair (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a
bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write is described in Section 7.1 and a register pair
read is described in Section 7.2.
Table 11.
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
Table 12.
Bit
PCAL9539A
Product data sheet
Configuration port 0 register (address 06h)
Configuration port 1 register (address 07h)
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
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PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.6 Output drive strength register pairs (40h, 41h, 42h, 43h)
The Output drive strength registers control the output drive level of the GPIO. Each GPIO
can be configured independently to a certain output current level by two register control
bits. For example, Port 0.7 is controlled by register 41 bits CC0.7 (bits [7:6]), Port 0.6 is
controlled by register 41 CC0.6(bits [5:4]). The output drive level of the GPIO is
programmed 00b = 0.25, 01b = 0.50, 10b = 0.75, or 11b = 1 of the maximum drive
capability of the I/O. See Section 8.2 “Output drive strength control”. A register pair write is
described in Section 7.1 and a register pair read is described in Section 7.2.
Table 13.
Bit
Current control port 0 register (address 40h)
7
Symbol
Default
Table 14.
Bit
Table 15.
Bit
1
Table 16.
Bit
3
CC0.2
1
7
1
6
2
1
CC0.1
1
5
CC0.7
1
0
CC0.0
1
1
1
1
4
3
2
1
0
CC0.6
1
1
CC0.5
1
CC0.4
1
1
1
1
3
2
1
0
Current control port 1 register (address 42h)
7
6
5
CC1.3
1
4
CC1.2
1
1
CC1.1
1
CC1.0
1
1
1
1
3
2
1
0
Current control port 1 register (address 43h)
7
Symbol
Default
4
Current control port 0 register (address 41h)
Symbol
Default
5
CC0.3
Symbol
Default
6
6
5
CC1.7
1
4
CC1.6
1
1
CC1.5
1
1
CC1.4
1
1
1
6.2.7 Input latch register pair (44h, 45h)
The input latch registers (registers 44 and 45) enable and disable the input latch of the I/O
pins. These registers are effective only when the pin is configured as an input port. When
an input latch register bit is 0, the corresponding input pin state is not latched. A state
change of the corresponding input pin generates an interrupt. A read of the input register
clears the interrupt. If the input goes back to its initial logic state before the input port
register is read, then the interrupt is cleared.
When an input latch register bit is 1, the corresponding input pin state is latched. A change
of state in the input generates an interrupt and the input logic value is loaded into the
corresponding bit of the input port register (registers 0 and 1). A read of the input port
register clears the interrupt. If the input pin returns to its initial logic state before the input
port register is read, then the interrupt is not cleared and the corresponding bit of the input
port register keeps the logic value that initiated the interrupt. See Figure 12 “Read input
port register (latch enabled), scenario 3”.
For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back to
logic 0, the input port 0 register will capture this change and an interrupt is generated (if
unmasked). When the read is performed on the input port 0 register, the interrupt is
PCAL9539A
Product data sheet
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
9 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
cleared, assuming there were no additional input(s) that have changed, and bit 4 of the
input port 0 register will read ‘1’. The next read of the input port 0 register bit 4 register
should now read ‘0’.
An interrupt remains active when a non-latched input simultaneously switches state with a
latched input and then returns to its original state. A read of the input register reflects only
the change of state of the latched input and also clears the interrupt. The interrupt is not
cleared if the input latch register changes from latched to non-latched configuration. If the
input pin is changed from latched to non-latched input, a read from the input port register
reflects the current port logic level. If the input pin is changed from non-latched to latched
input, the read from the input register reflects the latched logic level. A register pair write is
described in Section 7.1 and a register pair read is described in Section 7.2.
Table 17.
Bit
Input latch port 0 register (address 44h)
7
6
5
4
3
2
1
0
Symbol
L0.7
L0.6
L0.5
L0.4
L0.3
L0.2
L0.1
L0.0
Default
0
0
0
0
0
0
0
0
Table 18.
Bit
Input latch port 1 register (address 45h)
7
6
5
4
3
2
1
0
Symbol
L1.7
L1.6
L1.5
L1.4
L1.3
L1.2
L1.1
L1.0
Default
0
0
0
0
0
0
0
0
6.2.8 Pull-up/pull-down enable register pair (46h, 47h)
These registers allow the user to enable or disable pull-up/pull-down resistors on the I/O
pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting
the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the
resistors will be disconnected when the outputs are configured as open-drain outputs (see
Section 6.2.12). Use the pull-up/pull-down registers to select either a pull-up or pull-down
resistor. A register pair write is described in Section 7.1 and a register pair read is
described in Section 7.2.
Table 19.
Bit
7
6
5
4
3
2
1
0
Symbol
PE0.7
PE0.6
PE0.5
PE0.4
PE0.3
PE0.2
PE0.1
PE0.0
Default
0
0
0
0
0
0
0
0
Table 20.
Bit
PCAL9539A
Product data sheet
Pull-up/pull-down enable port 0 register (address 46h)
Pull-up/pull-down enable port 1 register (address 47h)
7
6
5
4
3
2
1
0
Symbol
PE1.7
PE1.6
PE1.5
PE1.4
PE1.3
PE1.2
PE1.1
PE1.0
Default
0
0
0
0
0
0
0
0
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
10 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.9 Pull-up/pull-down selection register pair (48h, 49h)
The I/O port can be configured to have a pull-up or pull-down resistor by programming the
pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up
resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that
I/O pin. If the pull-up/pull-down feature is disconnected, writing to this register will have no
effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
A register pair write is described in Section 7.1 and a register pair read is described in
Section 7.2.
Table 21.
Bit
Pull-up/pull-down selection port 0 register (address 48h)
7
6
5
4
3
2
1
0
Symbol
PUD0.7
PUD0.6
PUD0.5
PUD0.4
PUD0.3
PUD0.2
PUD0.1
PUD0.0
Default
1
1
1
1
1
1
1
1
Table 22.
Bit
Pull-up/pull-down selection port 1 register (address 49h)
7
6
5
4
3
2
1
0
Symbol
PUD1.7
PUD1.6
PUD1.5
PUD1.4
PUD1.3
PUD1.2
PUD1.1
PUD1.0
Default
1
1
1
1
1
1
1
1
6.2.10 Interrupt mask register pair (4Ah, 4Bh)
Interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during
system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0.
If an input changes state and the corresponding bit in the Interrupt mask register is set
to 1, the interrupt is masked and the interrupt pin will not be asserted. If the corresponding
bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted.
When an input changes state and the resulting interrupt is masked (interrupt mask bit
is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted.
If the interrupt mask bit of an input that is currently the source of an interrupt is set to 1,
the interrupt pin will be de-asserted. A register pair write is described in Section 7.1 and a
register pair read is described in Section 7.2.
Table 23.
Bit
7
6
5
4
3
2
1
0
Symbol
M0.7
M0.6
M0.5
M0.4
M0.3
M0.2
M0.1
M0.0
Default
1
1
1
1
1
1
1
1
Table 24.
Bit
PCAL9539A
Product data sheet
Interrupt mask port 0 register (address 4Ah) bit description
Interrupt mask port 1 register (address 4Bh) bit description
7
6
5
4
3
2
1
0
Symbol
M1.7
M1.6
M1.5
M1.4
M1.3
M1.2
M1.1
M1.0
Default
1
1
1
1
1
1
1
1
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
11 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.11 Interrupt status register pair (4Ch, 4Dh)
These read-only registers are used to identify the source of an interrupt. When read, a
logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0
indicates that the input pin is not the source of an interrupt.
When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt
status bit will return logic 0. A register pair write is described in Section 7.1 and a register
pair read is described in Section 7.2.
Table 25.
Bit
Interrupt status port 0 register (address 4Ch) bit description
7
6
5
4
3
2
1
0
Symbol
S0.7
S0.6
S0.5
S0.4
S0.3
S0.2
S0.1
S0.0
Default
0
0
0
0
0
0
0
0
Table 26.
Bit
Interrupt status port 1 register (address 4Dh) bit description
7
6
5
4
3
2
1
0
Symbol
S1.7
S1.6
S1.5
S1.4
S1.3
S1.2
S1.1
S1.0
Default
0
0
0
0
0
0
0
0
6.2.12 Output port configuration register (4Fh)
The output port configuration register selects port-wise push-pull or open-drain I/O stage.
A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 6). A logic 1
configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended
command sequence to program this register (4Fh) before the configuration registers (06h,
07h) sets the port pins as outputs.
ODEN0 configures Port 0_x and ODEN1 configures Port 1_x.
Table 27.
Bit
Output port configuration register (address 4Fh)
7
6
5
Symbol
Default
PCAL9539A
Product data sheet
4
3
2
reserved
0
0
0
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 October 2012
0
0
1
0
ODEN1
ODEN0
0
0
© NXP B.V. 2012. All rights reserved.
12 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.3 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
data from
shift register
data from
shift register
write
configuration
pulse
output port
register data
configuration
register
D
VDD
Q
Q1
ESD
protection
diode
Q2
ESD
protection
diode
FF
CK
D
Q
Q
FF
write pulse
CK
P0_0 to P0_7
P1_0 to P1_7
output port
register
VSS
D
Q
input port
register data
FF
read pulse
CK
VDD
PULL-UP/PULL-DOWN
CONTROL
INTERRUPT
MASK
input port
register
100 kΩ
D
input latch
register
data from
shift register
D
data from
shift register
CK
Q
LATCH
Q
read pulse
FF
write input
latch pulse
to INT
polarity inversion
register
D
EN
input port
latch
Q
FF
write polarity
pulse
CK
002aah428
At power-on reset, all registers return to default values.
Fig 6. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
PCAL9539A
Product data sheet
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
13 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.4 Power-on reset
When power (from 0 V) is applied to VDD, an internal power-on reset holds the
PCAL9539A in a reset condition until VDD has reached VPOR. At that time, the reset
condition is released and the PCAL9539A registers and I2C-bus/SMBus state machine
initializes to their default states. After that, VDD must be lowered to below VPORF and back
up to the operating voltage for a power-reset cycle. See Section 8.3 “Power-on reset
requirements”.
6.5 RESET input
The RESET input can be asserted to initialize the system while keeping the VDD at its
operating level. A reset can be accomplished by holding the RESET pin LOW for a
minimum of tw(rst). The PCAL9539A registers and I2C-bus/SMBus state machine are
changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O
levels at the ports can be changed externally or through the master. This input requires a
pull-up resistor to VDD if no active connection is used.
6.6 Interrupt output
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port
changes back to the original value or when data is read form the port that generated the
interrupt (see Figure 10). Resetting occurs in the Read mode at the acknowledge (ACK)
or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the
resetting of the interrupt during this pulse. Any change of the I/Os after resetting is
detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to VDD.
When using the input latch feature, the input pin state is latched. The interrupt is reset only
when data is read from the port that generated the interrupt. The reset occurs in the Read
mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of
the SCL signal.
PCAL9539A
Product data sheet
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
14 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
7. Bus transactions
The PCAL9539A is an I2C-bus slave device. Data is exchanged between the master and
PCAL9539A through write and read commands using I2C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Writing to the port registers
Data is transmitted to the PCAL9539A by sending the device address and setting the least
significant bit to a logic 0 (see Figure 4 “PCAL9539A device address”). The command
byte is sent after the address and determines which register will receive the data following
the command byte.
Twenty-two registers within the PCAL9539A are configured to operate as eleven register
pairs. The eleven pairs are input port, output port, polarity inversion, configuration,
output drive strength (two 16-bit registers), input latch, pull-up/pull-down enable,
pull-up/pull-down selection, interrupt mask, and interrupt status registers. After sending
data to one register, the next data byte is sent to the other register in the pair (see Figure 7
and Figure 8). For example, if the first byte is sent to Output Port 1 (register 3), the next
byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, the host can continuously update a register pair independently of the other registers,
or the host can simply update a single register.
PCAL9539A
Product data sheet
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
15 of 48
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2
3
4
5
6
7
8
9
slave address
SDA S
1
1
1
data to port 0
command byte
0
1 A1 A0 0
START condition
R/W
NXP Semiconductors
PCAL9539A
Product data sheet
1
SCL
A
0
0
0
0
0
0
1
0
acknowledge
from slave
A 0.7
data to port 1
0.0 A 1.7
DATA 0
acknowledge
from slave
DATA 1
1.0 A
P
STOP
condition
acknowledge
from slave
write to port
tv(Q)
data out
from port 1
DATA VALID
002aad725
Fig 7.
Write to output port registers
SCL
1
2
3
4
5
6
7
8
9
slave address
1
1
1
1 A1 A0 0
START condition
R/W
A
0 0/1 0
16 of 48
© NXP B.V. 2012. All rights reserved.
acknowledge
from slave
0 0/1 0/1 0/1 0/1 A
MSB
acknowledge
from slave
STOP
condition
data to register
DATA 0
A
LSB
MSB
acknowledge
from slave
DATA 1
A
P
LSB
acknowledge
from slave
002aah063
Fig 8.
Write to Control registers
PCAL9539A
0
SDA S
data to register
command byte
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Rev. 1 — 3 October 2012
All information provided in this document is subject to legal disclaimers.
tv(Q)
data out
from port 0
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
7.2 Reading the port registers
In order to read data from the PCAL9539A, the bus master must first send the
PCAL9539A address with the least significant bit set to a logic 0 (see Figure 4
“PCAL9539A device address”). The command byte is sent after the address and
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte is sent by the PCAL9539A (see Figure 9, Figure 10 and
Figure 11). Data is clocked into the register on the falling edge of the acknowledge clock
pulse. After the first byte is read, additional bytes may be read but the data now reflects
the information in the other register in the pair. For example, if Input Port 1 is read, the
next byte read is Input Port 0. There is no limit on the number of data bytes received in
one read transmission, but on the final byte received the bus master must not
acknowledge the data.
After a subsequent restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register
that is read after the restart is the Input Port 0.
command byte
slave address
SDA S
1
1
1
0
1 A1 A0 0
START condition
A
0 0/1 0
R/W
acknowledge
from slave
acknowledge
from slave
data from lower or
upper byte of register
slave address
(cont.) S
1
1
1
0
(repeated)
START condition
MSB
1 A1 A0 1
(cont.)
0 0/1 0/1 0/1 0/1 A
A
data from upper or
lower byte of register
LSB
DATA (first byte)
R/W
acknowledge
from slave
MSB
A
acknowledge
from master
LSB
DATA (last byte)
NA P
no acknowledge
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
STOP
condition
002aah064
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 9.
Read from register
PCAL9539A
Product data sheet
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
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NXP Semiconductors
PCAL9539A
Product data sheet
data into port 0
data into port 1
tv(INT)
SCL
1
2
3
4
trst(INT)
5
6
slave address
SDA S
1
1
1
0
START condition
7
8
9
R/W
1 A1 A0 1
I0.x
A
acknowledge
from slave
7
6
5
4
3
I1.x
2
1
0
A
7
acknowledge
from master
6
5
4
3
I0.x
2
1
0
A
acknowledge
from master
7
6
5
4
3
STOP condition
I1.x
2
1
0
A
acknowledge
from master
7
6
5
4
3
2
1
0
1
P
non acknowledge
from master
read from port 0
read from port 1
002aah407
Fig 10. Read input port register (input latch disabled), scenario 1
PCAL9539A
18 of 48
© NXP B.V. 2012. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Rev. 1 — 3 October 2012
All information provided in this document is subject to legal disclaimers.
INT
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DATA 00
DATA 01
DATA 02
DATA 03
tsu(D)
th(D)
data into port 1
NXP Semiconductors
PCAL9539A
Product data sheet
data into port 0
DATA 10
DATA 11
DATA 12
tsu(D)
th(D)
tv(INT)
SCL
1
2
3
4
trst(INT)
5
6
slave address
SDA S
1
1
1
0
START condition
7
8
9
R/W
1 A1 A0 1
I0.x
A
acknowledge
from slave
I1.x
DATA 00
A
acknowledge
from master
DATA 10
I0.x
A
acknowledge
from master
DATA 03
I1.x
A
acknowledge
from master
DATA 12
STOP condition
1
P
non acknowledge
from master
read from port 0
read from port 1
002aah408
Fig 11. Read input port register (non-latched), scenario 2
PCAL9539A
19 of 48
© NXP B.V. 2012. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Rev. 1 — 3 October 2012
All information provided in this document is subject to legal disclaimers.
INT
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DATA 01
DATA 02
NXP Semiconductors
PCAL9539A
Product data sheet
data into port 0
DATA 01
tsu(D)
data into port 1
DATA 10
DATA 11
DATA 10
I1.x
I0.x
th(D)
tv(INT)
SCL
1
2
3
4
trst(INT)
5
6
slave address
SDA S
1
1
1
0
START condition
7
8
9
R/W
1 A1 A0 1
I0.x
A
acknowledge
from slave
DATA 01
A
acknowledge
from master
DATA 10
A
acknowledge
from master
DATA 02
I1.x
A
acknowledge
from master
DATA 11
STOP condition
1
P
non acknowledge
from master
read from port 0
read from port 1
002aah065
Fig 12. Read input port register (latch enabled), scenario 3
PCAL9539A
20 of 48
© NXP B.V. 2012. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Rev. 1 — 3 October 2012
All information provided in this document is subject to legal disclaimers.
INT
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
8. Application design-in information
VDD
(3.3 V)
10 kΩ
10 kΩ
10 kΩ
10 kΩ
2 kΩ
VDD
VDD
MASTER
CONTROLLER
PCAL9539A
INT
SCL
SCL
P0_0
SDA
SDA
P0_1
INT
INT
RESET
RESET
SUB-SYSTEM 1(1)
(e.g., temp sensor)
100 kΩ
(×3)
SUB-SYSTEM 2
(e.g., counter)
P0_2
RESET
P0_3
VSS
A
P0_4
controlled
switch
(e.g., CBT device)
enable
P0_5
B
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
A1
A0
SUB-SYSTEM 3(1)
(e.g., alarm system)
10 DIGIT
NUMERIC
KEYPAD
ALARM
VDD
VSS
002aag170
Device address configured as 1110 100X for this example.
P0_0, P0_2, P0_3 configured as outputs.
P0_1, P0_4, P0_5 configured as inputs.
P0_6, P0_7 and (P1_0 to P1_7) configured as inputs.
(1) External resistors are required for inputs (on P port) that may float. Also, internal pull-up or pull-down may be used to eliminate
the need for external components. If a driver to an input will never let the input float, a resistor is not needed. If an output in the
P port is configured as a push-pull output there is no need for external pull-up resistors. If an output in the P port is configured
as an open-drain output, external pull-up resistors are required.
Fig 13. Typical application
8.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 13. Since the LED acts as a diode, when the LED is off the I/O
VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower
than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 14 shows a high value resistor in parallel with the LED. Figure 15 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI
at or above VDD and prevents additional supply current consumption when the LED is off.
PCAL9539A
Product data sheet
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Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
21 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
3.3 V
VDD
VDD
LED
5V
VDD
100 kΩ
LED
Pn
Pn
002aag164
Fig 14. High value resistor in parallel with
the LED
002aag165
Fig 15. Device supplied by a lower voltage
8.2 Output drive strength control
The Output drive strength registers allow the user to control the output drive level of the
GPIO. Each GPIO can be configured independently to one of the four possible output
current levels. By programming these bits the user is changing the number of transistor
pairs or ‘fingers’ that drive the I/O pad.
Figure 16 shows a simplified output stage. The behavior of the pad is affected by the
Configuration register, the output port data, and the current control register. When the
Current Control register bits are programmed to 10b, then only two of the fingers are
active, reducing the current drive capability by 50 %.
PMOS_EN0
VDD
PMOS_EN1
Current Control
register
PMOS_EN[3:0]
DECODER
NMOS_EN[3:0]
PMOS_EN2
Configuration
register
PMOS_EN3
P0_0 to P0_7
P1_0 to P1_7
Output port
register
NMOS_EN3
NMOS_EN2
NMOS_EN1
NMOS_EN0
002aah431
Fig 16. Simplified output stage
PCAL9539A
Product data sheet
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PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Reducing the current drive capability may be desirable to reduce system noise. When the
output switches (transitions from H/L), there is a peak current that is a function of the
output drive selection. This peak current runs through VDD and VSS package inductance
and will create noise (some radiated, but more critically Simultaneous Switching Noise
(SSN)). In other words, switching many outputs at the same time will create ground and
supply noise. The output drive strength control through the Current Control registers
allows the user to mitigate SSN issues without the need of additional external
components.
8.3 Power-on reset requirements
In the event of a glitch or data corruption, PCAL9539A can be reset to its default
conditions by using the power-on reset feature. Power-on reset requires that the device
go through a power cycle to be completely reset. This reset also happens when the device
is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 17 and Figure 18.
VDD
ramp-up
ramp-down
re-ramp-up
td(rst)
time
(dV/dt)r
(dV/dt)f
time to re-ramp
when VDD drops
below 0.2 V or to VSS
(dV/dt)r
002aah329
Fig 17. VDD is lowered below 0.2 V or to 0 V and then ramped up to VDD
VDD
ramp-down
ramp-up
td(rst)
VI drops below POR levels
(dV/dt)f
time to re-ramp
when VDD drops
to VPOR(min) − 50 mV
time
(dV/dt)r
002aah330
Fig 18. VDD is lowered below the POR threshold, then ramped back up to VDD
Table 28 specifies the performance of the power-on reset feature for PCAL9539A for both
types of power-on reset.
PCAL9539A
Product data sheet
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23 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Table 28. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 17
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 17
0.1
-
2000
ms
td(rst)
reset delay time
Figure 17; re-ramp time when
VDD drops below 0.2 V or to VSS
1
-
-
s
Figure 18; re-ramp time when
VDD drops to VPOR(min) 50 mV
1
-
-
s
VDD(gl)
glitch supply voltage difference
Figure 19
[1]
-
-
1
V
[2]
-
-
10
s
tw(gl)VDD
supply voltage glitch pulse width
Figure 19
VPOR(trip)
power-on reset trip voltage
falling VDD
0.7
-
-
V
rising VDD
-
-
1.4
V
[1]
Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2]
Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 19 and Table 28 provide more information on
how to measure these specifications.
VDD
∆VDD(gl)
tw(gl)VDD
time
002aah331
Fig 19. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0 V. Figure 20 and Table 28 provide more details on this specification.
VDD
VPOR (rising VDD)
VPOR (falling VDD)
time
POR
time
002aah332
Fig 20. Power-on reset voltage (VPOR)
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PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
8.4 Device current consumption with internal pull-up and pull-down
resistors
The PCAL9539A integrates programmable pull-up and pull-down resistors to eliminate
external components when pins are configured as inputs and pull-up or pull-down
resistors are required (for example, nothing is driving the inputs to the power supply rails.
Since these pull-up and pull-down resistors are internal to the device itself, they contribute
to the current consumption of the device and must be considered in the overall system
design.
The pull-up or pull-down function is selected in registers 48h and 49h, while the resistor is
connected by the enable registers 46h and 47h. The configuration of the resistors is
shown in Figure 6.
If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow from
the VDD pin through the resistor to ground when the pin is held LOW. This current will
appear as additional IDD upsetting any current consumption measurements.
In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH,
current will flow from the power supply through the pin to the VSS pin. While this current
will not be measured as part of IDD, one must be mindful of the 200 mA limiting value
through VSS.
The pull-up and pull-down resistors are simple resistors and the current is linear with
voltage. The resistance specification for these devices spans from 50 k with a nominal
100 k value. Any current flow through these resistors is additive by the number of pins
held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure 24 for a
graph of supply current versus the number of pull-up resistors.
PCAL9539A
Product data sheet
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PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
9. Limiting values
Table 29. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Max
Unit
0.5
+6.5
V
0.5
+6.5
V
0.5
+6.5
V
VI
input voltage
[1]
VO
output voltage
[1]
IIK
input clamping current
A0, A1, RESET, SCL; VI < 0 V
-
20
mA
IOK
output clamping current
INT; VO < 0 V
-
20
mA
IIOK
input/output clamping current
P port; VO < 0 V or VO > VDD
-
20
mA
SDA; VO < 0 V or VO > VDD
-
20
mA
continuous; I/O port
-
50
mA
continuous; SDA, INT
-
25
mA
continuous; P port
LOW-level output current
IOL
IOH
HIGH-level output current
-
25
mA
IDD
supply current
-
160
mA
ISS
ground supply current
-
200
mA
Ptot
total power dissipation
-
200
mW
Tstg
storage temperature
65
+150
C
Tj(max)
maximum junction temperature
-
125
C
[1]
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
10. Recommended operating conditions
Table 30.
Operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
1.65
5.5
V
VIH
HIGH-level input voltage
SCL, SDA, RESET
0.7 VDD
5.5
V
A0, A1, P1_7 to P0_0
0.7 VDD
5.5
V
VIL
LOW-level input voltage
SCL, SDA, RESET
0.5
0.3 VDD
V
A0, A1, P1_7 to P0_0
0.5
0.3 VDD
V
P1_7 to P0_0
-
10
mA
IOH
HIGH-level output current
IOL
LOW-level output current
P1_7 to P0_0
-
25
mA
Tamb
ambient temperature
operating in free air
40
+85
C
11. Thermal characteristics
Table 31.
Symbol
Zth(j-a)
[1]
Thermal characteristics
Parameter
Conditions
transient thermal impedance from junction to ambient
Max
Unit
TSSOP24 package
[1]
88
K/W
HWQFN24 package
[1]
66
K/W
The package thermal impedance is calculated in accordance with JESD 51-7.
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Product data sheet
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26 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
12. Static characteristics
Table 32. Static characteristics
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1] Max
Unit
VIK
input clamping voltage
II = 18 mA
1.2
-
-
V
VPOR
power-on reset voltage
VI = VDD or VSS; IO = 0 mA
-
1.1
1.4
V
VOH
HIGH-level output voltage[2]
P port; IOH = 8 mA; CCX.X = 11b
VDD = 1.65 V
1.2
-
-
V
VDD = 2.3 V
1.8
-
-
V
VDD = 3 V
2.6
-
-
V
VDD = 4.5 V
4.1
-
-
V
VDD = 1.65 V
1.1
-
-
V
VDD = 2.3 V
1.7
-
-
V
VDD = 3 V
2.5
-
-
V
VDD = 4.5 V
4.0
-
-
V
VDD = 1.65 V
-
-
0.45
V
VDD = 2.3 V
-
-
0.25
V
VDD = 3 V
-
-
0.25
V
VDD = 4.5 V
-
-
0.2
V
VDD = 1.65 V
-
-
0.5
V
VDD = 2.3 V
-
-
0.3
V
VDD = 3 V
-
-
0.25
V
VDD = 4.5 V
-
-
0.2
V
SDA
3
-
-
mA
INT
3
15[3]
-
mA
SCL, SDA, RESET; VI = VDD or VSS
-
-
1
A
A0, A1; VI = VDD or VSS
P port; IOH = 2.5 mA and CCX.X = 00b;
IOH = 5 mA and CCX.X = 01b;
IOH = 7.5 mA and CCX.X = 10b;
IOH = 10 mA and CCX.X = 11b;
VOL
LOW-level output
voltage[2]
P port; IOL = 8 mA; CCX.X = 11b
P port; IOL = 2.5 mA and CCX.X = 00b;
IOL = 5 mA and CCX.X = 01b;
IOL = 7.5 mA and CCX.X = 10b;
IOL = 10 mA and CCX.X = 11b;
IOL
II
LOW-level output current
input current
VOL = 0.4 V; VDD = 1.65 V to 5.5 V
VDD = 1.65 V to 5.5 V
-
-
1
A
IIH
HIGH-level input current
P port; VI = VDD; VDD = 1.65 V to 5.5 V
-
-
1
A
IIL
LOW-level input current
P port; VI = VSS; VDD = 1.65 V to 5.5 V
-
-
1
A
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PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Table 32. Static characteristics …continued
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Min
Typ[1] Max
Unit
VDD = 3.6 V to 5.5 V
-
10
25
A
VDD = 2.3 V to 3.6 V
-
6.5
15
A
VDD = 1.65 V to 2.3 V
-
4
9
A
VDD = 3.6 V to 5.5 V
-
1.5
7
A
VDD = 2.3 V to 3.6 V
-
1
3.2
A
VDD = 1.65 V to 2.3 V
-
0.5
1.7
A
VDD = 3.6 V to 5.5 V
-
60
125
A
VDD = 2.3 V to 3.6 V
-
40
75
A
VDD = 1.65 V to 2.3 V
-
20
45
A
-
1.1
1.5
mA
SCL, SDA, RESET; one input at VDD 0.6 V,
other inputs at VDD or VSS; VDD = 1.65 V to 5.5 V
-
-
25
A
P port, A0, A1; one input at VDD 0.6 V,
other inputs at VDD or VSS; VDD = 1.65 V to 5.5 V
-
-
80
A
Symbol
Parameter
Conditions
IDD
supply current
SDA, P port, A0, A1, RESET;
VI on SDA and RESET = VDD or VSS;
VI on P port and A0, A1 = VDD;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
SCL, SDA, P port, A0, A1, RESET;
VI on SCL, SDA and RESET = VDD or VSS;
VI on P port and A0, A1 = VDD;
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
Active mode; P port, A0, A1, RESET;
VI on RESET = VDD;
VI on P port and A0, A1 = VDD;
IO = 0 mA; I/O = inputs;
fSCL = 400 kHz, continuous register read
with pull-ups enabled; P port, A0, A1, RESET;
VI on SCL, SDA and RESET = VDD or VSS;
VI on P port = VSS; VI on A0, A1 = VDD or VSS;
IO = 0 mA; I/O = inputs with pull-up enabled;
fSCL = 0 kHz
VDD = 1.65 V to 5.5 V
IDD
additional quiescent
supply current[4]
Ci
input capacitance
VI = VDD or VSS; VDD = 1.65 V to 5.5 V
-
6
7
pF
Cio
input/output capacitance
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
-
7
8
pF
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
-
7.5
8.5
pF
Rpu(int)
internal pull-up resistance
input/output
50
100
150
k
Rpd(int)
internal pull-down resistance input/output
50
100
150
k
[1]
For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the
typical values are at VDD = 3.3 V and Tamb = 25 C.
[2]
The total current sourced by all I/Os must be limited to 160 mA.
[3]
Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V.
[4]
Internal pull-up/pull-down resistors disabled.
PCAL9539A
Product data sheet
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28 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
12.1 Typical characteristics
002aah333
20
IDD
(μA)
16
12
002aah334
1400
IDD(stb)
(nA)
VDD = 5.5 V
5.0 V
3.6 V
3.3 V
2.5 V
2.3 V
VDD = 5.5 V
5.0 V
3.6 V
3.3 V
1000
800
600
8
400
2.5 V
2.3 V
1.8 V
1.65 V
4
0
−40
200
VDD = 1.8 V
1.65 V
−15
10
35
0
−40
60
85
Tamb (°C)
Fig 21. Supply current versus ambient temperature
002aah335
20
IDD
(μA)
16
−15
10
35
60
85
Tamb (°C)
Fig 22. Standby supply current versus
ambient temperature
002aah336
1.2
Tamb = −40 °C
25 °C
85 °C
IDD
(mA)
0.8
12
8
0.4
4
0
1.5
0
2.5
3.5
4.5
5.5
0
VDD (V)
Tamb = 25 C
Product data sheet
8
12
16
number of I/O held LOW
VDD = 5 V
Fig 23. Supply current versus supply voltage
PCAL9539A
4
Fig 24. Supply current versus number of I/O held LOW
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29 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Isink
(mA)
002aaf578
35
Isink
(mA)
30
Tamb = −40 °C
25 °C
85 °C
25
002aaf579
35
30
Tamb = −40 °C
25 °C
85 °C
25
20
20
15
15
10
10
5
5
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
a. VDD = 1.65 V
Isink
(mA)
b. VDD = 1.8 V
002aaf580
50
002aaf581
60
Isink
(mA)
40
Tamb = −40 °C
25 °C
85 °C
30
0.3
VOL (V)
Tamb = −40 °C
25 °C
85 °C
40
20
20
10
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
c. VDD = 2.5 V
Isink
(mA)
0.3
VOL (V)
d. VDD = 3.3 V
002aaf582
70
Isink
(mA)
Tamb = −40 °C
25 °C
85 °C
60
50
002aaf583
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
40
30
30
20
20
10
10
0
0
0
0.1
0.2
0.3
0
VOL (V)
e. VDD = 5.0 V
0.1
0.2
0.3
VOL (V)
f. VDD = 5.5 V
Fig 25. I/O sink current versus LOW-level output voltage with CCX.X = 11b
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Product data sheet
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30 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
002aah110
30
Isource
(mA)
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
20
002aah111
35
Tamb = −40 °C
25 °C
85 °C
30
25
20
15
10
10
5
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
a. VDD = 1.65 V
0
002aah112
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
40
0.4
0.6
VDD − VOH (V)
b. VDD = 1.8 V
60
Isource
(mA)
0.2
002aah113
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
30
20
20
10
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
c. VDD = 2.5 V
002aah114
0.4
0.6
VDD − VOH (V)
002aah115
90
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
60
0.2
d. VDD = 3.3 V
90
Isource
(mA)
0
Tamb = −40 °C
25 °C
85 °C
60
30
30
0
0
0
e. VDD = 5.0 V
0.2
0.4
0.6
VDD − VOH (V)
0
0.2
0.4
0.6
VDD − VOH (V)
f. VDD = 5.5 V
Fig 26. I/O source current versus HIGH-level output voltage with CCX.X = 11b
PCAL9539A
Product data sheet
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31 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
VOL
(mV)
002aah056
120
100
002aah343
200
VDD − VOH (mV)
160
(1)
80
120
VDD = 1.8 V
5V
60
(2)
80
40
(4)
20
0
−40
40
(3)
−15
10
35
60
85
Tamb (°C)
0
−40
−15
10
35
60
85
Tamb (°C)
Isource = 10 mA
(1) VDD = 1.8 V; Isink = 10 mA
(2) VDD = 5 V; Isink = 10 mA
(3) VDD = 1.8 V; Isink = 1 mA
(4) VDD = 5 V; Isink = 1 mA
Fig 27. LOW-level output voltage versus temperature
PCAL9539A
Product data sheet
Fig 28. I/O high voltage versus temperature
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PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
13. Dynamic characteristics
Table 33. I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 29.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
tHIGH
HIGH period of the SCL clock
4
-
0.6
-
s
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tSP
pulse width of spikes that must
be suppressed by the input filter
0
50
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
-
ns
kHz
tr
rise time of both SDA and SCL signals
-
1000
20
300
ns
tf
fall time of both SDA and SCL signals
-
300
20
(VDD / 5.5 V)
300
ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tHD;STA
hold time (repeated) START condition
4
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4
-
0.6
-
s
tVD;DAT
data valid time
SCL LOW to
SDA output valid
-
3.45
-
0.9
s
tVD;ACK
data valid acknowledge time
ACK signal
from SCL LOW
to SDA (out) LOW
-
3.45
-
0.9
s
Table 34. Reset timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 31.
Symbol
Parameter
tw(rst)
reset pulse width
trec(rst)
reset recovery time
trst
reset time
[1]
Conditions
Standard-mode
I2C-bus
[1]
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
30
-
30
-
ns
200
-
200
-
ns
600
-
600
-
ns
Minimum time for SDA to become HIGH or minimum time to wait before doing a START.
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Table 35. Switching characteristics
Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 29.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Min
Max
Min
Max
Unit
tv(INT)
valid time on pin INT
from P port to INT
-
1
-
1
s
trst(INT)
reset time on pin INT
from SCL to INT
-
1
-
1
s
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
ns
14. Parameter measurement information
VDD
RL = 1 kΩ
DUT
SDA
CL = 50 pF
002aag803
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
STOP
condition
(P)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VDD
0.3 × VDD
SCL
tBUF
tVD;DAT
tr
tf
tf(o)
tVD;ACK
tSU;STA
0.7 × VDD
SDA
tf
tHD;STA
tr
0.3 × VDD
tVD;ACK
tSU;DAT
tSU;STO
tHD;DAT
repeat START condition
STOP condition
002aag804
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
(1) See Figure 9.
Fig 29. I2C-bus interface load circuit and voltage waveforms
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
VDD
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
002aah069
a. Interrupt load configuration
acknowledge
from slave
START condition
R/W
8 bits (one data byte)
from port
slave address
SDA S
SCL
1
1
1
1
2
3
0
4
1 A1 A0 1
5
6
7
8
acknowledge
from slave
DATA 1
A
no acknowledge
from master
STOP
condition
data from port
A
DATA 2
1
P
9
B
trst(INT) B
trst(INT)
INT
tv(INT)
data into
port
A
A
tsu(D)
ADDRESS
INT
DATA 1
SCL
0.5 × VDD
DATA 2
R/W
0.3 × VDD
tv(INT)
trst(INT)
0.5 × VDD
Pn
0.7 × VDD
A
0.5 × VDD
INT
View A - A
View B - B
002aah070
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Fig 30. Interrupt load circuit and voltage waveforms
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
500 Ω
Pn
DUT
2 × VDD
CL = 50 pF
500 Ω
002aag805
a. P port load configuration
SCL
P0
A
P7
0.7 × VDD
0.3 × VDD
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
002aag806
b. Write mode (R/W = 0)
SCL
P0
0.7 × VDD
0.3 × VDD
tsu(D)
th(D)
Pn
002aag807
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 31. P port load circuit and voltage waveforms
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
VDD
RL = 1 kΩ
SDA
DUT
500 Ω
Pn
DUT
CL = 50 pF
2 × VDD
CL = 50 pF
500 Ω
002aag803
002aag805
a. SDA load configuration
b. P port load configuration
START
SCL
ACK or read cycle
SDA
0.3 × VDD
trst
RESET
0.5 × VDD
trec(rst)
tw(rst)
trec(rst)
trst
Pn
0.5 × VDD
002aah073
c. RESET timing
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
Fig 32. Reset load circuits and voltage waveforms
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
15. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 33. Package outline SOT355-1 (TSSOP24)
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PCAL9539A
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.75 mm
B
D
SOT994-1
A
terminal 1
index area
E
A
A1
c
detail X
e1
1/2 e
∅v
∅w
b
e
7
12
M
M
C
C A B
C
y1 C
y
L
13
6
e
e2
Eh
1/2 e
1
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
b
c
D(1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
0.8
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT994-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
07-02-07
07-03-03
Fig 34. Package outline SOT994-1 (HWQFN24)
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 35) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 36 and 37
Table 36.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 37.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 35.
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 35. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
18. Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP24 package
SOT355-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
8.200
5.300
8.600
7.450
sot355-1_fr
Fig 36. PCB footprint for SOT355-1 (TSSOP24); reflow soldering
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Footprint information for reflow soldering of HVQFN24 package
SOT994-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
nSPx
Hy
SPy tot
SPy
Gy
SLy
nSPy
By
Ay
SPx tot
SLx
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
SPx tot
SPy tot
SPx
SPy
Gx
Gy
Hx
Hy
0.500
5.000
5.000
3.200
3.200
0.900
0.240
2.100
2.100
1.200
1.200
0.450
0.450
4.300
4.300
5.250
5.250
Issue date
07-09-24
09-06-15
sot994-1_fr
Fig 37. PCB footprint for SOT994-1 (HWQFN24); reflow soldering
PCAL9539A
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
19. Abbreviations
Table 38.
Abbreviations
Acronym
Description
ACPI
Advanced Configuration and Power Interface
CBT
Cross-Bar Technology
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
FF
Flip-Flop
GPIO
General Purpose Input/Output
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
PCB
Printed-Circuit Board
POR
Power-On Reset
PRR
Pulse Repetition Rate
SMBus
System Management Bus
20. Revision history
Table 39.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCAL9539A v.1
20121003
Product data sheet
-
-
PCAL9539A
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCAL9539A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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PCAL9539A
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCAL9539A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
47 of 48
PCAL9539A
NXP Semiconductors
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
23. Contents
1
2
2.1
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pointer register and command byte . . . . . . . . . 5
Input port register pair (00h, 01h) . . . . . . . . . . . 7
Output port register pair (02h, 03h) . . . . . . . . . 7
Polarity inversion register pair (04h, 05h) . . . . . 8
Configuration register pair (06h, 07h) . . . . . . . . 8
Output drive strength register pairs
(40h, 41h, 42h, 43h) . . . . . . . . . . . . . . . . . . . . . 9
6.2.7
Input latch register pair (44h, 45h) . . . . . . . . . . 9
6.2.8
Pull-up/pull-down enable register pair
(46h, 47h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2.9
Pull-up/pull-down selection register pair
(48h, 49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2.10
Interrupt mask register pair (4Ah, 4Bh). . . . . . 11
6.2.11
Interrupt status register pair (4Ch, 4Dh) . . . . . 12
6.2.12
Output port configuration register (4Fh) . . . . . 12
6.3
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5
RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.6
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
Writing to the port registers. . . . . . . . . . . . . . . 15
7.2
Reading the port registers . . . . . . . . . . . . . . . 17
8
Application design-in information . . . . . . . . . 21
8.1
Minimizing IDD when the I/Os are used to
control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2
Output drive strength control . . . . . . . . . . . . . 22
8.3
Power-on reset requirements . . . . . . . . . . . . . 23
8.4
Device current consumption with internal
pull-up and pull-down resistors . . . . . . . . . . . . 25
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26
10
Recommended operating conditions. . . . . . . 26
11
Thermal characteristics . . . . . . . . . . . . . . . . . 26
12
Static characteristics. . . . . . . . . . . . . . . . . . . . 27
12.1
13
14
15
16
17
17.1
17.2
17.3
17.4
18
19
20
21
21.1
21.2
21.3
21.4
22
23
Typical characteristics . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Parameter measurement information . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering: PCB footprints . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
33
34
38
40
40
40
40
40
41
43
45
45
46
46
46
46
47
47
48
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 October 2012
Document identifier: PCAL9539A
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湘ICP备2023018690号
