PCF85263AUKZ

PCF85263A Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, 2 and I C-bus Rev. 5.3 — 22 November 2023 Product data sheet 1 General description 1 The PCF85263A is a CMOS Real-Time Clock (RTC) and calendar optimized for low power consumption and with automatic switching to battery on main power loss. The RTC can also be configured as a stop-watch (elapsed time counter). Three time log registers triggered from battery switch-over as well as input driven 2 events. Featuring clock output and two independent interrupt signals, two alarms, I C-bus interface and quartz crystal calibration. For a selection of NXP Real-Time Clocks, see Table 71. 2 Features and benefits • UL Recognized Component (PCF85263ATL) • Provides year, month, day, weekday, hours, minutes, seconds and 100th seconds based on a 32.768 kHz quartz crystal • Stop-watch mode for elapsed time counting. From 100th seconds to 999 999 hours • Two independent alarms • Battery back-up circuit • WatchDog timer • Three timestamp registers • Two independent interrupt generators plus predefined interrupts at every second, minute, or hour • Frequency adjustment via programmable offset register • Clock operating voltage: 0.9 V to 5.5 V • Low current; typical 0.28 μA at VDD = 3.0 V and Tamb = 25 °C 2 • 400 kHz two-line I C-bus interface (at VDD = 1.8 V to 5.5 V) • Programmable clock output for peripheral devices (32.768 kHz, 16.384 kHz, 8.192 kHz, 4.096 kHz, 2.048 kHz, 1.024 kHz, and 1 Hz) • Configurable oscillator circuit for a wide variety of quartzes: CL = 6 pF, CL = 7 pF, and CL = 12.5 pF • Packages offered: SI8, TSSOP8, TSSOP10, HXSON10 and WLCSP12 3 Applications • • • • Printers and copiers Electronic metering Digital cameras White goods 1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 23. PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus • • • • • • • Elapsed time counter Network powered devices Battery backed up systems Data loggers Digital voice recorders Mobile equipment Accurate high duration timer 4 Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PCF85263AT/A 85263A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCF85263ATL/A 263A DFN2626-10 plastic thermal enhanced extremely thin small outline package; no leads; 10 terminals; body 2.6 × 2.6 × 0.5 mm SOT1197-1 PCF85263ATT/A 263A TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 PCF85263ATT1/A 263A TSSOP10 plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1 PCF85263AUK F WLCSP12 wafer level package 12 cu pillars; body 1.19 x 0.94 x 0.22 mm with 0.25 mm pitch SOT2035-1 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method PCF85263AT/A PCF85263AT/AJ SO8 PCF85263ATL/A PCF85263ATL/AX PCF85263ATT/A PCF85263ATT/AJ Minimum order quantity Temperature Reel 13" Q1 NDP 2500 Tamb = -40 °C to +85 °C DFN2626-10 Reel 7" Q1 NDP 4000 Tamb = -40 °C to +85 °C TSSOP8 Reel 13" Q1 NDP 2500 Tamb = -40 °C to +85 °C TSSOP10 Reel 13" Q1 NDP 2500 Tamb = -40 °C to +85 °C PCF85263ATT1/AZ TSSOP10 Reel 13" Q1 NDP [3] SSB 2500 Tamb = -40 °C to +85 °C PCF85263AUKZ WLCSP12 Reel 13" Q1 Dry Pack 20000 Tamb = -40 °C to +85 °C PCF85263ATT1/A PCF85263ATT1/AJ PCF85263AUK [1] [2] [3] [1] [2] Standard packing quantities and other packaging data are available at www.nxp.com/packages/ Discontinuation Notice 202104010DN; drop in replacement is PCF85263ATT1/AZ. Refer to PCN 202104008A. This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 2 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 5 Block diagram Alarm control 100TH seconds 1 byte RAM Seconds Minutes RTC Stopwatch Hours Hours xxxx00 Weekdays Hours xx00xx Days Hours 00xxxx Months - Years - Alarm 1 Alarm 2 I2C interface Time stamp 1 Time stamp 2 Time stamp 3 SDA SCL Time stamp control VSS VDD(int) Mechanical switch detec. VDD Stopwatch control batt_mode VDD VBAT VBAT/VTH VDD(int) Battery switch over TS (1) (CLK/INTB) batt_mode Pulse/ level Interrupt generation Alarms Time stamps Periodic interrupt Offset calibration WatchDog Battery mode INTA (CLK) Pulse/ level Interrupt generation CLK (1) OSCI OSCO 32768 Hz quartz oscillator CLK generation PCF85263A Offset calibration WatchDog aaa-009062 1. Not available on all package types. Figure 1. Block diagram of PCF85263A PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 3 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 6 Pinning information 6.1 Pinning PCF85263AT OSCI 1 8 VDD OSCO 2 7 INTA(CLK) VBAT 3 6 SCL VSS 4 5 SDA aaa-009079 For mechanical details, see Figure 45. Figure 2. Pin configuration for PCF85263AT (SO8) terminal 1 index area OSCI 1 10 VDD OSCO 2 VBAT 3 9 INTA (CLK) PCF85263ATL 8 CLK TS (CLK/INTB) 4 7 SCL VSS 5 6 SDA aaa-009081 Transparent top view For mechanical details, see Figure 46. Figure 3. Pin configuration for PCF85263ATL (DFN2626-10) OSCI 1 OSCO 2 VBAT 3 8 VDD PCF85263ATT VSS 4 7 INTA(CLK) 6 SCL 5 SDA aaa-011437 For mechanical details, see Figure 47. Figure 4. Pin configuration for PCF85263ATT (TSSOP8) PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 4 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus OSCI 1 10 VDD OSCO 2 9 INTA (CLK) PCF85263ATT1 VBAT 3 8 CLK TS (CLK/INTB) 4 7 SCL VSS 5 6 SDA aaa-009082 For mechanical details, see Figure 48. Figure 5. Pin configuration for PCF85263ATT1 (TSSOP10) PCF85263AUK 1 2 3 A B C D Transparent top view aaa-032284 For mechanical details, see Figure 49. Figure 6. Pin configuration for PCF85263AUK (WLCSP12) 6.2 Pin description Table 3. Pin description Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Symbol Pin Type PCF85263AT (SO8) PCF85263ATL (DFN2626-10) PCF85263ATT (TSSOP8) PCF85263ATT1 (TSSOP10) PCF85263AUK (WLCSP12) OSCI 1 1 1 1 A2 OSCO 2 2 2 2 A3 VBAT 3 3 3 3 TS (CLK/INTB) - 4 - 4 [3] Description Primary use Secondary use input oscillator input - output oscillator output - B3 supply battery backup supply [1] voltage - C3 input/ output can be configured with TSPM[1:0] timestamp input [2] INTB and CLK output (push-pull); stop-watch control VSS 4 5 4 5 D2, D3 supply ground supply voltage - SDA 5 6 5 6 D1 input/ output serial data line - SCL 6 7 6 7 C1 input serial clock input - CLK - 8 - 8 B2 output CLK (push-pull) - INTA (CLK) 7 9 7 9 B1 output can be configured with INTAPM[1:0] interrupt output (open-drain) VDD 8 PCF85263A Product data sheet 10 8 10 A1, C2 supply All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 supply voltage [4] CLK output (opendrain) - © 2023 NXP B.V. All rights reserved. 5 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus [1] [2] [3] [4] Connect to VDD if not used. See Table 6 and Table 46. The die paddle (exposed pad) is connected to VSS through high ohmic (non-conductive) silicon attach and should be electrically isolated. It is good engineering practice to solder the exposed pad to an electrically isolated PCB copper pad as shown in Figure 46 for better heat transfer but it is not required as the RTC doesn’t consume much power. In no case should traces be run under the package exposed pad. See Table 6 and Table 48. 7 Functional description The PCF85263A contains 8-bit registers for time information, for timestamp information and registers for system configuration. Included is an auto-incrementing register address, an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which provides the source clock for the Real-Time Clock (RTC) and 2 calender, and an I C-bus interface with a maximum data rate of 400 kbit/s. The built-in address register will increment automatically after each read or write of a data byte. After register 2Fh, the auto-incrementing will wrap around to address 00h (see Figure 7). address register 00h 01h auto-increment 02h 03h ... 2Dh 2Eh 2Fh wrap around aaa-009084 Figure 7. Address register incrementing All registers (see Table 4, Table 5, and Table 6) are designed as addressable 8-bit parallel registers although not all bits are implemented. Figure 8 gives an overview of the address map. : Time registers 00h : 07h : Alarm registers 08h : 10h : : : 11h Timestamp registers : : 23h Offset register 24h : 25h Function setting : : 2Bh RAM byte 2Ch Watchdog 2Dh Stop and reset 2Eh 2Fh aaa-009114 Figure 8. Register map PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 6 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus The 100th seconds, seconds, minutes, hours, days, months, and years as well as the corresponding alarm registers are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is read, the contents of all time counters are frozen. Therefore, faulty reading of the clock and calendar during a carry condition is prevented. 7.1 Registers organization overview 7.1.1 Time mode registers The PCF85263A has two time mode register sets, one for the real-time clock mode and one for the stopwatch clock mode. The access to these registers can be switched by the RTCM bit in the Function control register (28h), see Table 6 and Table 53. real-time clock mode register set 0 RTCM 1 stopwatch mode register set aaa-009600 Figure 9. Time mode register set selection 7.1.1.1 RTC mode time registers overview (RTCM = 0) Table 4. RTC mode time registers Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61. Address Register name Bit 7 Reference 6 5 4 3 2 1 0 RTC time and date registers 00h 100th_seconds 100TH_SECONDS (0 to 99) 01h Seconds OS SECONDS (0 to 59) Section 7.2 02h Minutes EMON MINUTES (0 to 59) 03h Hours - - AMPM HOURS (1 to 12) in 12 hour mode HOURS (0 to 23) in 24 hour mode 04h Days - - DAYS (1 to 31) 05h Weekdays - - - - 06h Months - - - MONTHS (1 to 12) 07h Years YEARS (0 to 99) 08h Second_alarm1 - SEC_ALARM1 (0 to 59) 09h Minute_alarm1 - MIN_ALARM1 (0 to 59) 0Ah Hour_alarm1 - - - WEEKDAYS (0 to 6) RTC alarm1 AMPM Section 7.4 HR_ALARM1 (1 to 12) in 12 hour mode HR_ALARM1 (0 to 23) in 24 hour mode 0Bh Day_alarm1 - - DAY_ALARM1 (1 to 31) 0Ch Month_alarm1 - - - Minute_alarm2 - MIN_ALARM2 (0 to 59) MON_ALARM1 (1 to 12) RTC alarm2 0Dh PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 Section 7.4 © 2023 NXP B.V. All rights reserved. 7 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 4. RTC mode time registers...continued Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61. Address Register name Bit Reference 7 6 5 4 3 2 1 0 0Eh Hour_alarm2 - - AMPM HR_ALARM2 (1 to 12) in 12 hour mode 0Fh Weekday_alarm2 - - - - - WDAY_ALARM2 (0 to 6) WDAY_A2E HR_A2E MIN_A2E MON_A1E DAY_A1E HR_A1E RTC alarm enables 10h Alarm_enables MIN__A1E SEC__A1E Section 7.4 RTC timestamp1 (TSR1) 11h TSR1_seconds - TSR1_SECONDS (0 to 59) 12h TSR1_minutes - TSR1_MINUTES (0 to 59) 13h TSR1_hours - - AMPM Section 7.7 TSR1_HOURS (1 to 12) in 12 hour mode TSR1_HOURS (0 to 23) in 24 hour mode 14h TSR1_days - - TSR1_DAYS (1 to 31) 15h TSR1_months - - - 16h TSR1_years TSR1_YEARS (0 to 99) TSR1_MONTHS (1 to 12) RTC timestamp2 (TSR2) 17h TSR2_seconds - TSR2_SECONDS (0 to 59) 18h TSR2_minutes - TSR2_MINUTES (0 to 59) 19h TSR2_hours - - AMPM Section 7.7 TSR2_HOURS (1 to 12) in 12 hour mode TSR2_HOURS (0 to 23) in 24 hour mode 1Ah TSR2_days - - TSR2_DAYS (1 to 31) 1Bh TSR2_months - - - 1Ch TSR2_years TSR2_YEARS (0 to 99) TSR2_MONTHS (1 to 12) RTC timestamp3 (TSR3) 1Dh TSR3_seconds - TSR3_SECONDS (0 to 59) 1Eh TSR3_minutes - TSR3_MINUTES (0 to 59) 1Fh TSR3_hours - - AMPM Section 7.7 TSR3_HOURS (1 to 12) in 12 hour mode TSR3_HOURS (0 to 23) in 24 hour mode 20h TSR3_days - - TSR3_DAYS (1 to 31) 21h TSR3_months - - - TSR3_MONTHS (1 to 12) 22h TSR3_years TSR3_YEARS (0 to 99) - TSR2M[2:0] RTC timestamp mode control 23h TSR_mode TSR3M[1:0] TSR1M[1:0] Section 7.7 7.1.1.2 Stop-watch mode time registers (RTCM = 1) Table 5. Stop-watch mode time registers Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61. Address Register name Bit 7 Reference 6 5 4 3 2 1 0 Stop-watch time registers 00h 100th_seconds 100TH_SECONDS (0 to 99) 01h Seconds OS SECONDS (0 to 59) Section 7.3 02h Minutes EMON MINUTES (0 to 59) 03h Hours_xx_xx_00 HR_XX_XX_00 (0 to 99) 04h Hours_xx_00_xx HR_XX_00_XX (0 to 99) 05h Hours_00_xx_xx HR_00_XX_XX (0 to 99) 06h not used - - - - - - - - 07h not used - - - - - - - - Stop-watch alarm1 08h Second_alm1 - SEC_ALM1 (0 to 59) 09h Minute_alm1 - MIN_ALM1 (0 to 59) PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 Section 7.4 © 2023 NXP B.V. All rights reserved. 8 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 5. Stop-watch mode time registers...continued Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61. Address Register name Bit Reference 7 6 5 0Ah Hr_xx_xx_00_alm1 HR_XX_XX_00_ALM1 (0 to 99) 0Bh Hr_xx_00_xx_alm1 HR_XX_00_XX_ALM1 (0 to 99) 0Ch Hr_00_xx_xx_alm1 HR_00_XX_XX_ALM1 (0 to 99) 4 3 2 1 0 Stop-watch alarm2 MIN_ALM2 (0 to 59) 0Dh Minute_alm2 - 0Eh Hr_xx_00_alm2 HR_XX_00_ALM2 (0 to 99) 0Fh Hr_00_xx_alm2 HR_00_XX_ALM2 (0 to 99) Section 7.4 Stop-watch alarm enables 10h Alarm_enables HR_00_XX_ A2E HR_XX_00_ A2E MIN_A2E HR_00_XX_ XX_A1E HR_XX_00_ XX_A1E HR_XX_XX_ 00_A1E MIN_A1E SEC_A1E Section 7.4 Stop-watch timestamp1 (TSR1) 11h TSR1_seconds - TSR1_SECONDS (0 to 59) 12h TSR1_minutes - TSR1_MINUTES (0 to 59) 13h TSR1_hr_xx_xx_00 TSR1_HR_XX_XX_00 (0 to 99) 14h TSR1_hr_xx_00_xx TSR1_HR_XX_00_XX (0 to 99) 15h TSR1_hr_00_xx_xx TSR1_HR_00_XX_XX (0 to 99) 16h not used - - Section 7.7 - - - - - - Stop-watch timestamp2 (TSR2) 17h TSR2_seconds - TSR2_SECONDS (0 to 59) 18h TSR2_minutes - TSR2_MINUTES (0 to 59) 19h TSR2_hr_xx_xx_00 TSR2_HR_XX_XX_00 (0 to 99) 1Ah TSR2_hr_xx_00_xx TSR2_HR_XX_00_XX (0 to 99) 1Bh TSR2_hr_00_xx_xx TSR2_HR_00_XX_XX (0 to 99) 1Ch not used - - Section 7.7 - - - - - - Stop-watch timestamp3 (TSR3) 1Dh TSR3_seconds - TSR3_SECONDS (0 to 59) 1Eh TSR3_minutes - TSR3_MINUTES (0 to 59) 1Fh TSR3_hr_xx_xx_00 TSR3_HR_XX_XX_00 (0 to 99) 20h TSR3_hr_xx_00_xx TSR3_HR_XX_00_XX (0 to 99) 21h TSR3_hr_00_xx_xx TSR3_HR_00_XX_XX (0 to 99) 22h not used - - Section 7.7 - - - TSR2M[2:0] - - - - Stop-watch timestamp mode control 23h TSR3M[1:0] TSR_mode TSR1M[1:0] Section 7.7 7.1.2 Control registers overview Table 6. Control and function registers overview Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61. Address Register name Bit 7 Reference 6 5 4 3 2 1 0 Offset register 24h Offset OFFSET[7:0] Section 7.8 Control registers 25h Oscillator CLKIV OFFM 12_24 LOWJ OSCD[1:0] 26h Battery_switch - - - BSOFF BSRR 27h Pin_IO CLKPM TSPULL TSL TSIM TSPM[1:0] 28h Function 100TH PI[1:0] RTCM STOPM COF[2:0] 29h INTA_enable ILPA PIEA OIEA A1IEA A2IEA TSRIEA BSIEA WDIEA Section 7.9 2Ah INTB_enable ILPB PIEB OIEB A1IEB A2IEB TSRIEB BSIEB WDIEB Section 7.9 2Bh Flags PIF A2F A1F WDF BSF TSR3F TSR2F TSR1F Section 7.14 PCF85263A Product data sheet CL[1:0] BSM[1:0] INTAPM[1:0] All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 Section 7.10 BSTH Section 7.11 Section 7.12 Section 7.13 © 2023 NXP B.V. All rights reserved. 9 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 6. Control and function registers overview...continued Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61. Address Register name Bit Reference 7 6 5 4 3 2 1 0 RAM byte 2Ch B[7:0] RAM_byte Section 7.6 WatchDog registers 2Dh WatchDog WDM WDR[4:0] Stop_enable - - WDS[1:0] Section 7.5 Stop 2Eh - - - - - STOP Section 7.16 Reset 2Fh Resets CPR 0 1 0 SR 1 0 CTS Section 7.15 7.2 RTC mode time and date registers RTC mode is enabled by setting RTCM = 0. These registers are coded in the BCD format to simplify application use. Default state is: Time: 00:00:00.00 Date: 2000 01 01 Weekday: Saturday Monitor bits: OS = 1, EMON = 0 Table 7. Time and date registers in RTC mode (RTCM = 0) Bit positions labeled as - are not implemented and return 0 when read. Address Register name Upper-digit (ten’s place) Bit 7 [1] Bit 6 Bit 5 Digit (unit place) Bit 4 Bit 3 00h 100th_seconds 01h Seconds OS 0 to 5 0 to 9 02h Minutes EMON 0 to 5 0 to 9 - - 03h Hours 04h Days 05h [2] [3] 0 to 9 AMPM 0 to 1 Bit 0 0 to 9 0 to 2 0 to 9 0 to 9 - 0 to 3 Weekdays - - - - - 06h Months - - - 0 to 1 0 to 9 07h Years 0 to 9 [2] [3] Bit 1 0 to 9 - [1] Bit 2 0 to 6 0 to 9 The 100th_seconds register is only available when the 100TH mode is enabled, see Section 7.13.1. When the 100TH mode is disabled, this register always returns 0. Hour mode is set by the 12_24 bit in the Oscillator register, see Section 7.10. If the year counter contains a value, which is exactly divisible by 4, the PCF85263A compensates for leap years by adding a 29th day to February. 7.2.1 Definition of BCD The Binary-Coded Decimal (BCD) is an encoding of numbers where each digit is represented by a separate bit field. Each bit field may only contain the values 0 to 9. In this way, decimal numbers and counting is implemented. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 10 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Example: 59 encoded as an entire number is represented by 3Bh or 11 1011. In BCD the 5 is represented as 5h or 0101 and the 9 as 9h or 1001 which combines to 59h. Table 8. BCD coding Value in decimal Upper-digit (ten’s place) Digit (unit place) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 0 01 0 0 0 1 0 0 0 1 02 0 0 1 0 0 0 1 0 : : : : : : : : : 09 1 0 0 1 1 0 0 1 10 0 0 0 0 0 0 0 0 : : : : : : : : : 98 1 0 0 1 1 0 0 0 99 1 0 0 1 1 0 0 1 7.2.2 OS: Oscillator stop When the oscillator of the PCF85263A is stopped, the OS status bit is set. The oscillator can be stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to ground. The oscillator is considered to be stopped during the time between power-on and stable crystal resonance. This time can be in the range of 200 ms to 2 s depending on crystal type, temperature, and supply voltage. The status bit remains set until cleared by command (see Figure 10). If the bit cannot be cleared, then the oscillator is not running. This method can be used to monitor the oscillator and to determine if the supply voltage has reduced to the point where oscillation fails. OS = 1 and bit can not be cleared OS = 1 and bit can be cleared VDD oscillation OS flag OS bit cleared by software oscillation now stable OS bit set when oscillation stops t aaa-009576 Figure 10. OS status bit 7.2.3 EMON: event monitor The EMON can be used to monitor the status of all the flags in the Flags register, see Section 7.14. When one or more of the flags is set, then the EMON bit returns a logic 1. The EMON bit cannot be cleared. EMON returns a logic 0 when all flags are cleared. See Figure 23 for a pictorial representation. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 11 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 7.2.4 Definition of weekdays Definition may be reassigned by the user. Table 9. Weekday assignments Day Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 7.2.5 Definition of months Table 10. Month assignments in BCD format Month Upper-digit (ten’s Digit (unit place) place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 7.2.6 Setting and reading the time in RTC mode Figure 11 shows the data flow and data dependencies starting from the 100 Hz clock tick. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 12 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 100 Hz tick 100TH_SECOND 1 Hz tick 100TH SECONDS MINUTES 12_24 LEAP YEAR CALCULATION HOURS DAYS WEEKDAY MONTHS YEARS aaa-009580 Figure 11. Data flow for the time function During read operations, the time counting circuits (memory locations 00h through 07h) are copied into an output register. The RTC continues counting in the background. When reading or writing the time it is very important to make a read or write access in one go, that is, setting or reading 100th seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted. As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time increments between the two accesses. A similar problem exists when reading. A roll-over may occur between reads thus giving the minutes from one moment and the hours from the next. Before setting the time, the STOP bit should be set and the prescalers should be cleared (see Section 7.16). An example of setting the time: 14 hours, 23 minutes and 19 seconds. • • • • • • • • • • • • 2 I C START condition 2 I C target address + write (A2h) register address (2Eh) write data (set STOP, 01h) write data (clear prescaler, A4h) write data (100th seconds, 00h) write data (Hours, 14h) write data (Minutes, 23h) write data (Seconds, 19h) 2 I C START condition 2 I C target address + write (A2h) register address (2Eh) PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 13 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus • write data (clear STOP, 00h). Time starts counting from this point 2 • I C STOP condition 7.3 Stop-watch mode time registers These registers are coded in the BCD format to simplify application use. Stop-watch mode is enabled by setting RTCM = 1. In stop-watch mode, the PCF85263A counts from 100th seconds to 99 9 999 hours. There are no days, weekdays, months or year registers. Default state is: Time 00 00 00:00:00.00 Monitor bits OS = 1, EMON = 0 (see Section 7.2.2 and Section 7.2.3) Table 11. Time registers in stop-watch mode (RTCM = 1) Bit positions labeled as - are not implemented and return 0 when read. Address Register name Upper-digit (ten’s place) Bit 7 [1] Bit 6 Bit 5 Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h 100th_seconds 01h Seconds OS 0 to 5 0 to 9 02h Minutes EMON 0 to 5 0 to 9 03h Hours_xx_xx_00 0 to 9 0 to 9 04h Hours_xx_00_xx 0 to 9 0 to 9 05h Hours_00_xx_xx 0 to 9 0 to 9 06h not used - - - - - - - - 07h not used - - - - - - - - [1] 0 to 9 0 to 9 The 100th_seconds register is only available when the 100TH mode is enabled, see Section 7.13.1. When the 100TH mode is disabled, this register always returns 0. 7.3.1 Setting and reading the time in stop-watch mode Figure 12 shows the data flow and data dependencies starting from the 100 Hz clock tick. During read operations, the time counting circuits (memory locations 00h through 07h) are copied into an output register. The RTC continues counting in the background. When reading or writing the time it is very important to make a read or write access in one go, that is, setting or reading 100th_seconds through to HR_00_xx_xx should be made in one single access. Failing to comply with this method could result in the time becoming corrupted. As an example, if the seconds value is set in one access and then in a following access the minutes value is set, it is possible that the time increments between the two accesses. A similar problem exists when reading. A roll-over may occur between reads thus giving the seconds from one moment and the minutes from the next. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 14 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 100 Hz tick 100TH_SECONDS 1 Hz tick 100TH SECONDS MINUTES HR_XX_XX_00 HR_XX_00_XX HR_00_XX_XX aaa-009581 Figure 12. Data flow for the stop-watch function 7.4 Alarms There are two independent alarms. Each is separately configured and may be used to generate an interrupt. In RTC mode, an alarm is configured for time and date. In stop-watch mode when the RTC is functioning as an elapsed time counter, an alarm is configured for time only. 7.4.1 Alarms in RTC mode In RTC mode, Alarm 1 can be configured from seconds to months. Alarm 2 operates on minutes, hours and weekday. Each segment of the time is independently enabled. Alarms can be output on the INTA and INTB pins. 7.4.1.1 Alarm1 and alarm2 registers in RTC mode Setting the time for alarm1: Only the information which is relevant for the alarm condition must to be programmed. The unused parts are ignored. Table 12. Alarm1 and alarm2 registers in RTC mode coded in BCD (RTCM = 0) Bit positions labeled as - are not implemented. Address Register name Upper-digit (ten’s place) Bit 7 Bit 6 Bit 5 Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTC alarm1 registers 08h Second_alarm1 - 0 to 5 0 to 9 09h Minute_alarm1 - 0 to 5 0 to 9 0Ah Hour_alarm1 - - AMPM 0 to 9 0 to 9 Day_alarm1 - - 0 to 3 0Ch Month_alarm1 - - - Product data sheet 0 to 9 0 to 2 0Bh PCF85263A 0 to 1 0 to 1 0 to 9 All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 15 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 12. Alarm1 and alarm2 registers in RTC mode coded in BCD (RTCM = 0)...continued Bit positions labeled as - are not implemented. Address Register name Upper-digit (ten’s place) Bit 7 Bit 6 Digit (unit place) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTC alarm2 registers 0Dh Minute_alarm2 - 0 to 5 0Eh Hour_alarm2 - - 0 to 9 AMPM 0 to 1 0 to 2 0Fh Weekday_alarm2 - - - 0 to 9 0 to 9 - - 0 to 6 7.4.1.2 Alarm1 and alarm2 control in RTC mode Table 13. Alarm_enables- alarm enable control register (address 10h) bit description Bit Symbol Value Description RTC alarm2 7 weekday alarm2 enable WDAY_A2E 0 [1] 1 6 enabled hour alarm2 enable HR_A2E 0 [1] 1 5 disabled disabled enabled minute alarm2 enable MIN_A2E 0 [1] 1 disabled enabled RTC alarm1 4 month alarm1 enable MON_A1E 0 [1] 1 3 enabled day alarm1 enable DAY_A1E 0 [1] 1 2 hour alarm1 enable [1] 1 minute alarm1 enable [1] 1 second alarm1 enable 0 Product data sheet disabled enabled SEC_A1E PCF85263A disabled enabled MIN_A1E 0 0 disabled enabled HR_A1E 0 1 disabled [1] disabled All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 16 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 13. Alarm_enables- alarm enable control register (address 10h) bit description...continued Bit Symbol Value Description 1 [1] enabled Default value. 7.4.1.3 Alarm1 and alarm2 function in RTC mode The registers at addresses 08h through 0Ch contain alarm1 information. When one or more of these registers is loaded with second, minute, hour, day, or month, and its corresponding alarm enable bit (SEC_A1E to MON_A1E) is set logic 1, then that information is compared with the current second, minute, hour, day, and month. The registers at addresses 0Dh through 0Fh contain alarm2 information. When one or more of these registers is loaded with minute, hour or weekday, and its corresponding alarm enable bit (MIN_A2E to WDAY_A2E) is set logic 1, then that information is compared with the current minute, hour and weekday. Alarm registers which have their alarm enable bit at logic 0 are ignored. When the time increments to match the enabled alarms, the alarm flag in the Flags register (Section 7.14) is set. A1F for alarm1 and A2F for alarm2. The alarm flag is cleared by command. When the time increments to match the enabled alarms, an interrupt can be generated. See Section 7.4.3. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 17 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus example check now signal SEC_A1E SEC_A1E = 0 SECOND ALARM1 = 0 1 SECOND TIME MIN_A1E MINUTE ALARM1 = MINUTE TIME HR_A1E HOUR ALARM1 set alarm flag A1F (1) = HOUR TIME DAY_A1E DAY ALARM1 = DAY TIME MON_A1E MONTH ALARM1 = MONTH TIME example check now signal MIN_A2E MIN_A2E = 0 MINUTE ALARM2 = 0 1 MINUTE TIME HR_A2E HOUR ALARM2 set alarm flag A2F (1) = HOUR TIME WDAY_A2E WEEKDAY ALARM2 = WEEKDAY TIME aaa-009582 1. Only when all enabled alarm settings are matching. The flag is set only on increment to a matched case (and not all the time it is equal). Figure 13. Alarm1 and alarm2 function block diagram (RTC mode) 7.4.2 Alarms in stop-watch mode In stop-watch mode, Alarm 1 can be configured from seconds to 999 999 hours. Alarm 2 operates on minutes up to 9 999 hours. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 18 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 7.4.2.1 Alarm1 and alarm2 registers in stop-watch mode Setting the time for alarm1 and alarm2: Only the information which is relevant for the alarm condition must to be programmed. The unused parts are ignored. Table 14. Alarm1 and alarm2 registers in stop-watch mode coded in BCD (RTCM = 1) Bit positions labeled as - are not implemented. Address Register name Upper-digit (ten’s place) Bit 7 Bit 6 Bit 5 Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Stop-watch alarm1 registers 08h Second_alm1 - 0 to 5 0 to 9 09h Minute_alm1 - 0 to 5 0 to 9 09h Hr_xx_xx_00_alm1 0 to 9 0 to 9 0Bh Hr_xx_00_xx_alm1 0 to 9 0 to 9 0Ch Hr_00_xx_xx_alm1 0 to 9 0 to 9 Stop-watch alarm2 registers 0Dh Minute_alm2 - 0Eh Hr_xx_00_alm2 0 to 9 0 to 9 0Fh Hr_00_xx_alm2 0 to 9 0 to 9 0 to 5 0 to 9 7.4.2.2 Alarm1 and alarm2 control in stop-watch mode Table 15. Alarm_enables- alarm enable control register (address 10h) bit description Bit Symbol Value Description Stop-watch alarm2 7 thousands of hours alarm2 enable HR_00_XX_A2E 0 [1] 1 6 enabled tens of hours alarm2 enable HR_XX_00_A2E 0 [1] 1 5 disabled disabled enabled minute alarm2 enable MIN_A2E 0 [1] 1 disabled enabled Stop-watch alarm1 4 100 thousands of hours alarm1 enable HR_00_XX_XX_A1E 0 [1] 1 3 enabled thousands of hours alarm1 enable HR_XX_00_XX_A1E 0 1 PCF85263A Product data sheet disabled [1] disabled enabled All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 19 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 15. Alarm_enables- alarm enable control register (address 10h) bit description...continued Bit Symbol 2 HR_XX_XX_00_A1E Value tens of hour alarm1 enable 0 [1] 1 1 minute alarm1 enable 0 [1] 1 disabled enabled second alarm1 enable SEC_A1E 0 1 [1] disabled enabled MIN_A1E 0 Description [1] disabled enabled Default value. 7.4.2.3 Alarm1 and alarm2 function in stop-watch mode The registers at addresses 08h through 0Ch contain alarm1 information. When one or more of these registers is loaded with second, minute, and hours, and its corresponding alarm enable bit (SEC_A1E to HR_00_XX_XX_A1E) is set logic 1, then that information is compared with the current second, minute, and hours. The registers at addresses 0Dh through 0Fh contain alarm2 information. When one or more of these registers is loaded with minute and hours, and its corresponding alarm enable bit (MIN_A2E to HR_00_XX_A2E) is set logic 1, then that information is compared with the current minute and hours. Alarm registers which have their alarm enable bit at logic 0 are ignored. When the time increments to match the enabled alarms, the alarm flag in the Flags register (Section 7.14) is set. A1F for alarm1 and A2F for alarm2. The alarm flag is cleared by command. When the time increments to match the enabled alarms, an interrupt can be generated. See Section 7.4.3. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 20 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus example check now signal SEC_A1E SEC_A1E = 0 SECOND ALARM1 = 0 1 SECOND TIME MIN_A1E MINUTE ALARM1 = MINUTE TIME HR_xx_xx_00_A1E HR_xx_xx_00 ALARM1 set alarm flag A1F (1) = xx_xx_00 HOUR TIME HR_xx_00_xx_A1E HR_xx_00_xx ALARM1 = xx_00_xx HOUR TIME HR_00_xx_xx_A1E HR_00_xx_xx ALARM1 = 00_xx_xx HOUR TIME example check now signal MIN_A2E MIN_A2E = 0 MINUTE ALARM2 = 0 1 MINUTE TIME HR_xx_00_A2E HR_xx_00 ALARM2 set alarm flag A2F (1) = xx_xx_00 HOUR TIME HR_00_xx_A2E HR_00_xx ALARM2 = xx_00_xx HOUR TIME aaa-009583 1. Only when all enabled alarm settings are matching. The flag is set only on increment to a matched case (and not all the time it is equal). Figure 14. Alarm1 and alarm2 function block diagram (stop-watch mode) 7.4.3 Alarm interrupts The generation of interrupts from the alarm functions is controlled via the alarm interrupt enable bits; A1IEA, A1IEB, A2IEA, A2IEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address 2Ah). The assertion of flags A1F or A2F can be used to generate an interrupt at the pins INTA and INTB. The interrupt may be generated as a pulse signal every time the time increments to match the alarm setting or as PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 21 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus a permanently active signal which follows the condition of bit A1F and/or A2F. See Section 7.9 for interrupt control. A1F and A2F remain set until cleared by command. Once an alarm flag has been cleared, it will only be set again when the time increments to match the alarm condition once more. When an interrupt pin is configured to pulse mode and if an alarm flag is not cleared and the time increments to match the alarm condition again, then a repeated interrupt pulse will be generated. 7.5 WatchDog Table 16. WatchDog - WatchDog control and register (address 2Dh) bit description Bit Symbol 7 WDM Value WatchDog mode 0 [1] single shot 1 6 to 2 repeat mode WatchDog register bits WDR[4:0] 0h [1] to 1Fh 0h to 1Fh 1 to 0 Write: WatchDog counter load value Read: current counter value WatchDog step size (source clock) WDS[1:0] 00 [1] Description [1] 4 seconds (0.25 Hz) 01 1 second (1 Hz) 10 1 ⁄4 second (4 Hz) 11 1 ⁄16 second (16 Hz) Default value. 7.5.1 WatchDog functions The WatchDog has four selectable step sizes allowing for periods in the range from 62.5 ms to 124 seconds. For periods greater than 2 minutes, the alarm function can be used. (1) Table 17. WatchDog durations WDS[1:0] WatchDog step size Delay [1] Minimum WatchDog duration WDR = 1 Maximum WatchDog duration WDR = 31 00 4s 4s 124 s 01 1s 1s 31 s 10 1 0.25 s 7.75 s 11 1 0.0625 s 1.9375 s [1] ⁄4 s ⁄16 s Time periods can be affected by correction pulses. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 22 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Remark: Note that all timings are generated from the 32.768 kHz oscillator and are based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency results in deviation in timings. This is not applicable to interface timing. The WatchDog counts down from a software-loaded 5-bit binary value, WDR[4:0], in register WatchDog. Loading the counter with 0 stops the WatchDog. Loading the counter with a non-0 value starts the counter. Values from 1 to 31 are allowed. countdown value, WDR 00 03 WatchDog clock counter 00 03 02 01 03 02 01 03 02 01 03 WDF INTA or INTB WDR counts WDR counts duration of first WatchDog period after start may range from WDR to WDR -1 counts aaa-009584 In this example, it is assumed that the WatchDog flag (WDF) is cleared before the next WatchDog period expires and that the interrupt output is set to pulsed mode. Figure 15. WatchDog repeat mode If a new value of WDR[4:0] is written before the end of the current WatchDog period, then this value takes immediate effect. When starting the timer for the first time or when reloading WDR[4:0] before the end of the current period, the first period has an uncertainty of maximum one count. The uncertainty is a result of loading the WDR[4:0] from the interface clock which is asynchronous from the WatchDog source clock. Subsequent WatchDog periods do not have such variation. Reading the WatchDog register returns the current value of the WatchDog counter (see Figure 15) and not the initial value WDR[4:0]. Since it is not possible to freeze the WatchDog counter during read back, it is recommended to read the register twice and check for consistent results. 7.5.1.1 WatchDog repeat mode In repeat mode, at the end of every WatchDog period, the WatchDog flag (bit WDF in the Flags register, Section 7.14) is set and the counter automatically reloads and starts the next WatchDog period. An example is given in Figure 15. The asserted bit WDF can be used to generate an interrupt. Bit WDF can only be cleared by command. 7.5.1.2 WatchDog single shot mode In single shot mode, at the end of the countdown period, the WatchDog flag (bit WDF in the Flags register, Section 7.14) is set and the counter stops with the value 0. The WatchDog register must be reloaded to start another WatchDog period. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 23 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus countdown value, WDR 00 06 WatchDog clock counter 00 06 05 04 03 02 01 00 WDF INTA or INTB duration of WatchDog period after start may range from WDR to WDR -1 counts aaa-009585 Figure 16. WatchDog single shot mode 7.5.1.3 WatchDog interrupts The generation of interrupts from the WatchDog functions is controlled via the WatchDog interrupt enable bits; WDIEA and WDIEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address 2Ah). The assertion of the flag WDF can be used to generate an interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed signal every time the WatchDog counter reaches the end of the countdown period. Alternatively as a permanently active signal which follows the condition of bit WDF. WDF remains set until cleared by command. When enabled, interrupts are triggered every time the WatchDog counter reaches the end of the countdown period and even if the WDF is not cleared, an interrupt pulse can be generated. See Section 7.9 for interrupt control. 7.6 RAM byte Table 18. RAM_byte - 8-bit RAM register (address 2Ch) bit description Bit Symbol 7 to 0 [1] B[7:0] Value 0000 0000 1111 1111 Description [1] to RAM content Default value. The PCF85263A provides a free RAM byte, which can be used for any purpose, for example, status bits of the system. 7.7 Timestamps There are three timestamp registers which can be independently configured to record the time for battery switch-over events and/or transitions on the TS pin. Each timestamp register has an associated flag. It is also possible to generate an interrupt signal for every timestamp register update. Timestamps work in both RTC and stop-watch mode. During battery operation, the mechanical switch detector may also be used to trigger the timestamp. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 24 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus The timestamp registers are read only and cannot be written. It is possible to set all three registers to 0 with the CTS instruction in the Resets register (Section 7.15). mode TSR1M[1:0] flag TSR1F mode TSR2M[2:0] flag TSR2F mode TSR3M[1:0] flag TSR3F timer registers RTC mode seconds minutes : years timestamp register timestamp register timestamp register TSR1 TSR2 TSR3 stopwatch mode seconds minutes : 999999 hours load load load load TS pin battery switchover aaa-009595 Figure 17. Timestamp The mode for each register is controlled by the TSR_mode register. Table 19. TSR_mode - timestamp mode control register (address 23h) bit description Bit Symbol Value Description Timestamp3 (TSR3) 7 to 6 timestamp register 3 mode TSR3M[1:0] 00 5 - PCF85263A Product data sheet [1] no timestamp 01 FB, record First time switch to Battery event 10 LB, record Last time switch to Battery event 11 LV, record Last time switch to VDD event 0 not used All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 25 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 19. TSR_mode - timestamp mode control register (address 23h) bit description...continued Bit Symbol Value Description Timestamp2 (TSR2) 4 to 2 timestamp register 2 mode TSR2M[2:0] 000 [1] no timestamp 001 FB, record First time switch to Battery event 010 LB, record Last time switch to Battery event 011 LV, record Last time switch to VDD event 100 FE, record First TS pin Event 101 LE, record Last TS pin Event 110 to 111 no timestamp Timestamp1 (TSR1) 1 to 0 timestamp register 1 mode TSR1M[1:0] 00 [1] [1] no timestamp 01 FE, record First TS pin Event 10 LE, record Last TS pin Event 11 no timestamp Default value. First event means that the time is only stored on the first event and not recorded for subsequent events. When the first event occurs, the associated timestamp flag is set. When the flag is cleared, then a new ‘first’ event is recorded. See Figure 18 and Figure 19. Last event means that the time is stored on every event. When an event occurs, the associated timestamp flag is set. It is not necessary to clear the flag before a new event is recorded. Interrupts can be generated in INTA pin and/or INTB pin. Interrupts are generated every time a timestamp register is updated. Interrupt generation is not conditional on the state of the timestamp flags. See Section 7.7.1. source of power VDD power battery power VDD power battery power VDD power event time t1 t2 t3 t4 t5 event type FB, LB LV FB, LB LV LB timestamp3 flag, TSR3F flag cleared by interface TSR3 set to first time switch to battery, FB TSR3 = t1 no change TSR3 = t3 no change no change TSR2 set to last time switch to VDD , LV no change TSR2 = t2 no change TSR2 = t4 no change aaa-009596 Figure 18. Example battery switch-over timestamp PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 26 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus TS pin(1) event time t1 t2 t3 t4 t5 event type FE, LE LE LE FE, LE LE timestamp1 flag, TSR1F flag cleared by interface TSR2 set to last TS pin event, LE TSR2 = t1 TSR2 = t2 TSR2 = t3 TSR2 = t4 TSR2 = t5 TSR1 set to first TS pin event, FE TSR3 = t1 no change no change TSR3 = t4 no change aaa-009604 1. TS pin set to active HIGH (TSL = 0), see register Pin_IO (address 27h). Figure 19. Example TS pin driven timestamp The recorded time is stored in the associated timestamp register. The time format depends on the RTC mode. The timestamp registers follows the time format of the time registers. Table 20. Timestamp registers in RTC mode (RTCM = 0) Bit positions labeled as - are not implemented and return 0 when read. Address Register name Upper-digit (ten’s place) Bit 7 Bit 6 Bit 5 Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTC timestamp1 (TSR1) 11h TSR1_seconds - 0 to 5 0 to 9 12h TSR1_minutes - 0 to 5 0 to 9 13h TSR1_hours - - AMPM 0 to 1 0 to 9 0 to 2 0 to 9 0 to 9 14h TSR1_days - - 0 to 3 15h TSR1_months - - - 16h TSR1_years 0 to 9 0 to 1 0 to 9 0 to 9 RTC timestamp2 (TSR2) 17h TSR2_seconds - 0 to 5 0 to 9 18h TSR2_minutes - 0 to 5 0 to 9 19h TSR2_hours - - AMPM 0 to 1 0 to 9 0 to 2 0 to 9 0 to 9 1Ah TSR2_days - - 0 to 3 1Bh TSR2_months - - - 1Ch TSR2_years 0 to 9 0 to 1 0 to 9 0 to 9 RTC timestamp3 (TSR3) 1Dh TSR3_seconds - 0 to 5 0 to 9 1Eh TSR3_minutes - 0 to 5 0 to 9 PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 27 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 20. Timestamp registers in RTC mode (RTCM = 0)...continued Bit positions labeled as - are not implemented and return 0 when read. Address 1Fh Register name TSR3_hours Upper-digit (ten’s place) Bit 7 Bit 6 - - Bit 5 AMPM Digit (unit place) Bit 4 Bit 3 0 to 1 0 to 9 0 to 2 0 to 9 0 to 9 20h TSR3_days - - 0 to 3 21h TSR3_months - - - 22h TSR3_years 0 to 9 0 to 1 Bit 2 Bit 1 Bit 0 0 to 9 0 to 9 Table 21. Timestamp registers in stop-watch mode (RTCM = 1) Bit positions labeled as - are not implemented and return 0 when read. Address Register name Upper-digit (ten’s place) Bit 7 Bit 6 Bit 5 Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - - - - Stop-watch timestamp1 (TSR1) 11h TSR1_seconds - 0 to 5 0 to 9 12h TSR1_minutes - 0 to 5 0 to 9 13h TSR1_hr_xx_xx_00 0 to 9 0 to 9 14h TSR1_hr_xx_00_xx 0 to 9 0 to 9 15h TSR1_hr_00_xx_xx 0 to 9 0 to 9 16h not used - - - - - Stop-watch timestamp2 (TSR2) 17h TSR2_seconds - 0 to 5 0 to 9 18h TSR2_minutes - 0 to 5 0 to 9 19h TSR2_hr_xx_xx_00 0 to 9 0 to 9 1Ah TSR2_hr_xx_00_xx 0 to 9 0 to 9 1Bh TSR2_hr_00_xx_xx 0 to 9 0 to 9 1Ch not used - - - - - Stop-watch timestamp3 (TSR3) 1Dh TSR3_seconds - 0 to 5 0 to 9 1Eh TSR3_minutes - 0 to 5 0 to 9 1Fh TSR3_hr_xx_xx_00 0 to 9 0 to 9 20h TSR3_hr_xx_00_xx 0 to 9 0 to 9 21h TSR3_hr_00_xx_xx 0 to 9 0 to 9 22h not used - PCF85263A Product data sheet - - - All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 - © 2023 NXP B.V. All rights reserved. 28 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 7.7.1 Timestamps interrupts The generation of interrupts from the timestamp functions is controlled via the timestamp interrupt enable bits; TSRIEA and TSRIEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address 2Ah). The loading of new information into one of the timestamp registers can be used to generate an interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed signal every time a timestamp register updates or as a permanently active signal which follows the condition of timestamp flags, TSR1F to TSR3F. The timestamp flags remain set until cleared by command. When enabled, interrupts are triggered every time a timestamp register updates and even if the associated flag is not cleared, an interrupt pulse can be generated. See Section 7.9 for interrupt control. 7.8 Offset register The PCF85263A incorporates an offset register (address 24h) which can be used to implement several functions, such as: • Accuracy tuning • Aging adjustment • Temperature compensation Table 22. Offset - offset register (address 24h) bit description Bit Symbol Value Description 7 to 0 OFFSET[7:0] see Table 24 offset value There are two modes which define the correction period, normal mode and fast mode. The normal mode is suitable for offset trimming. The fast mode is suitable for dynamic offset correction e.g. implementing a temperature correction. The fast mode consumes more current. Offset mode is defined by bit OFFM in the Oscillator register (Section 7.10). Table 23. OFFM bit - oscillator control register (address 25h) See Section 7.10 Bit Symbol 6 OFFM Value offset mode bit 0 [1] normal mode: correction is made every 4 hours; 2.170 ppm/step 1 [1] Description fast mode: correction is made once every 8 minutes;2. 0345 ppm/step Default value. For OFFM = 0, each LSB introduces an offset of 2.170 ppm. For OFFM = 1, each LSB introduces an offset of 2.0345 ppm. The offset value is coded in two’s complement giving a range of +127 LSB to -128 LSB, see Table 24. Table 24. Offset values OFFSET[7:0] 011 1 1111 PCF85263A Product data sheet Offset value in decimal +127 Offset value in ppm Normal mode OFFM = 0 Fast mode OFFM = 1 +275.590 +258.3815 All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 29 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 24. Offset values...continued OFFSET[7:0] Offset value in decimal Offset value in ppm Normal mode OFFM = 0 Fast mode OFFM = 1 011 1 1110 +126 +273.420 +256.3470 : : : : 0000 0010 +2 +4.340 +4.0690 +1 +2.170 +2.0345 0000 0001 0000 0000 [1] [1] 0 1111 1111 -1 -2.170 -2.0345 1111 1110 -2 -4.340 -4.0690 : : : : 1000 0001 -127 -275.590 -258.3815 1000 0000 -128 -277.760 -260.416 [1] 0 [1] 0 Default value. The correction is made by adding or subtracting clock correction pulses, thereby changing the period of a single second but not by changing the oscillator frequency. It is possible to monitor when correction pulses are applied. See Section 7.8.4. 7.8.1 Correction when OFFM = 0 The correction is triggered once every four hours and then correction pulses are applied once per minute until the programmed correction values have been implemented. Table 25. Correction pulses for OFFM = 0 th Correction value Every n hour Actual minute +1 or -1 4 00 +2 or -2 4 00 and 01 +3 or -3 4 00, 01, and 02 : : : +59 or -59 4 00 to 58 +60 or -60 4 00 to 59 +61 or -61 4 00 to 59 4+1 00 4 00 to 59 4+1 00 and 01 : : : +123 or -123 4 00 to 59 4+1 00 to 59 4+2 00, 01, and 02 +62 or -62 PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 30 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 25. Correction pulses for OFFM = 0...continued th Correction value Every n hour Actual minute -128 4 00 to 59 4+1 00 to 59 4+2 00 to 07 7.8.2 Correction when OFFM = 1 The correction is triggered once every eight minutes and then correction pulses are applied once per second until the programmed correction values have been implemented. Clock correction is made more frequently in OFFM = 1; however, this can result in higher power consumption. Table 26. Correction pulses for OFFM = 1 th Correction value Every n minute Actual second +1 or -1 8 00 +2 or -2 8 00 and 01 +3 or -3 8 00, 01, and 02 : : : +59 or -59 8 00 to 58 +60 or -60 8 00 to 59 +61 or -61 8 00 to 59 8+1 00 8 00 to 59 8+1 00 and 01 : : : +123 or -123 8 00 to 59 8+1 00 to 59 8+2 00, 01, and 02 8 00 to 59 8+1 00 to 59 8+2 00 to 07 +62 or -62 -128 7.8.3 Offset calibration workflow The calibration offset has to be calculated based on the time. Figure 20 shows the workflow how the offset register values can be calculated: PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 31 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Measure the frequency on pin CLKOUT: fmeas sample calculation: 32768.28 Hz Convert to time: 30.517320 µs tmeas = 1 / fmeas Calculate the difference to the ideal period of 1 / 32768.00: 0.000260 µs Dmeas = 1 / 32768 - tmeas Calculate the ppm deviation compared to the measured value: 8.51975 ppm Eppm = 1000000 × Dmeas / tmeas Calculate the offset register value: OFFM = 0 (low power): Offset value = Eppm / 2.17 3.926 OFFM = 1 (fast correction) Offset value = Eppm / 2.0345 4 correction pulses are needed 4.188 4 correction pulses are needed aaa-009636 Figure 20. Offset calibration calculation workflow (1) (2) (3) -2 -1 deviation after correction in OFFM = 0 -0.160 ppm 0 1 2 3 4 5 6 deviation after correction in OFFM = 1 +0.382 ppm 7 8 9 measured/calculated deviation 8.51975 ppm aaa-009637 With the offset calibration an accuracy of ±1 ppm (0.5 × offset per LSB) can be reached (see Table 24). ±1 ppm corresponds to a time deviation of 0.0864 seconds per day. 1. 4 correction pulses in OFFM = 0 correspond to -8.680 ppm. 2. 4 correction pulses in OFFM = 1 correspond to -8.138 ppm. 3. Reachable accuracy zone. Figure 21. Result of offset calibration PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 32 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 7.8.4 Offset interrupts The generation of interrupts from the offset functions is controlled via the offset interrupt enable bits; OIEA and OIEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address 2Ah). Every time a correction pulse is made an interrupt pulse can be generated at pins INTA and INTB. As there is no offset calibration flag, it is only possible to generate pulse interrupts. See Section 7.9 for interrupt control. 7.9 Interrupts There are two interrupt output pins, INTA and INTB. Both pins have the same possible sources and a dedicated register to control what is output. The pins can be used independently from each other. INTA data is output on the INTA pin. INTA is an interrupt output pin with open-drain drive. INTA pin mode is controlled by INTAPM[1:0] bits in the Pin_IO register (Section 7.12). INTB data is output on TS pin with push-pull drive. The TS pin must first be configured as INTB output by setting TSIO[1:0] bits in the Pin_IO register (Section 7.12). Interrupts will only be output when the pin mode is correctly defined. Interrupts are output from the IC as active LOW signals. The registers INTA_enable (address 29h) and INTB_enable (address 2Ah) are used to select which interrupts should be output on which pin. Table 27. INTA and INTB interrupt control bits Bit 7 6 5 4 3 2 1 0 A1IEA A2IEA TSRIEA BSIEA WDIEA A1IEB A2IEB TSRIEB BSIEB WDIEB INTA_enable - INTA pin enable control (address 29h) Symbol ILPA PIEA OIEA INTB_enable - INTB pin enable control (address 2Ah) Symbol ILPB PIEB OIEB Table 28. Definition of interrupt control bits Bit 7 Symbol Value INTA INTB ILPA ILPB level or pulse mode 0 [1] 1 6 PIEA periodic interrupt enable [1] 1 OIEA offset correction interrupt enable [1] 1 A1IEA Product data sheet no correction interrupt generated interrupt generated from correction alarm1 interrupt enable A1IEB 0 PCF85263A no periodic interrupt generated periodic interrupt generated OIEB 0 4 interrupt generates a pulse interrupt follows flags (permanent signal) PIEB 0 5 Description [1] no alarm interrupt generated All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 33 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 28. Definition of interrupt control bits...continued Bit Symbol INTA Value INTB 1 3 A2IEA alarm interrupt generated alarm2 interrupt enable A2IEB 0 [1] no alarm interrupt generated 1 2 TSRIEA alarm interrupt generated timestamp register interrupt enable TSRIEB 0 [1] no timestamp register interrupt generated 1 1 BSIEA timestamp register interrupt generated battery switch interrupt enable BSIEB 0 [1] no battery switch interrupt generated 1 0 WDIEA battery switch interrupt generated WatchDog interrupt enable WDIEB 0 [1] no WatchDog interrupt generated 1 [1] Description WatchDog interrupt generated Default value. 7.9.1 ILPA/ILPB: interrupt level or pulse mode Interrupts can be configured to generate a pulse or to send a continuous level (permanent signal) which follows the state of the flag. In pulse mode, an interrupt pulse is generated every time that the selected source triggers. Triggered means • • • • • • for periodic interrupts, every time a period has elapsed for offset correction, every time a correction pulse is initiated for alarms, every time the time increments to match the alarm time for timestamps, every time a register updates for battery switch, every time the IC switches to or from battery for WatchDog, every time the counter reaches the end of its count The interrupt signal goes active coincident with the triggering event. The signal is cleared by an internal 128 Hz clock. The internal clock is asynchronous to the triggering event and so the pulse duration has a minimum period of one 128 Hz cycle and a maximum of two 128 Hz cycles. Interrupt pulses may be shortened by clearing the flag before the end of the pulse period. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 34 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Flag does not need to be cleared for interrupts to be generated trigger event flag interrupt 128 Hz clock Minimum interrupt period Maximum interrupt period aaa-009638 Figure 22. Interrupt pulse width In level mode, the interrupt signal follows the state of the flag. Only interrupts which are enabled will affect the pin state. All enabled flags must be cleared for the interrupt signal to be cleared. The EMON is used only for monitoring all flags and can be read back in the minutes register. See Section 7.2.3. 7.9.2 Interrupt enable bits The remainder of the bits in register INTA_enable (address 29h) and register INTB_enable (address 2Ah) are used to select which interrupt data goes where. See Figure 23 PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 35 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Pulse generator trigger clear 128 Hz Alarm 1 set A1IEA A1IEB Alarm 2 set A2IEA A2IEB Battery switch set BSIEA set WDIEA clear A1IEA WDIEB A1IEB 0 INTA data Flag: A2F 1 clear A2IEA A2IEB BSIEA BSIEB WDIEA WDIEB Flag: BSF clear BSIEB WatchDog ILPA Flag: A1F Flag: WDF clear EMON OR Timestamp1 set TSRIEA clear TSRIEB Timestamp2 set Timestamp3 set Periodic interrupt set PIEA PIEB Offset calibration OIEA OIEB Flag: TSR1F TSIEA TSIEB PIEA PIEB Flag: TSR2F clear Flag: TSR3F clear Flag: PIF clear Flag(s) cleared by command 1 Pulse generator trigger 0 INTB data clear 128 Hz ILPB aaa-010367 Figure 23. Interrupt selection PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 36 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 7.10 Oscillator register Table 29. Oscillator - oscillator control register (address 25h) bit description Bit 7 6 5 4 3 2 1 0 Symbol CLKIV OFFM 12_24 LOWJ OSCD[1:0] CL[1:0] Section Section 7.16 Section 7.8 Section 7.10.3 Section 7.10.4 Section 7.10.5 Section 7.10.6 7.10.1 CLKIV: invert the clock output Table 30. CLKIV bit - oscillator control register (address 25h) Bit Symbol 7 CLKIV Value Description output clock inversion 0 [1] non-inverting; LOWJ mode will affect rising edge 1 [1] inverted; LOWJ mode will affect falling edge Default value. The clock selected with the COF[2:0] bits (register Function, address 28h) can be inverted. This is intended for use in conjunction with the low jitter mode, LOWJ. The low jitter mode reduces the jitter for the rising edge of the output clock. If the reduced jitter needs to be on the falling edge, for example when using an open-drain clock output, then the CLKIV bit can be used to implement this. 7.10.2 OFFM: offset calibration mode See Section 7.8 for a full description of offset calibration. 7.10.3 12_24: 12 hour or 24 hour clock Table 31. 12_24 bit - oscillator control register (address 25h) Bit Symbol 5 12_24 Value Description 12 hour or 24 hour mode 0 [1] 24 hour mode is selected 1 [1] 12 hour mode is selected Default value. In RTC mode, time counting can be configured for 24 hour clock or 12 hour clock with the AMPM flag. This bit is ignored in stop-watch mode. 7.10.4 LOWJ: low jitter mode Table 32. LOWJ bit - oscillator control register (address 25h) Bit Symbol 4 LOWJ Value low jitter CLK output bit 0 1 PCF85263A Product data sheet Description [1] normal reduced CLK output jitter; increase IDD All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 37 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus [1] Default value. Oscillator circuits suffer from jitter. In particular, ultra low-power oscillators like the one used in the PCF85263A are optimized for power and not jitter. By setting the LOWJ bit, the jitter performance can be improved at the cost of power consumption. 7.10.5 OSCD[1:0]: quartz oscillator drive control Table 33. OSCD[1:0] bits - oscillator control register (address 25h) Bit Symbol 3 to 2 OSCD[1:0] Value oscillator drive bits 00 [1] Description [1] normal drive; RS(max): 100 kΩ 01 low drive; RS(max): 60 kΩ; reduced IDD 10, 11 high drive; RS(max): 500 kΩ; increased IDD Default value. The oscillator is designed to be used with quartz with a series resistance up to 100 kΩ. This covers the typical range of 32.768 kHz quartz crystals. Series resistance is also referred to as: ESR, motional resistance, or RS. A low drive mode is available for low series resistance quartz. This reduces the current consumption. For very high series resistance quartz, there is a high drive mode. Current consumption increases substantially in this mode. 7.10.6 CL[1:0]: quartz oscillator load capacitance Table 34. CL[1:0] bits - oscillator control register (address 25h) Bit Symbol 1 to 0 CL[1:0] Value internal oscillator capacitor selection for quartz crystals with the corresponding load capacitance of CL: 00 [1] Description [1] 7.0 pF 01 6.0 pF 10 12.5 pF 11 12.5 pF Default value. CL refers to the load capacitance of the oscillator circuit and allows for a certain amount of package and PCB parasitic capacitance. When the oscillator circuit matches the CL parameter of the quartz, then the frequency offset is zero. The PCF85263A is designed to operate with quartz with CL values of 6.0 pF, 7.0 pF and 12.5 pF. 12.5 pF are generally the cheapest and most widely available, but also require the most power to drive. The circuit also operates with 9.0 pF quartz, however the offset calibration would be needed to compensate. If a 9.0 pF quartz is used, then it is recommended to set CL to 7.0 pF. 7.11 Battery switch register This register configures the battery switch-over mode. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 38 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Associated with the battery switch-over is the battery switch flag (BSF) in the Flags register (Section 7.14). Whenever the IC switches to battery operation, the flag is set. The flag can only be read when operating from VDD power, however an interrupt pulse or static LOW signal can be generated whenever switching to battery. An interrupt pulse can also be generated when switching back to VDD power. Examples are given in Figure 25 and Figure 26. 2 When switched to battery, the VDD power domain is disabled. This means that I C pins are ignored, CLK output is disabled and Hi-Z, TS pin output mode is disabled and Hi-Z, TS digital input is ignored and may be left floating. TS pin mechanical switch detector is active. INTA output is still active for interrupt output and battery switch indication, but disabled for clock output. Table 35. IO pin behavior in battery mode IO pin (mode) VDD operation VBAT operation SCL active input disabled; may be left floating SDA active input/output disabled; may be left floating CLK active output disabled; Hi-Z TS (output mode) active output disabled; Hi-Z TS (digital input) active input disabled; may be left floating TS (mechanical switch input) active input active input INTA active output active interrupt output Table 36. Battery_switch - battery switch control (address 26h) bit description Bit 7 6 5 4 3 2 1 0 Symbol - - - BSOFF BSRR BSM[1:0] BSTH Section - - - Section 7.11.1 Section 7.11.2 Section 7.11.3 Section 7.11.4 7.11.1 BSOFF: battery switch on/off control Table 37. BSOFF bit - battery switch control (address 26h) bit description Bit Symbol 4 BSOFF Value Description battery switch on/off 0 [1] enable battery switch feature 1 [1] disable battery switch feature Default value. The battery switch circuit may be disabled when not used. This disables all the circuit and save power consumption. When disabled connect VBAT and VDD together. 7.11.2 BSRR: battery switch internal refresh rate Table 38. BSRR bit - battery switch control (address 26h) bit description Bit Symbol 3 BSRR Value battery switch refresh rate 0 PCF85263A Product data sheet Description [1] low All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 39 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 38. BSRR bit - battery switch control (address 26h) bit description...continued Bit Symbol Value 1 [1] Description high Default value. Non-user bit. Recommended to leave set at default. 7.11.3 BSM[1:0]: battery switch mode Table 39. BSM[1:0] bits - battery switch control (address 26h) bit description Bit Symbol 2 to 1 BSM[1:0] Value battery switch mode bits 00 [1] Description [1] switching at the Vth level 01 switching at the VBAT level 10 switching at the higher level of Vth or VBAT 11 switching at the lower level of Vth or VBAT Default value. Switching is automatic and controlled by the voltages on the VBAT and VDD pins. There are three modes: • Compare VDD with an internal reference (Vth) • Compare VDD with VBAT • Compare VDD with an internal reference (Vth) and VBAT The last mode is useful when a rechargeable battery is employed. Table 40. Battery switch-over modes BSM[1:0] Condition Internal power 00 VDD > Vth VDD VDD < Vth VBAT VDD > VBAT VDD VDD < VBAT VBAT VDD > the higher of Vth or VBAT VDD VDD < the higher of Vth or VBAT VBAT VDD > the lower of Vth or VBAT VDD VDD < the lower of Vth or VBAT VBAT 01 10 11 Due to the nature of the power switch circuit there is a switching hysteresis (see Figure 24 and Table 67). PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 40 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus VDD VDD decreasing switching point hysteresis VDD increasing max Vth(low) Vth(high) typ min t battery operation RTC power supply switch to VDD switch to battery VDD operation VDD operation aaa-010665 Figure 24. Threshold voltage switching hysteresis 7.11.3.1 Switching at the Vth level, BSM[1:0] = 00 VDD VBAT internal power supply Vth VDD (= 0 V) cleared via interface BSF INTA I2C battery mode indication interface active interface inactive interface active aaa-010423 Figure 25. Switching at Vth PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 41 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 7.11.3.2 Switching at the VBAT level, BSM[1:0] = 01 VDD VBAT internal power supply Vth VDD (= 0 V) cleared via interface BSF INTA I2C battery mode indication interface active interface inactive interface active aaa-010425 Figure 26. Switching at VBAT 7.11.3.3 Switching at the higher of VBAT or Vth level, BSM[1:0] = 10 With this mode switching takes place when VDD falls below the higher of Vth or VBAT. In Figure 27, an example is given where the threshold is set to 1.5 V and a single cell battery is connected to VBAT. In this example, switching to the battery voltage takes place when VDD falls below Vth. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 42 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus VDD Vth = 1.5 V internal power supply VBAT = 1.2 V VDD (= 0 V) cleared via interface BSF INTA I2C battery mode indication interface active interface inactive interface active aaa-010426 Figure 27. Switching at the higher of VBAT or Vth 7.11.3.4 Switching at the lower of VBAT and Vth level, BSM[1:0] = 11 With this mode switching takes place when VDD falls below the lower of Vth or VBAT. In Figure 28, an example is given where the threshold is set to 1.5 V and a single cell battery is connected to VBAT. In this example, switching to the battery voltage takes place when VDD falls below VBAT. VDD Vth = 1.5 V VBAT = 1.2 V internal power supply VDD (= 0 V) cleared via interface BSF INTA I2C battery mode indication interface active interface inactive interface active aaa-010429 Figure 28. Switching at the lower of VBAT or Vth PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 43 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 7.11.4 BSTH: threshold voltage control Table 41. BSTH - battery switch control (address 26h) bit description Bit Symbol 0 BSTH Value Description battery switch threshold voltage, Vth 0 [1] Vth = 1.5 V 1 [1] Vth = 2.8 V Default value. The threshold for battery switch-over is selectable between two voltages, 1.5 V and 2.8 V. 7.11.5 Battery switch interrupts The generation of interrupts from the battery switch function is controlled via the battery switch interrupt enable bits; BSIEA and BSIEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address 2Ah). The assertion of the flag BSF (register Flags, address 2Bh) can be used to generate an interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed signal or alternatively as a permanently active signal which follows the condition of bit BSF. BSF remains set until cleared by command. When enabled, interrupts are triggered every time the battery switch circuit switches to either battery or to VDD and even if the BSF is not cleared, an interrupt pulse can be generated. In addition, the INTA pin can be configured as a battery mode indicator (INTAPM[1:0] = 00). See Section 7.12.6. This mode differs from a general interrupt signal in that it is only controlled by the current battery switch status. See Section 7.9 for interrupt control. Remark: INTB pin is only active when the IC is operating from VDD. 7.12 Pin_IO register Table 42. Pin_IO- pin input output control register (address 27h) bit description Bit 7 6 5 4 3 2 1 0 Symbol CLKPM TSPULL TSL TSIM TSPM[1:0] INTAPM[1:0] Section Section 7.12.1 Section 7.12.2 Section 7.12.3 Section 7.12.5 Section 7.12.4 Section 7.12.6 This register is used to define the input and output modes of the IC. 7.12.1 CLKPM: CLK pin mode control Table 43. CLKPM bit - Pin_IO control register (address 27h) Bit Symbol 7 CLKPM Value [1] CLK pin mode 0 1 [1] [2] Description [2] enable CLK pin disable CLK pin CLK pin is not available on all package types. Default value. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 44 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Setting the CLKPM bit disables the CLK output and force the pin to drive out a logic 0. Clearing this bit enables the pad to output the selected clock frequency (see bits COF[2:0] in the Function register, see Table 50). 7.12.2 TSPULL: TS pin pull-up resistor value Table 44. TSPULL bit - Pin_IO control register (address 27h) Bit Symbol 6 TSPULL Value TS pin pull-up resistor value 0 [1] 80 kΩ 1 [1] Description 40 kΩ Default value. Controls the pull-up resistor value used in the mechanical switch detector. For applications where there is a large capacitance on the TS pin e.g. from a long connecting cable to the mechanical switch, the pull-up resistor value can be halved to improve switch detection. Using the low-resistance value increases current consumption when the switch is closed i.e. shorting to VSS. 7.12.3 TSL: TS pin level sense Table 45. TSL bit - Pin_IO control register (address 27h) Bit Symbol 5 TSL Value TS pin input sense 0 [1] active HIGH 1 [1] Description active LOW Default value. The active state of the TS pin can be defined for use as a timestamp trigger and/or as stop control for the time counting. Active HIGH implies a transition from logic 0 to logic 1 is active. Active LOW implies a transition from logic 1 to logic 0 is active. 7.12.4 TSPM[1:0]: TS pin I/O control Table 46. TSPM[1:0] bits - Pin_IO control register (address 27h) Bit Symbol 3 to 2 TSPM[1:0] Value TS pin IO mode 00 [1] Description [1] disabled; input can be left floating 01 INTB output; push-pull 10 CLK output; push-pull 11 input mode Default value. These bits control the operation of the TS pin. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 45 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus mechanical switch detector vdd_int sample clock TSL sample 80 kΩ/ 40 kΩ invert input data TS (CLK/INTB) pin (1) INTB data clock data aaa-010443 1. Not available on all package types. Figure 29. TS pin TSIM is only considered when the TS pin is in input mode. 7.12.4.1 TS pin output mode; INTB It is possible to output INTB data on the TS pin. The output is push-pull. No output is available when on VBAT. When on VBAT the output is Hi-Z. 7.12.4.2 TS pin output mode; CLK It is possible to output a clock frequency on the TS pin. Clock frequency is selected with the COF[2:0] bits in the Function register (Section 7.13). The output is push-pull. No output is available when on VBAT. When on VBAT the output is Hi-Z. 7.12.4.3 TS pin disabled When disabled the pin is Hi-Z and can be left floating. 7.12.5 TSIM: TS pin input type control Table 47. TSIM bit - Pin_IO control register (address 27h) Bit Symbol 4 TSIM Value TS pin input mode 0 1 [1] Description [1] CMOS input; reference to VDD; disabled when on VBAT mechanical switch mode; active pull-up sampled at 16 Hz; operates on VDD and VBAT Default value. In CMOS input mode (TSIM = 0), input is taken directly from the TS pin. The input is conditioned by the setting of TSL. When operating on the battery voltage (VBAT), the input is disabled and is allowed to float. In mechanical switch detector mode (TSIM = 1), the TS pin is sampled at a rate of 16 Hz for a period of 30.5 μs. At the same time as the sample a pull-up resistor is activated to detect an open pin or a pin shorted to VSS. The PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 46 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus input is referenced to the internal power supply. This mode operates when on VDD or VBAT. The pull-up resistor value can be controlled by TSPULL bit in the Pin_IO register (see Section 7.12). 7.12.5.1 TS pin input mode There are two input types which are controlled by the TSIM bit. The TS input can be used to generate a timestamp event by configuring the timestamp mode bits; TSR2M[2:0] and TSR1M[1:0] bits in TSR_mode register (see Table 19). Also it is possible to use the TS pin to control counting of time. This is typically for use with the stop-watch mode where an elapsed time counter function can be implemented. Using the STOPM bit in the Function register (see Table 50) it is possible to control the STOP bit by the TS pin. 7.12.6 INTAPM[1:0]: INTA pin mode control Table 48. INTAPM[1:0] bits - Pin_IO control register (address 27h) Bit Symbol 1 to 0 INTAPM[1:0] Value INTA pin mode 00 [1] Description [1] CLK output mode 01 battery mode indication 10 INTA output 11 Hi-Z Default value. The INTA pin can be used to output three different signals. battery mode clock data INTA (CLK) INTA data aaa-010464 Figure 30. INTA pin 7.12.6.1 INTAPM[1:0]: INTA The primary function of the INTA pin is to output INTA data. INTA data is controlled by the bits of the INTA_enable register (see Table 28). The output is active LOW with an open-drain output. The output is available during VDD and VBAT operation. 7.12.6.2 INTAPM[1:0]: clock data It is possible to output a clock frequency on the INTA pin. Clock frequency is selected with the COF[2:0] bits in the Function register (Section 7.13). The output is active LOW with an open-drain output. The output is available only during VDD operation. The output is Hi-Z when operating from VBAT. Remark: Clock output is the default state. To save power, it is recommended to disable the clock when not being used. If no clock is required, then set COF[2:0] in the Function register (Section 7.13) to CLK disabled. If clock output is only required on the CLK pin, then set the INTA pin to either INTA data or battery mode. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 47 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 7.12.6.3 INTAPM[1:0]: battery mode indication It is possible to output the state of the power switch on the INTA pin. The output has an open-drain output. The output is available during VDD and VBAT operation. Table 49. INTA battery mode Power supply INTA pin state VDD INTA = Hi-Z VBAT INTA = logic 0 7.13 Function register Table 50. Function - chip function control register (address 28h) bit description Bit 7 6 5 4 3 2 1 Symbol 100TH PI[1:0] RTCM STOPM COF[2:0] Section Section 7.13.1 Section 7.13.2 Section 7.13.3 Section 7.13.4 Section 7.13.5 0 7.13.1 100TH: 100th seconds mode Table 51. 100TH bit - Function control register (address 28h) Bit Symbol 7 100TH Value Description 100th second mode 0 [1] 100th second disabled 1 [1] 100th second enabled Default value. The PCF85263A can be configured to count at a resolution of 1 second or 0.01 seconds. In 100th mode, the 100th_seconds register becomes available and the RTC counts at a resolution of 0.01 seconds. The 256 Hz clock signal is divided by 3 for fourteen 100 Hz periods and then by 2 for eleven 100 Hz periods. This produces an effective division ratio of 2.56 with a maximum jitter of 3.91 ms. Over twenty-five 100 Hz cycles the jitter is 0 ns. 7.13.2 PI[1:0]: Periodic interrupt Table 52. PI[1:0] bits - Function control register (address 28h) Bit Symbol 6 to 5 PI[1:0] Value periodic interrupt 00 [1] Description [1] no periodic interrupt 01 once per second 10 once per minute 11 once per hour Default value. The periodic interrupt mode can be used to enable pre-defined timers for generating pulses on the interrupt pin. Interrupts once per second, once per minute or once per hour can be generated. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 48 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus When disabled, the timers are reset. When enabled, the time to the first pulse is between the chosen period and the chosen period minus 1 seconds. The timers are not affected by STOP. When the periodic interrupt triggers, the PIF (PI flag) in the Flags register (Section 7.14) is set. The flag does not have to be cleared to allow another INTA or INTB pulse. The duration of the periodic interrupt is unaffected by offset calibration. See Section 7.9 for a description of interrupt pulse control and output pins. 7.13.3 RTCM: RTC mode Table 53. RTCM bit - Function control register (address 28h) Bit Symbol 4 RTCM Value Description RTC mode 0 [1] real-time clock mode 1 [1] stop-watch mode Default value. The RTC mode is used to control how the time is counted. When configured as a classic RTC, then time is counted from 100th seconds to years. In stop-watch mode, time is counted from 100th seconds to 999 999 hours. Table 54. RTC time counting modes RTCM Mode Time counting 0 RTC 100th seconds [1] , seconds, minutes, hours, days, weekdays, months, years 100th seconds [1] , seconds, minutes, hours (0 hours to 999 999 hours) 1 [1] stop-watch Enabled with 100TH bit in the Function register (Section 7.13). 7.13.4 STOPM: STOP mode control Table 55. STOPM bit - Function control register (address 28h) Bit Symbol 3 STOPM Value Description STOP mode 0 [1] RTC stop is controlled by STOP bit only 1 [1] RTC stop is controlled by STOP bit or TS pin Default value. The STOP register bit in the Oscillator register (Section 7.10) is used to stop the counting of time in both RTC mode and stop-watch mode. Stopping of the oscillator can also be controlled from the TS pin. The TS pin must first be configured as an input by the TSPM[1:0] bits, then selected for active HIGH or active LOW by the TSL bits. Table 56. Oscillator stop control when STOPM = 1 STOP bit [1] 0 PCF85263A Product data sheet TSL TS pin 0 0 [2] Oscillator state Description running TS pin active HIGH All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 49 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 56. Oscillator stop control when STOPM = 1...continued STOP bit [1] TSL 1 1 - [1] [2] In the Oscillator register (Section 7.10). TSPM[1:0] = 11. TS pin [2] Oscillator state 1 stopped 0 stopped 1 running - stopped Description TS pin active LOW TS pin ignored 7.13.5 COF[2:0]: Clock output frequency Table 57. COF[2:0] bits - Function control register (address 28h) Bit Symbol 2 to 0 [1] COF[2:0] Value Frequency selection (Hz) CLK pin TS pin INTA pin 32 768 32 768 32 768 001 16 384 16 384 16 384 010 8 192 8 192 8 192 011 4 096 4 096 4 096 100 2 048 2 048 2 048 101 1 024 1 024 1 024 110 1 1 1 111 static LOW static LOW Hi-Z 000 [1] Default value. A programmable square wave is available at pin CLK. Operation is controlled by the COF[2:0] bits. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Pin CLK is a push-pull output and enabled at power-on. Pin CLK can be disabled by setting CLKPM = 1 in the Pin_IO register (Section 7.12). When disabled, the CLK pin is LOW. The selected clock frequency may also be output on the TS pin and the INTA pin. The CLKIV bit may be used to invert the clock output. CLKIV does not invert for the setting COF[2:0] = 111. The duty cycle of the selected clock is not controlled. However, due to the nature of the clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50:50. Table 58. Clock duty cycles COF[2:0] Frequency (Hz) Typical duty cycle 32 768 60 : 40 to 40 : 60 001 16 384 50 : 50 010 8 192 50 : 50 011 4 096 50 : 50 100 2 048 50 : 50 101 1 024 50 : 50 000 [2] PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 [1] © 2023 NXP B.V. All rights reserved. 50 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 58. Clock duty cycles...continued COF[2:0] Frequency (Hz) 110 1 111 static [1] [2] [3] Typical duty cycle [3] [1] 50 : 50 - Duty cycle definition: % HIGH-level time : % LOW-level time. Default values. The duty cycle of the CLKOUT when outputting 32,768 Hz could change from 60:40 to 40:60 depending on the detector since the 32,768 Hz is derived from the oscillator output which is not perfect. It could change from device to device and it depends on the silicon diffusion. There is nothing that can be done from outside the chip to influence the duty cycle. 1 Hz clock pulses are not affected by offset correction pulses. 7.14 Flags register Table 59. Flags - Flag status register (address 2Bh) bit description Bit 7 Symbol PIF Flag name Value Periodic Interrupt Flag Section 7.13.2 0 [1] Description read: periodic interrupt flag inactive write: periodic interrupt flag is cleared read: periodic interrupt flag active 1 write: periodic interrupt flag remains unchanged 6 A2F Alarm2 Flag Section 7.4 0 [1] read: alarm2 flag inactive write: alarm2 flag is cleared read: alarm2 flag active 1 write: alarm2 flag remains unchanged 5 A1F Alarm1 Flag Section 7.4 0 [1] read: alarm1 flag inactive write: alarm1 flag is cleared read: alarm1 flag active 1 write: alarm1 flag remains unchanged 4 WDF WatchDog Flag Section 7.5 0 [1] read: WatchDog flag inactive write: WatchDog flag is cleared read: WatchDog flag active 1 write: WatchDog flag remains unchanged 3 BSF Battery Switch Flag Section 7.11 0 [1] read: battery switch flag inactive write: battery switch flag is cleared read: battery switch flag active 1 write: battery switch flag remains unchanged 2 TSR3F Timestamp Register 3 event Flag Section 7.7 0 [1] read: timestamp register 3 flag inactive write: timestamp register 3 flag is cleared read: timestamp register 3 flag active 1 write: timestamp register 3 flag remains unchanged 1 TSR2F PCF85263A Product data sheet Timestamp Register 2 event Flag Section 7.7 0 [1] read: timestamp register 2 flag inactive write: timestamp register 2 flag is cleared 1 read: timestamp register 2 flag active All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 51 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 59. Flags - Flag status register (address 2Bh) bit description...continued Bit Symbol Flag name Value Description write: timestamp register 2 flag remains unchanged 0 TSR1F Timestamp Register 1 event Flag Section 7.7 0 [1] read: timestamp register 1 flag inactive write: timestamp register 1 flag is cleared read: timestamp register 1 flag active 1 write: timestamp register 1 flag remains unchanged [1] Default value. The flags are set by their respective function. A full description can be found there. All flags behave the same way. They are set by some function of the IC and remain set until overwritten by command. It is possible to clear flags individually. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access. All flags are combined to generate an event monitoring signal called EMON. EMON is described in Section 7.2.3 and can be read as the MSB of minutes register. 7.15 Reset register Table 60. Reset - software reset control (address 2Fh) bit description Bit 7 6 5 4 3 2 1 0 Symbol CPR 0 1 0 SR 1 0 CTS Section Section 7.15.2 Section 7.15.1 Section 7.15.3 For a • software reset (SR), 0010 1100 (2Ch) must be sent to register Reset (address 2Fh). A software reset also triggers CPR and CTS • clear prescaler (CPR), 1010 0100 (A4h) must be sent to register Reset (address 2Fh) • clear timestamp (CTS),0010 0101 (25h) must be sent to register Reset (address 2Fh) It is possible to combine CPR and CTS by sending 1010 0101 (A5h). Remark: Any other value sent to this register is ignored. 7.15.1 SR - Software reset A reset is automatically generated at power-on. A reset can also be initiated with the software reset command. target address SDA s 1 0 1 0 0 address 2Fh R/W 0 1 0 A 0 0 1 0 1 1 software reset 2Ch 1 1 A 0 0 1 0 1 1 0 0 A P/S SCL internal reset signal aaa-010473 Figure 31. Software reset command PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 52 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus The PCF85263A resets to: Mode: real-time clock, 100th second off Time: 00:00:00.00 Date: 2000.01.01 Weekday: Saturday Battery switch: on, switching on the lower threshold voltage Oscillator: CL = 7 pF Pins: INTA = 32 kHz output, CLK = 32 kHz output, TS = disabled In the reset state, all registers are set according to Table 61. Table 61. Registers reset values Registers labeled as - remain unchanged. Address Register name Bit 7 6 5 4 3 2 1 0 00h 100TH_seconds 0 0 0 0 0 0 0 0 01h Seconds 1 0 0 0 0 0 0 0 02h Minutes 0 0 0 0 0 0 0 0 03h Hours 0 0 0 0 0 0 0 0 04h Days 0 0 0 0 0 0 0 1 05h Weekdays 0 0 0 0 0 1 1 0 06h Months 0 0 0 0 0 0 0 1 07h Years 0 0 0 0 0 0 0 0 08h Second_alarm1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Second_alm1 09h Minute_alarm1 Minute_alm1 0Ah Hour_alarm1 Hr_xx_xx_00_alm1 0Bh Day_alarm1 Hr_xx_00_xx_alm1 0Ch Month_alarm1 Hr_00_xx_xx_alm1 0Dh Minute_alarm2 Minute_alm2 0Eh Hour_alarm2 Hr_xx_00_alm2 0Fh Weekday_alarm2 Hr_00_xx_alm2 PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 53 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 61. Registers reset values...continued Registers labeled as - remain unchanged. Address Register name Bit 7 6 5 4 3 2 1 0 10h Alarm enables 0 0 0 0 0 0 0 0 11h to 16h Timestamp 1 0 0 0 0 0 0 0 0 17h to 1Ch Timestamp 2 0 0 0 0 0 0 0 0 1Dh to 22h Timestamp 3 0 0 0 0 0 0 0 0 23h Timestamp_mode 0 0 0 0 0 0 0 0 24h Offset 0 0 0 0 0 0 0 0 25h Oscillator 0 0 0 0 0 0 0 0 26h Battery_switch 0 0 0 0 0 0 0 0 27h Pin_IO 0 0 0 0 0 0 0 0 28h Function 0 0 0 0 0 0 0 0 29h INTA_enable 0 0 0 0 0 0 0 0 2Ah INTB_enable 0 0 0 0 0 0 0 0 2Bh Flags 0 0 0 0 0 0 0 0 2Ch RAM_byte 0 0 0 0 0 0 0 0 2Dh WatchDog 0 0 0 0 0 0 0 0 2Fh Reset 0 0 0 0 0 0 0 0 7.15.2 CPR: clear prescaler To set the time for RTC mode accurately or to clear the time in stop-watch mode, the clear prescaler instruction is needed. Before sending this instruction, it is recommended to first set stop either by the STOP bit or by the TS pin (see STOPM bit). See STOP definition for an explanation on using this instruction. 7.15.3 CTS: clear timestamp The timestamp registers (address 11h to 22h) can be set to all 0 with this instruction. 7.16 Stop_enable register Table 62. Stop_enable - control of STOP bit (address 2Eh) Bit Symbol Value Description 7 to 1 0 - 0000 000 not used STOP bit STOP 0 1 [1] [1] RTC clock runs RTC clock is stopped Default value. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 54 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus The STOP bit stops the time from counting in both RTC mode and stop-watch mode. For RTC mode STOP is useful to set the time accurately. For stop-watch mode it is the start/stop control for the watch. The counter can also be controlled from the TS pin by configuring STOPM in the Function register (Section 7.13). The internal stop signal is a combination of STOP and the TS pin state. Table 63. Counter stop signal STOP bit TS pin 1 [1] [2] stop signal Counter - 1 stopped - 1 1 stopped 0 0 0 running [1] [2] Requires STOPM and TSPM[1:0] to be configured. TSL = 0 (active HIGH) (Pin_IO register, address 27h). OSCILLATOR STOP DETECTOR 32768 Hz OSCILLATOR div 4 8192 Hz setting the OS flag 0 PRESCALER 1 RESET 100 Hz tick 1 Hz tick CPR stop(1) aaa-010477 1. stop is a combination of STOP register bit and the TS pin when programmed for stop control. Figure 32. CPR and STOP bit functional diagram The stop signal blocks the 8.192 kHz clock from generating system clocks and freezes the time. In this state, the prescaler can be cleared with the CPR command in the Resets register (Section 7.15). Remark: The output of clock frequencies is not affected. The time circuits can then be set and do not increment until the STOP bit is released. 2 The stop acts on the 8.192 kHz signal. And because the I C-bus or TS pin input is asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is between zero and one 8.192 kHz cycle (see Figure 33). 8192 Hz stop released 0 µs to 122 µs aaa-004417 Figure 33. STOP release timing The first increment of the time circuits is between 0 s and 122 μs after STOP is released. The flow for accurately setting the time in RTC mode is: 2 • start an I C access at register 2Eh • set STOP bit PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 55 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus • • • • • • • • send CPR instruction address counter rolls over to address 00h set time (100th seconds, seconds to years) 2 end I C access wait for external time reference to indicate that time counting should start 2 start an I C access at register 2Eh clear STOP bit (time starts counting from now) 2 end I C access The flow for resetting time in stop-watch mode is: • • • • • • 2 start an I C access at register 2Eh set STOP bit send CPR instruction address counter will roll over to address 00h set time to 000000:00:00.00 2 end I C access 2 8 I C-bus interface 2 The I C-bus is for bidirectional, two-line communication between different ICs. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. Both data and clock lines remain HIGH when the bus is not busy. The PCF85263A acts as a target receiver when being written to and as a target transmitter when being read from. Remark: When on VBAT power, the interface is not accessible. Write S target address + 0 A ACK from target Read target address + 1 S write data A ACK from target A ACK from target read data ACK from controller write data A ACK from target A read data write data A P ACK from target A ACK from controller read data A P ACK from target aaa-010487 2 Figure 34. I C read and write protocol PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 56 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus I2C write example SCL SDA bit7 bit0 S START condition ACK 1st byte, target address with R/W = 0 bit7 bit0 ACK P write 2nd byte ACK of 2nd byte from target ACK of 1st byte from target STOP condition I2C read example SCL SDA bit7 bit0 S ACK 1st byte, target address with R/W = 1 START condition ACK of 1st byte from target bit7 bit0 ACK read 2nd byte ACK of 2nd byte from target P STOP condition aaa-010489 2 Figure 35. I C read and write signaling 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time are interpreted as STOP or START conditions. 8.2 START and STOP conditions A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 35). 8.3 Acknowledge Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as logic 0. A notacknowledge is defined as logic 1. When written to, the target will generate an acknowledge after the reception of each byte. After the acknowledge, another byte may be transmitted. It is also possible to send a STOP or START condition. When read from, the controller receiver must generate an acknowledge after the reception of each byte. When the controller receiver no longer requires bytes to be transmitter, it must generate a not-acknowledge. After the not-acknowledge, either a STOP or START condition must be sent. 2 A detailed description of the I C-bus specification is given in [8]. 9 Interface protocol 2 The PCF85263A uses the I C interface for data transfer. Interpretation of the data is determined by the interface protocol. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 57 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 9.1 Write protocol 2 After the I C target address is transmitted, the PCF85263A requires that the register address pointer is defined. It can take the value 00h to 2Fh. Values outside of that range will result in the transfer being ignored, however the target will still respond with acknowledge pulses. After the register address is transmitted, write data is transmitted. The minimum number of data write bytes is 0 and the maximum number is unlimited. After each write, the address pointer increments by one. After address 2Fh, the address pointer will roll over to 00h. • • • • • • • • 2 I C START condition 2 I C target address + write register address write data write data : write data 2 2 I C STOP condition; an I C RE-START condition is also possible. 9.2 Read protocol When reading the PCF85263A, reading starts at the current position of the address pointer. The address pointer for read data should first be defined by a write sequence. • • • • 2 I C START condition 2 I C target address + write register address 2 2 I C STOP condition; an I C RE-START condition is also possible. 2 After setting the address pointer, a read can be executed. After the I C target address is transmitted, the PCF85263A will immediately output read data. After each read, the address pointer increments by one. After address 2Fh, the address pointer will roll over to 00h. • • • • • • • 2 I C START condition 2 I C target address + read read data (controller sends acknowledge bit) read data (controller sends acknowledge bit) : read data (controller sends not-acknowledge bit) 2 2 I C STOP condition. An I C RE-START condition is also possible. The controller must indicate that the last byte has been read by generating a not-acknowledge after the last read byte. 9.3 Target addressing 9.3.1 Target address 2 2 One I C-bus target address (1010  001) is reserved for the PCF85263A. The entire I C-bus target address byte is shown in Table 64. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 58 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 2 Table 64. I C target address byte Target address Bit 7 6 5 4 3 2 1 MSB 1 0 LSB 0 1 0 0 0 1 R/W 2 After a START condition, the I C target address has to be sent to the PCF85263A device. Target address can also be written in a hexadecimal format: • A2h - Write target address • A3h - Read target address 10 Application design-in information In this application, stop-watch mode is used to implement an elapsed time counter. The TS pin is used with a mechanical switch to start and stop the time. Each time the time is stopped, timestamp2 is loaded with the current time and an interrupt is generated on the INTA pin. Time counter stop vdd_int mechanical switch detector STOPM STOP control sample clock, 16 Hz TSL TS pin TSR2 sample invert load TSR2 flag VSS INTA INTA gen. aaa-010560 Figure 36. Application example The RTC must be configured correctly for this mode of operation. Outlined in Table 65 are the settings needed for this mode. In addition, the time must be set and any other configurations like battery switch-over, quartz oscillator driving mode, etc., which are dependent on the application. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 59 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus The sampler circuit shown in Figure 36 will hold invalid data until the mechanical switch detector mode is enabled. It then requires a minimum of one sample period to initialize to the current TS pin level. It is recommended to enable the mechanical detector mode on the TS pin at least 62.5 ms before enabling the TS event mode. Failure to do so can result in a false first event. Table 65. Application configuration Register Section Bit(s) State Comment Pin_IO Section 7.12 TSPM[1:0] 11 TS pin in input mode Pin_IO Section 7.12 TSIM 1 select mechanical switch mode Pin_IO Section 7.12 TSL 1 TS pin input is active LOW Function Section 7.13 STOPM 1 allow TS pin to control STOP TSRIEA 1 allow timestamps to create interrupts ILPA 0 generate interrupt pulses TSR_mode Section 7.12 TSR2M[2:0] 101 last event mode for timestamp2 Pin_IO Section 7.12 INTAPM[1:0] 10 output interrupt on INTA Figure 37 shows the waveforms that can be expected. sample clock, vdd_int and stop are internal nodes. vdd_int is the supply which operates the IC and will be either VDD or VBAT, depending on the state of the battery switch-over. sample clock, 16 Hz vdd_int TS pin floating VSS TS pin sampled open switch SW 1 open closed stop stopwatch running stopped running TSR2 = t4 TSR2 INTA t1 t2 t3 t4 t5 t6 aaa-010561 Figure 37. Application example timing • At and before t1, SW1 is open (TS pin floating). The TS pin is sampled and the internal pull-up resistor will pull the pin HIGH to vdd_int. No actions are taken by the IC. • At t2, SW1 is still open. No action is taken by the IC. • At t3, SW1 closes. The TS pin is now shorted to VSS. The TS pin has not been sampled yet, so no action is taken by the IC. • At t4, SW1 is closed. The internal pull-up resistor is enabled, but TS pin remains LOW. The pin is then sampled and the LOW level detected. As the TSL bit was set for active LOW detection, the HIGH-LOW transition of TS pin sampled triggers an event. STOPM mode was configured to allow the TS pin to stop the time counting. As the TSL bit was set for active LOW, time counting stops when the TS pin is LOW. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 60 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Timestamp register 2 was configured to take a copy of the time on an event of the TS pin, hence TSR2 loads the time t4. TSR2F is also set. INTA was configured to generate an interrupt when TSR2 loads a new time, hence an interrupt pulse is seen on INTA. • At t5, SW1 is opened. No action is taken by the IC. • At t6, SW1 is open. The internal pull-up is active and the TS pin raises to vdd_int level. The HIGH level is sampled and causes the stop signal to be released and time starts counting again. 11 Internal circuitry PCF85263A VDD OSCI INTA OSCO CLK VBAT SCL TS SDA VSS aaa-010564 Figure 38. Device diode protection diagram of PCF85263A 12 Safety notes CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 61 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 13 Limiting values Table 66. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Min Max Unit supply voltage -0.5 +6.5 V IDD supply current -50 +50 mA VBAT battery supply voltage -0.5 +6.5 V IBAT battery supply current -50 +50 mA VI input voltage -0.5 +6.5 V VO output voltage -0.5 +6.5 V II input current at any input -10 +10 mA IO output current at any output -10 +10 mA Ptot total power dissipation - 300 mW - ±3500 V PCF85263AT - ±1500 V PCF85263ATL - ±1750 V PCF85263ATT - ±1000 V PCF85263ATT1 - ±2000 V VESD Conditions on pins SCL, SDA, OSCI, TS [1] electrostatic discharge HBM voltage CDM [2] PCF85263AUK - ±1000 V latch-up current [3] - 200 mA Tstg storage temperature [4] -65 +150 °C Tamb ambient temperature -40 +85 °C Ilu [1] [2] [3] [4] operating device Pass level; Human Body Model (HBM) according to [1]. Pass level; Charged-Device Model (CDM), according to [2]. Pass level; latch-up testing, according to [3] at maximum ambient temperature (Tamb(max)). According to the store and transport requirements (see [9]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. 14 Characteristics Table 67. Characteristics VDD = 0.9 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; all registers in reset state; unless otherwise specified. Symbol Parameter Conditions supply voltage interface inactive; fSCL = 0 Hz interface active; fSCL = 400 kHz Min Typ Max Unit [1] 0.9 - 5.5 V [2] 1.8 - 5.5 V [1] 0.9 - 5.5 V Supplies VDD VBAT battery supply voltage PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 62 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 67. Characteristics...continued VDD = 0.9 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; all registers in reset state; unless otherwise specified. Symbol IDD Parameter supply current Conditions Min Typ Max Unit Tamb = 25 °C - 320 480 nA Tamb = 50 °C - 370 550 nA - 590 885 nA Tamb = 25 °C - 280 420 nA Tamb = 50 °C - 330 500 nA Tamb = 85 °C - 550 825 nA CLKOUT disabled; VDD = 3.3 V; interface active; fSCL = 400 kHz - 10 - μA VDD ≥ VBAT - - 10 nA VDD < VBAT - - 100 nA HIGH falling VDD 2.4 2.6 2.8 V HIGH rising VDD 2.5 2.7 2.95 V LOW falling VDD 1.3 1.4 1.5 V LOW rising VDD 1.37 1.47 1.6 V reference voltage hysteresis - ±50 - mV CLKOUT disabled; VDD = 3.3 V; interface inactive; fSCL = 0 Hz [3] battery switch enabled Tamb = 85 °C battery switch disabled IL(BAT) battery leakage current [4] Reference voltage Vth Inputs threshold voltage [5] VI input voltage -0.5 - +5.5 V VIL LOW-level input voltage -0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V ILI input leakage current - 0 - μA VI = VSS or VDD post ESD event -0.5 - +0.5 μA input capacitance [6] - - 7 pF pull-up resistance on pin TS 80 kΩ mode [7] 68 80 92 kΩ 40 kΩ mode [7] 36 40 64 kΩ VOH HIGH-level output voltage on pin CLK, TS 0.8VDD - VDD V VOL LOW-level output voltage on pins SDA, INTA, CLK, TS VSS - 0.2VDD V Ci RPU(TS) Outputs PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 63 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 67. Characteristics...continued VDD = 0.9 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; all registers in reset state; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IOH HIGH-level output current output source current; VOH = 2.9 V; VDD = 3.3 V; on pin CLK, TS 1 3 - mA IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 3.3 V on pin SDA 3 8.5 - mA on pin INTA 2 6 - mA on pin CLK 1 3 - mA on pin TS 1 3 - mA - 0.075 - ppm - 50 - ns - 25 - ns CL = 6 pF 4.8 6 7.2 pF CL = 7 pF 5.6 7 8.4 pF 10 12.5 15 pF - 60 100 kΩ Oscillator Δfosc/fosc relative oscillator frequency variation ΔVDD = 200 mV; Tamb = 25 °C tjit jitter time LOWJ = 0 [8] LOWJ = 1 CL(itg) integrated load capacitance on pins OSCO, OSCI; VDD = 3.3 V [9] CL = 12.5 pF Rs [1] [2] [3] [4] [5] [6] [7] [8] [9] series resistance of the quartz; normal drive [10] For reliable oscillator start-up at power-on use VDD greater than 1.2 V. If powered up at 0.9 V the oscillator will start but it might be a bit slow, especially if at high temperature. Normally the power supply is not 0.9 V at start-up and only comes at the end of battery discharge. VDD min of 0.9 V is specified so that the customer can calculate how large a battery or capacitor they need for their application. VDD min of 1.2 V or greater is needed to ensure speedy oscillator start-up time. 400 kHz I2C operation is production tested at 1.8 V. Design methodology allows I2C operation at 1.8 V - 5 % (1.71 V) which has been verified during product characterization on a limited number of devices. Measured after reset and CLK disabled, level of inputs is VDD or VSS. Measured after reset, CLK disabled, battery switch disabled and level of inputs is VDD or VSS. 2 The I C-bus interface of PCF85263A is 5 V tolerant. Implicit by design. See Table 44. See Table 32. Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series. [10] See Table 33. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 64 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus IDD (µA) aaa-010605 30 25 20 15 10 5 0 0 100 200 300 400 FSCL (kHz) 500 Tamb = 25 °C; CLKOUT disabled. 1. VDD = 5.0 V. 2. VDD = 3.3 V. Figure 39. Typical IDD with respect to fSCL aaa-010602 900 IDD (nA) 750 600 (1) (2) 450 300 150 0 -60 -40 -20 0 20 40 60 80 Tamb (ºC) 100 CL(itg) = 7 pF; CLKOUT disabled; battery switched on. 1. VDD = 5 V. 2. VDD = 3.3 V. Figure 40. Typical IDD as a function of temperature PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 65 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus IDD (µA) aaa-010603 18 15 12 9 (1) 6 (2) (3) 3 0 0 1 2 3 4 5 VDD (V) 6 Tamb = 25 °C; fCLKOUT = 32 768 Hz. 1. 47 pF CLKOUT load. 2. 22 pF CLKOUT load. 3. 0 pF CLKOUT load. aaa-010604 600 IDD (nA) 500 400 (1) (2) (3) 300 200 100 0 0 1 2 3 4 5 VDD (V) 6 Tamb = 25 °C; CLKOUT disabled. 1. CL(itg) = 12.5 pF. 2. CL(itg) = 7 pF. 3. CL(itg) = 6 pF. Figure 41. Typical IDD with respect to VDD PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 66 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus aaa-010607 0.4 Δfosc/fosc (ppm) 0.2 0 (1) (2) (3) -0.2 -0.4 0 1 2 3 4 5 VDD (V) 6 Tamb = 25 °C. 1. CL(itg) = 12.5 pF. 2. CL(itg) = 6 pF. 3. CL(itg) = 7 pF. Figure 42. Oscillator frequency variation with respect to VDD 2 Table 68. I C-bus characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and [1] VIH with an input voltage swing of VSS to VDD . Symbol Parameter Cb capacitive load for each bus line fSCL SCL clock frequency tHD;STA Min Max Unit - 400 pF 0 400 kHz hold time (repeated) START condition 0.6 - μs tSU;STA set-up time for a repeated START condition 0.6 - μs tLOW LOW period of the SCL clock 1.3 - μs tHIGH HIGH period of the SCL clock 0.6 - μs tr rise time of both SDA and SCL signals 20 300 ns tf fall time of both SDA and SCL signals 20 × (VDD / 5.5 V) 300 ns tBUF bus free time between a STOP and START condition 1.3 - μs tSU;DAT data set-up time 100 - ns PCF85263A Product data sheet Conditions [2] [3] [4] All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 67 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 2 Table 68. I C-bus characteristics...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and [1] VIH with an input voltage swing of VSS to VDD . Symbol Parameter tHD;DAT Min Max Unit data hold time 0 - ns tSU;STO set-up time for STOP condition 0.6 - μs tVD;DAT data valid time 0 0.9 μs tVD;ACK data valid acknowledge time 0 0.9 μs tSP pulse width of spikes that must be suppressed by the input filter 0 50 ns [1] [2] [3] [4] Conditions 2 A detailed description of the I C-bus specification is given in [8]. 2 I C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH 1/f bit 0 (R/W) acknowledge (A) STOP condition (P) SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 013aaa417 2 Figure 43. I C-bus timing diagram; rise and fall times refer to 30 % and 70 % PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 68 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 15 Application information VDD 100 nF SDA SCL 100 nF VBAT CLK VDD INTA SCL OSCI OSCO CONTROLLER TRANSMITTER/ RECEIVER VDD PCF85263A SDA TS R VSS R R: pull-up resistor R= SDA SCL (I2C-bus) tr Cb aaa-010565 Figure 44. Application diagram for PCF85263A The data sheet values were obtained using a crystal with an ESR of 60 kΩ. If a crystal with an ESR of 70 kΩ is used then the power consumption would increase by a few nA and the start-up time will increase slightly. 16 Test information 16.1 Quality information UL Component Recognition This (component or material) is Recognized by UL. Representative samples of this component have been evaluated by UL and meet applicable UL requirements. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 69 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 17 Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.20 0.014 0.0075 0.19 0.16 0.15 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Figure 45. Package outline SOT96-1 (SO8), PCF85263AT PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 70 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus DFN2626-10: plastic thermal enhanced extremely thin small outline package; no leads; 10 terminals; body 2.6 x 2.6 x 0.5 mm SOT1197-1 X B D A E A A1 A3 terminal 1 index area detail X e1 terminal 1 index area e 1 5 C C A B C v w b y1 C y L k Eh 10 6 Dh 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A A1 0.5 0.05 A3 b 0.30 0.127 0.25 0.00 0.20 D Dh E Eh e e1 2.7 2.6 2.5 2.20 2.15 2.10 2.7 2.6 2.5 1.30 1.25 1.20 0.5 2 k L v 0.2 0.40 0.35 0.30 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1197-1 --- --- --- sot1197-1_po European projection Issue date 11-01-20 12-09-16 Figure 46. Package outline SOT1197-1 (DFN2626-10), PCF85263ATL PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 71 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Figure 47. Package outline SOT505-1 (TSSOP8), PCF85263ATT PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 72 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm D E SOT552-1 A X c y HE v M A Z 6 10 A2 pin 1 index (A3) A1 A θ Lp L 1 5 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.15 0.23 0.15 3.1 2.9 3.1 2.9 0.5 5.0 4.8 0.95 0.7 0.4 0.1 0.1 0.1 0.67 0.34 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-07-29 03-02-18 SOT552-1 Figure 48. Package outline SOT552-1 (TSSOP10), PCF85263ATT1 PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 73 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Figure 49. Package outline SOT2035-1 (WLCSP12), PCF85263AUK 1 of 2 PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 74 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Figure 50. Package outline SOT2035-1 (WLCSP12), PCF85263AUK 2 of 2 PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 75 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 18 Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC  61340-5 or equivalent standards. 19 Packing information For tape and reel packing information, please see [4], [5], [6], and [7] in Section 24. 20 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 20.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 20.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 20.3 Wave soldering Key characteristics in wave soldering are: PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 76 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 20.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 51) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 69 and Table 70 Table 69. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 70. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 51. PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 77 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 51. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 21 Footprint information 5.50 0.60 (8×) 1.30 4.00 6.60 7.00 1.27 (6×) solder lands occupied area placement accuracy ± 0.25 Dimensions in mm sot096-1_fr Figure 52. Footprint information for reflow soldering of SOT96-1 (SO8), PCF85263AT PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 78 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Footprint information for reflow soldering of DFN2626-10 package SOT1197-1 Hx Gx D P 0.025 0.025 Ay Gy By SPy SLy nSPy Hy nSPx SPx SLx Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS in mm P Ay 0.5 3.05 Issue date By D SLx SLy SPx SPy Gx Gy Hx Hy 1.9 0.25 2.2 1.3 0.8 0.4 2.5 2.85 2.85 3.3 11-07-27 12-09-16 sot1197-1_fr Figure 53. Footprint information for reflow soldering of SOT1197-1 (DFN2626-10),PCF85263ATL PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 79 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 3.600 2.950 0.725 0.125 0.125 5.750 3.600 3.200 5.500 1.150 0.600 0.450 0.650 solder lands occupied area Dimensions in mm sot505-1_fr Figure 54. Footprint information for reflow soldering of SOT505-1 (TSSOP8),PCF85263ATT PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 80 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Footprint information for reflow soldering of TSSOP10 package SOT552 -1 Hx P1 Hy Gy solder land occupied area Dimensions in mm Gy Hy Hx P1 3.1 5.0 3.1 0.5 Issue date 11-04-19 13-05-02 sot552-1_fr Figure 55. Footprint information for reflow soldering of SOT552-1 (TSSOP10), PCF85263ATT1 PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 81 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 22 Appendix 22.1 Real-Time Clock selection Table 71. Selection of Real-Time Clocks Type name Alarm, Timer, Watchdog Interrupt output Interface IDD, typical (nA) Battery backup Timestamp, tamper input AEC-Q100 compliant Special features Packages PCF8563 X 1 I C 2 250 - - - - SO8, TSSOP8, HVSON10 PCF8564A X 1 I C 2 PCA8565 X 1 250 - - - integrated oscillator caps WLCSP I C 2 600 - - grade 1 high robustness, Tamb= -40 °C to 125 °C TSSOP8, HVSON10 PCA8565A X 1 I C 2 600 - - - integrated oscillator caps, Tamb= -40 °C to 125 °C WLCSP PCF85063 - 1 I C 2 PCF85063A X 1 220 - - - basic functions only, no alarm HXSON8 I C 2 220 - - - tiny package PCF85063B X SO8, DFN2626-10 1 SPI 220 - - - tiny package PCF85263A DFN2626-10 X 2 I C 230 X X - time stamp, battery backup, 1 stopwatch ⁄100 s SO8, TSSOP10, TSSOP8, DFN2626-10 PCF85263B X 2 SPI 230 X X - time stamp, battery backup, 1 stopwatch ⁄100s TSSOP10, DFN2626-10 PCF85363A X 2 I C 230 X X - time stamp, battery backup, 1 stopwatch ⁄100s, 64 Byte RAM TSSOP10, DFN2626-10 PCF85363B X 2 SPI 230 X X - time stamp, battery backup, 1 stopwatch ⁄100s, 64 Byte RAM TSSOP10, DFN2626-10 PCF8523 X 2 I C 150 X - - lowest power 150 nA in operation, FM+ 1 MHz SO8, HVSON8, TSSOP14, WLCSP PCF2123 X 1 SPI 100 - - - lowest power 100 nA in operation TSSOP14, HVQFN16 PCF2127 X 1 I C and SPI 2 500 X X - temperature compensated, quartz built in, calibrated, 512 Byte RAM SO16 PCF2127A X 1 I C and SPI 2 500 X X - temperature compensated, quartz built in, calibrated, 512 Byte RAM SO20 PCF2129 X 1 I C and SPI 2 500 X X - temperature compensated, quartz built in, calibrated SO16 PCF2129A X 1 I C and SPI 2 500 X X - temperature compensated, quartz built in, calibrated SO20 PCA2129 X 1 I C and SPI 2 500 X X grade 3 temperature compensated, quartz built in, calibrated SO16 PCA21125 X 1 SPI 820 - - grade 1 high robustness, Tamb= -40 °C to 125 °C TSSOP14 2 2 2 23 Abbreviations Table 72. Abbreviations Acronym Description BCD Binary Coded Decimal CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model 2 I C Inter-Integrated Circuit IC Integrated Circuit LSB Least Significant Bit PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 82 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Table 72. Abbreviations...continued Acronym Description MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board POR Power-On Reset RTC Real-Time Clock SCL Serial CLock line SDA Serial DAta line SMD Surface Mount Device 24 References [1] [2] [3] [4] [5] [6] [7] [8] [9] JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-C101 Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components JESD78 IC Latch-Up Test SOT96-1_118 SO8; Reel pack; SMD, 13", packing information SOT505-1_118 TSSOP8; Reel pack; SMD, 13", packing information SOT552-1_118 TSSOP10; Reel pack; SMD, 13", packing information SOT1197-1_115 DFN2626-10; Reel pack; SMD, 7", packing information 2 UM10204 I C-bus specification and user manual UM10569 Store and transport requirements 25 Revision history Table 73. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF85263A v.5.3 20231122 Product data sheet - PCF85263A v.5.2 • Table 67: Added spec for IL(BAT) battery leakage current PCF85263A v.5.2 20210922 Product data sheet 202104010DN PCF85263A v.5.1 PCF85263A v.5.1 20210618 Product data sheet 202104008A PCF85263A v.5 PCF85263A v.5 20210201 Product data sheet - PCF85263A v.4.1 PCF85263A v.4.1 20151127 Product data sheet - PCF85263A v.4 PCF85263A v.4 20151118 Product data sheet - PCF85263A v.3 PCF85263A v.3 20150116 Product data sheet - PCF85263A v.2 PCF85263A v.2 20140710 Product data sheet - PCF85263A v.1 PCF85263A v.1 20140418 Product data sheet - - PCF85263A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 83 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Legal information Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. 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NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCF85263A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 84 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. PCF85263A Product data sheet Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 85 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. Tab. 19. Tab. 20. Tab. 21. Tab. 22. Tab. 23. Tab. 24. Tab. 25. Tab. 26. Tab. 27. Tab. 28. Tab. 29. Tab. 30. Tab. 31. Tab. 32. Tab. 33. Tab. 34. Tab. 35. Tab. 36. Ordering information ..........................................2 Ordering options ................................................2 Pin description ...................................................5 RTC mode time registers .................................. 7 Stop-watch mode time registers ........................8 Control and function registers overview ............ 9 Time and date registers in RTC mode (RTCM = 0) ..................................................... 10 BCD coding ..................................................... 11 Weekday assignments .................................... 12 Month assignments in BCD format ..................12 Time registers in stop-watch mode (RTCM = 1) ..................................................................14 Alarm1 and alarm2 registers in RTC mode coded in BCD (RTCM = 0) ..............................15 Alarm_enables- alarm enable control register (address 10h) bit description .............. 16 Alarm1 and alarm2 registers in stop-watch mode coded in BCD (RTCM = 1) .................... 19 Alarm_enables- alarm enable control register (address 10h) bit description .............. 19 WatchDog - WatchDog control and register (address 2Dh) bit description .......................... 22 WatchDog durations ........................................ 22 RAM_byte - 8-bit RAM register (address 2Ch) bit description ......................................... 24 TSR_mode - timestamp mode control register (address 23h) bit description .............. 25 Timestamp registers in RTC mode (RTCM = 0) ..................................................................27 Timestamp registers in stop-watch mode (RTCM = 1) ..................................................... 28 Offset - offset register (address 24h) bit description ....................................................... 29 OFFM bit - oscillator control register (address 25h) .................................................. 29 Offset values ................................................... 29 Correction pulses for OFFM = 0 ......................30 Correction pulses for OFFM = 1 ......................31 INTA and INTB interrupt control bits ................33 Definition of interrupt control bits .....................33 Oscillator - oscillator control register (address 25h) bit description ...........................37 CLKIV bit - oscillator control register (address 25h) .................................................. 37 12_24 bit - oscillator control register (address 25h) .................................................. 37 LOWJ bit - oscillator control register (address 25h) .................................................. 37 OSCD[1:0] bits - oscillator control register (address 25h) .................................................. 38 CL[1:0] bits - oscillator control register (address 25h) .................................................. 38 IO pin behavior in battery mode ......................39 Battery_switch - battery switch control (address 26h) bit description ...........................39 PCF85263A Product data sheet Tab. 37. Tab. 38. Tab. 39. Tab. 40. Tab. 41. Tab. 42. Tab. 43. Tab. 44. Tab. 45. Tab. 46. Tab. 47. Tab. 48. Tab. 49. Tab. 50. Tab. 51. Tab. 52. Tab. 53. Tab. 54. Tab. 55. Tab. 56. Tab. 57. Tab. 58. Tab. 59. Tab. 60. Tab. 61. Tab. 62. Tab. 63. Tab. 64. Tab. 65. Tab. 66. Tab. 67. Tab. 68. Tab. 69. Tab. 70. Tab. 71. Tab. 72. BSOFF bit - battery switch control (address 26h) bit description ..........................................39 BSRR bit - battery switch control (address 26h) bit description ..........................................39 BSM[1:0] bits - battery switch control (address 26h) bit description ...........................40 Battery switch-over modes .............................. 40 BSTH - battery switch control (address 26h) bit description ..........................................44 Pin_IO- pin input output control register (address 27h) bit description ...........................44 CLKPM bit - Pin_IO control register (address 27h) .................................................. 44 TSPULL bit - Pin_IO control register (address 27h) .................................................. 45 TSL bit - Pin_IO control register (address 27h) ................................................................. 45 TSPM[1:0] bits - Pin_IO control register (address 27h) .................................................. 45 TSIM bit - Pin_IO control register (address 27h) ................................................................. 46 INTAPM[1:0] bits - Pin_IO control register (address 27h) .................................................. 47 INTA battery mode .......................................... 48 Function - chip function control register (address 28h) bit description ...........................48 100TH bit - Function control register (address 28h) .................................................. 48 PI[1:0] bits - Function control register (address 28h) .................................................. 48 RTCM bit - Function control register (address 28h) .................................................. 49 RTC time counting modes ...............................49 STOPM bit - Function control register (address 28h) .................................................. 49 Oscillator stop control when STOPM = 1 .........49 COF[2:0] bits - Function control register (address 28h) .................................................. 50 Clock duty cycles ............................................ 50 Flags - Flag status register (address 2Bh) bit description .................................................. 51 Reset - software reset control (address 2Fh) bit description ......................................... 52 Registers reset values .....................................53 Stop_enable - control of STOP bit (address 2Eh) ................................................................. 54 Counter stop signal ......................................... 55 I2C target address byte ...................................59 Application configuration ................................. 60 Limiting values ................................................ 62 Characteristics .................................................62 I2C-bus characteristics ....................................67 SnPb eutectic process (from J-STD-020D) ..... 77 Lead-free process (from J-STD-020D) ............ 77 Selection of Real-Time Clocks ........................ 82 Abbreviations ...................................................82 All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 86 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Tab. 73. Revision history ...............................................83 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Fig. 16. Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Fig. 26. Fig. 27. Fig. 28. Fig. 29. Fig. 30. Fig. 31. Fig. 32. Block diagram of PCF85263A ...........................3 Pin configuration for PCF85263AT (SO8) ......... 4 Pin configuration for PCF85263ATL (DFN2626-10) ....................................................4 Pin configuration for PCF85263ATT (TSSOP8) .......................................................... 4 Pin configuration for PCF85263ATT1 (TSSOP10) ........................................................ 5 Pin configuration for PCF85263AUK (WLCSP12) ....................................................... 5 Address register incrementing ...........................6 Register map .....................................................6 Time mode register set selection ...................... 7 OS status bit ................................................... 11 Data flow for the time function ........................ 13 Data flow for the stop-watch function .............. 15 Alarm1 and alarm2 function block diagram (RTC mode) .................................................... 18 Alarm1 and alarm2 function block diagram (stop-watch mode) ...........................................21 WatchDog repeat mode .................................. 23 WatchDog single shot mode ........................... 24 Timestamp ....................................................... 25 Example battery switch-over timestamp ..........26 Example TS pin driven timestamp .................. 27 Offset calibration calculation workflow .............32 Result of offset calibration ...............................32 Interrupt pulse width ........................................35 Interrupt selection ............................................36 Threshold voltage switching hysteresis ........... 41 Switching at Vth .............................................. 41 Switching at VBAT .......................................... 42 Switching at the higher of VBAT or Vth ........... 43 Switching at the lower of VBAT or Vth .............43 TS pin ..............................................................46 INTA pin .......................................................... 47 Software reset command ................................ 52 CPR and STOP bit functional diagram ............ 55 PCF85263A Product data sheet Fig. 33. Fig. 34. Fig. 35. Fig. 36. Fig. 37. Fig. 38. Fig. 39. Fig. 40. Fig. 41. Fig. 42. Fig. 43. Fig. 44. Fig. 45. Fig. 46. Fig. 47. Fig. 48. Fig. 49. Fig. 50. Fig. 51. Fig. 52. Fig. 53. Fig. 54. Fig. 55. STOP release timing ....................................... 55 I2C read and write protocol .............................56 I2C read and write signaling ........................... 57 Application example ........................................ 59 Application example timing ............................. 60 Device diode protection diagram of PCF85263A ..................................................... 61 Typical IDD with respect to fSCL .....................65 Typical IDD as a function of temperature ........ 65 Typical IDD with respect to VDD ..................... 66 Oscillator frequency variation with respect to VDD ............................................................ 67 I2C-bus timing diagram; rise and fall times refer to 30 % and 70 % .................................. 68 Application diagram for PCF85263A ............... 69 Package outline SOT96-1 (SO8), PCF85263AT ................................................... 70 Package outline SOT1197-1 (DFN2626-10), PCF85263ATL ........................ 71 Package outline SOT505-1 (TSSOP8), PCF85263ATT .................................................72 Package outline SOT552-1 (TSSOP10), PCF85263ATT1 ...............................................73 Package outline SOT2035-1 (WLCSP12), PCF85263AUK 1 of 2 ..................................... 74 Package outline SOT2035-1 (WLCSP12), PCF85263AUK 2 of 2 ..................................... 75 Temperature profiles for large and small components ..................................................... 78 Footprint information for reflow soldering of SOT96-1 (SO8), PCF85263AT ........................78 Footprint information for reflow soldering of SOT1197-1 (DFN2626-10),PCF85263ATL ...... 79 Footprint information for reflow soldering of SOT505-1 (TSSOP8),PCF85263ATT ..............80 Footprint information for reflow soldering of SOT552-1 (TSSOP10), PCF85263ATT1 .........81 All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 87 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.1.1 7.1.1.1 7.1.1.2 7.1.2 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3 7.3.1 7.4 7.4.1 7.4.1.1 7.4.1.2 7.4.1.3 7.4.2 7.4.2.1 7.4.2.2 7.4.2.3 7.4.3 7.5 7.5.1 7.5.1.1 7.5.1.2 7.5.1.3 7.6 7.7 7.7.1 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.9 7.9.1 7.9.2 General description ......................................... 1 Features and benefits ..................................... 1 Applications ..................................................... 1 Ordering information .......................................2 Ordering options ................................................ 2 Block diagram ..................................................3 Pinning information .........................................4 Pinning ............................................................... 4 Pin description ................................................... 5 Functional description .................................... 6 Registers organization overview ........................7 Time mode registers ..........................................7 RTC mode time registers overview (RTCM = 0) .................................................................... 7 Stop-watch mode time registers (RTCM = 1) ........................................................................8 Control registers overview ................................. 9 RTC mode time and date registers ..................10 Definition of BCD .............................................10 OS: Oscillator stop .......................................... 11 EMON: event monitor ...................................... 11 Definition of weekdays .....................................12 Definition of months .........................................12 Setting and reading the time in RTC mode ...... 12 Stop-watch mode time registers ...................... 14 Setting and reading the time in stop-watch mode ................................................................ 14 Alarms ..............................................................15 Alarms in RTC mode ....................................... 15 Alarm1 and alarm2 registers in RTC mode ......15 Alarm1 and alarm2 control in RTC mode .........16 Alarm1 and alarm2 function in RTC mode ....... 17 Alarms in stop-watch mode ............................. 18 Alarm1 and alarm2 registers in stop-watch mode ................................................................ 19 Alarm1 and alarm2 control in stop-watch mode ................................................................ 19 Alarm1 and alarm2 function in stop-watch mode ................................................................ 20 Alarm interrupts ............................................... 21 WatchDog ........................................................ 22 WatchDog functions .........................................22 WatchDog repeat mode ...................................23 WatchDog single shot mode ............................23 WatchDog interrupts ........................................ 24 RAM byte .........................................................24 Timestamps ......................................................24 Timestamps interrupts ..................................... 29 Offset register .................................................. 29 Correction when OFFM = 0 .............................30 Correction when OFFM = 1 .............................31 Offset calibration workflow ...............................31 Offset interrupts ............................................... 33 Interrupts ..........................................................33 ILPA/ILPB: interrupt level or pulse mode ......... 34 Interrupt enable bits .........................................35 PCF85263A Product data sheet 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 7.11 7.11.1 7.11.2 7.11.3 7.11.3.1 7.11.3.2 7.11.3.3 7.11.3.4 7.11.4 7.11.5 7.12 7.12.1 7.12.2 7.12.3 7.12.4 7.12.4.1 7.12.4.2 7.12.4.3 7.12.5 7.12.5.1 7.12.6 7.12.6.1 7.12.6.2 7.12.6.3 7.13 7.13.1 7.13.2 7.13.3 7.13.4 7.13.5 7.14 7.15 7.15.1 7.15.2 7.15.3 7.16 8 8.1 8.2 8.3 9 9.1 9.2 9.3 9.3.1 10 11 Oscillator register .............................................37 CLKIV: invert the clock output ......................... 37 OFFM: offset calibration mode ........................ 37 12_24: 12 hour or 24 hour clock ......................37 LOWJ: low jitter mode ..................................... 37 OSCD[1:0]: quartz oscillator drive control ........ 38 CL[1:0]: quartz oscillator load capacitance ...... 38 Battery switch register ..................................... 38 BSOFF: battery switch on/off control ............... 39 BSRR: battery switch internal refresh rate ....... 39 BSM[1:0]: battery switch mode ........................ 40 Switching at the Vth level, BSM[1:0] = 00 ........ 41 Switching at the VBAT level, BSM[1:0] = 01 .... 42 Switching at the higher of VBAT or Vth level, BSM[1:0] = 10 ........................................ 42 Switching at the lower of VBAT and Vth level, BSM[1:0] = 11 ........................................ 43 BSTH: threshold voltage control ...................... 44 Battery switch interrupts .................................. 44 Pin_IO register .................................................44 CLKPM: CLK pin mode control ........................44 TSPULL: TS pin pull-up resistor value .............45 TSL: TS pin level sense .................................. 45 TSPM[1:0]: TS pin I/O control ......................... 45 TS pin output mode; INTB ...............................46 TS pin output mode; CLK ................................46 TS pin disabled ................................................46 TSIM: TS pin input type control ....................... 46 TS pin input mode ........................................... 47 INTAPM[1:0]: INTA pin mode control ............... 47 INTAPM[1:0]: INTA .......................................... 47 INTAPM[1:0]: clock data .................................. 47 INTAPM[1:0]: battery mode indication ............. 48 Function register .............................................. 48 100TH: 100th seconds mode .......................... 48 PI[1:0]: Periodic interrupt ................................. 48 RTCM: RTC mode ...........................................49 STOPM: STOP mode control .......................... 49 COF[2:0]: Clock output frequency ................... 50 Flags register ...................................................51 Reset register .................................................. 52 SR - Software reset .........................................52 CPR: clear prescaler ....................................... 54 CTS: clear timestamp ...................................... 54 Stop_enable register ........................................54 I2C-bus interface ............................................56 Bit transfer ....................................................... 57 START and STOP conditions .......................... 57 Acknowledge ....................................................57 Interface protocol .......................................... 57 Write protocol ...................................................58 Read protocol .................................................. 58 Target addressing ............................................ 58 Target address .................................................58 Application design-in information ................59 Internal circuitry .............................................61 All information provided in this document is subject to legal disclaimers. Rev. 5.3 — 22 November 2023 © 2023 NXP B.V. All rights reserved. 88 / 89 PCF85263A NXP Semiconductors 2 Tiny RTC/calendar with alarm function, battery switch-over, time stamp input, and I C-bus 12 13 14 15 16 16.1 17 18 19 20 20.1 20.2 20.3 20.4 21 22 22.1 23 24 25 Safety notes ................................................... 61 Limiting values ...............................................62 Characteristics ............................................... 62 Application information ................................ 69 Test information .............................................69 Quality information ...........................................69 Package outline ............................................. 70 Handling information .....................................76 Packing information ...................................... 76 Soldering of SMD packages ......................... 76 Introduction to soldering ............................. Wave and reflow soldering ......................... Wave soldering ........................................... Reflow soldering ......................................... Footprint information .................................... 78 Appendix .........................................................82 Real-Time Clock selection ............................... 82 Abbreviations ................................................. 82 References ......................................................83 Revision history .............................................83 Legal information ...........................................84 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2023 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 22 November 2023 Document identifier: PCF85263A