PMN50XP,165

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia PMN50XP P-channel TrenchMOS extremely low level FET Rev. 02 — 2 October 2007 Product data sheet 1. Product profile 1.1 General description Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features „ Low on-state losses „ Low threshold voltage 1.3 Applications „ Battery management „ Load Switching „ Battery powered portable equipment „ Low power DC to DC converters 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - -20 V ID drain current VGS = -4.5 V; Tsp = 25 °C; see Figure 1 and 3 - - -4.8 A VGS = -4.5 V; ID = -4.7 A; VDS = -10 V; Tj = 25 °C; see Figure 9 and 10 - 1.3 - nC VGS = -4.5 V; ID = -2.8 A; Tj = 25 °C; see Figure 7 and 8 - 48 60 mΩ Dynamic characteristics QGD gate-drain charge Static characteristics RDSon drain-source on-state resistance PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 2. Pinning information Table 2. Pinning Pin Symbol Description 1 D drain 2 D drain 3 G gate 4 S source 5 D drain 6 D drain Simplified outline Graphic Symbol 6 5 4 1 2 3 D G S 003aaa671 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PMN50XP TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit - -20 V VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ VDGR drain-gate voltage VGS gate-source voltage ID drain current - -20 V -12 12 V Tsp = 25 °C; VGS = -4.5 V; see Figure 1 and 3 - -4.8 A Tsp = 100 °C; VGS = -4.5 V - -3 A IDM peak drain current Tsp = 25 °C; tp < 10 μs; pulsed; see Figure 3 - -19.4 A Ptot total power dissipation Tsp = 25 °C; see Figure 2 - 2.2 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tsp = 25 °C - -1.9 A ISM peak source current Tsp = 25 °C; tp ≤ 10 μs; pulsed - -7.5 A PMN50XP_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 2 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 03aa25 120 03aa17 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 Ider = 50 ID ID(25°C ) 100 150 Tsp (°C) 200 0 × 100 % 50 P der = Fig 1. Normalized continuous drain current as a function of solder point temperature P tot P tot (25°C ) 100 Tsp (°C) 200 × 100 % Fig 2. Normalized total power dissipation as a function of solder point temperature 001aae333 −102 ID (A) 150 Limit RDSon = −VDS/−ID tp = 10 μs 100 μs −10 1 ms −1 10 ms DC 100 ms −10−1 −10−1 −1 −10 −102 VDS (V) Ts p = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PMN50XP_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 3 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance see Figure 4 from junction to solder point Min Typ Max Unit - - 55 K/W 03aj69 102 Zth(j-sp) (K/W) δ = 0.5 0.2 10 0.1 δ= P 0.05 tp T 0.02 single pulse t tp T 1 10-4 10-3 10-2 10-1 1 10 tp (s) 102 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit ID = -250 μA; VGS = 0 V; Tj = 25 °C -20 - - V ID = -250 μA; VGS = 0 V; Tj = -55 °C -18 - - V -0.55 -0.75 -0.95 V ID = -0.25 mA; VDS = VGS; Tj = 150 °C; see Figure 5 and 6 -0.35 - - V ID = -0.25 mA; VDS = VGS; Tj = -55 °C; see Figure 5 and 6 - - -1.1 V VDS = -20 V; VGS = 0 V; Tj = 25 °C - - -1 μA VDS = -20 V; VGS = 0 V; Tj = 70 °C - - -5 μA Static characteristics V(BR)DSS VGS(th) IDSS drain-source breakdown voltage gate-source threshold ID = -0.25 mA; VDS = VGS; voltage Tj = 25 °C; see Figure 5 and 6 drain leakage current PMN50XP_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 4 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit IGSS gate leakage current VGS ≤ 12 V; VDS = 0 V; Tj = 25 °C - -10 -100 nA VGS ≥ 12 V; VDS = 0 V; Tj = 25 °C - -10 -100 nA VGS = -4.5 V; ID = -2.8 A; Tj = 25 °C; see Figure 7 and 8 - 48 60 mΩ VGS = -4.5 V; ID = -2.8 A; Tj = 150 °C; see Figure 7 and 8 - 77 96 mΩ VGS = -2.5 V; ID = -2.3 A; Tj = 25 °C; see Figure 7 and 8 - 65 80 mΩ RDSon drain-source on-state resistance Dynamic characteristics QG(tot) total gate charge ID = -4.7 A; VDS = -10 V; VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 - 10 - nC QGS gate-source charge ID = -4.7 A; VDS = -10 V; VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 - 2.2 - nC QGD gate-drain charge ID = -4.7 A; VDS = -10 V; VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 - 1.3 - nC Ciss input capacitance VDS = -20 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 11 - 1020 - pF Coss output capacitance VGS = 0 V; VDS = -20 V; f = 1 MHz; Tj = 25 °C; see Figure 11 - 140 - pF Crss reverse transfer capacitance VDS = -20 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 11 - 100 - pF td(on) turn-on delay time RG(ext) = 6 Ω; RL = 10 Ω; VDS = -10 V; VGS = -4.5 V; Tj = 25 °C - 8.5 - ns tr rise time RG(ext) = 6 Ω; RL = 10 Ω; VDS = -10 V; VGS = -4.5 V; Tj = 25 °C - 7.5 - ns td(off) turn-off delay time VDS = -10 V; RL = 10 Ω; VGS = -4.5 V; RG(ext) = 6 Ω; Tj = 25 °C - 82 - ns tf fall time RG(ext) = 6 Ω; RL = 6 Ω; VDS = -10 V; VGS = -4.5 V; Tj = 25 °C - 35 - ns VGS(pl) gate-source plateau voltage VDS = -10 V; ID = -4.7 A; Tj = 25 °C; see Figure 9 and 10 - -1.6 - V Source-drain diode VSD source-drain voltage IS = -1.7 A; VGS = 0 V; Tj = 25 °C - -0.77 -1.2 V trr reverse recovery time IS = 3.5 A; dIS/dt = -100 A/μs; VGS = 0 V; VDS = 20 V; Tj = 25 °C - - - ns PMN50XP_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 5 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 03ar95 -1.2 VGS(th) (V) -0.8 001aae334 −10−3 max ID (A) typ −10−4 min min typ max −10−5 -0.4 0 -60 0 60 120 Tj (°C) 180 −10−6 ID = í0.25 m A; VDS = VGS −0.2 −0.4 −0.6 −0.8 −1.0 VGS (V) T j = 25 °C; VDS = í5 V Fig 5. Gate-source threshold voltage as a function of junction temperature Fig 6. Sub-threshold drain current as a function of gate-source voltage 03aq05 150 0 03aq10 2 VGS (V) = -2 RDSon (mΩ) a 120 1.5 -2.5 90 -3 -3.5 -4.5 60 1 0.5 30 0 0 -5 -10 -15 ID (A) -20 T j = 25 °C 0 -60 a= Fig 7. Drain-source on-state resistance as a function of drain current; typical values 60 120 Tj (°C) 180 R DSon R DSon (25°C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature PMN50XP_2 Product data sheet 0 © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 6 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 03aq09 -5 ID = -4.7 A Tj = 25 °C VDS = -10 V VGS (V) -4 VDS ID -3 VGS(pl) -2 VGS(th) VGS -1 QGS1 QGS2 QGS 0 0 4 8 QG (nC) 12 QGD QG(tot) 003aaa508 ID = í4.7 A; T j = 25 °C; VDS = í10 V Fig 9. Gate-source voltage as a function of gate charge; typical values Fig 10. Gate charge waveform definitions 001aae335 104 C (pF) 103 Ciss 102 Coss Crss 10 −10−1 −1 −10 VDS (V) −102 VGS = 0 V; f = 1 M H z Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PMN50XP_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 7 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 7. Package outline Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 5 X v M A 4 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A1 bp c D E e HE Lp Q v w y 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT457 JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 12. Package outline SOT457 (TSOP6) PMN50XP_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 8 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PMN50XP_2 20071002 Product data sheet - PMN50XP_1 Modifications: PMN50XP_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the company name where appropriate. 20060123 Product data sheet PMN50XP_2 Product data sheet - - © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 9 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com PMN50XP_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 2 October 2007 10 of 11 PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 October 2007 Document identifier: PMN50XP_2