PNX9530E/V120,557

R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D D R R R D D Software enabled video and multimedia entertainment platform F FT FT A A Preliminary data sheet A Rev. 01.11C — 1 October 2009 D D D D D PNX9530; PNX9531; PNX9535 D FT FT A A R R D D D R A FT D R A 1. General description The PNX9530; PNX9531; PNX9535 is a software enabled video and multimedia entertainment platform that provides video playback from a wide range of video sources and different video formats. The PNX9530; PNX9531; PNX9535 has an outstanding array of proprietary video post processing algorithms. 2. Features PA D EN NY TI A L The PNX9530; PNX9531; PNX9535 is a true multimedia platform enabling Graphical User Interface (GUI), connectivity and advanced audio processing, qualified for automotive applications. M 2.1 Software enabled video and multimedia entertainment platform C O N FI C O n Fixed basic hardware platform u Digital video input and output u Digital audio output u DDR2 SDRAM interface (JEDEC compliant) u USB 2.0 u I2C-bus n Built-in flexibility for multimedia processing through programmable GPIO interfaces u Digital video input and output u Digital audio input and output n Built-in flexibility for connectivity through programmable GPIO interfaces u EXtended I/O functions (XIO) for Hard Disc Drives (HDD), CD or DVD u Host interface u PCI 2.2 u USB High-Speed On-The-Go (OTG) u Clocks and generic signals D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT Decodes two video streams in parallel Renders each video stream on different video screens Independent control of each video stream Independent On-Screen Display (OSD) for each video stream A A A A R R D D D 2.2 Dual video MPEG decoding and rendering FT FT FT FT FT Software enabled video and multimedia entertainment platform n n n n A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D R A 2.3 Video quality FI C O M PA D EN NY TI A L n Outstanding array of proprietary video post-processing algorithms (available on dedicated request and commercial agreement; please contact NXP; see Section 22) for: u Color correction u Image noise reduction u Sharpness enhancement u Natural motion u Error concealment u MPEG artifact reduction u Film detection u Deinterlacing and edge dependent deinterlacing u Panorama scaling u Contrast enhancement u Blue stretch, green enhancement and skin tone control u Adaptive backlight dimming u Auto picture control u Video format scaling 2.4 Memory C O N n External DDR2 SDRAM memory configuration options Remark: The DDR interface is capable to operate DDR1 memories also, but this function will not be guaranteed. u 32-bit data width u 16-bit data width u Footprint up to 1 Gb u Data rate up to 533 MHz u Recommended device MT47H16M16BG-37E n EEPROM for external booting n FLASH memory through XIO interface 2.5 Miscellaneous n n n n Only one external quartz crystal required Several power modes 5 V tolerant interface pins for GPIO, PCI, XIO, I2C-bus, USB and host interface Qualified automotive grade 3 according to AEC-Q100 PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 2 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 3.1 Benefits from using PNX9530; PNX9531; PNX9535 A A A A R R D D D Software enabled video and multimedia entertainment platform 3. Applications FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D n Experience: u Enables the consumer to enjoy music and movies that they bring into their car on portable media and personal devices u Displays of up to two video sources in-car (dual video) u High-quality processing of video from a range of sources and in different formats u Turns even problematic video sources into high-quality video experience n Product design: u Software enabled processor flexible enough to address a wide variety of use case combinations, including dual video decoding u Design various differentiating in-car multimedia products with the same entertainment platform u Use available ecosystem of independent software partners to enable fast time-to-market of new features u Synergistic integration with other in-car digital systems u Significantly reduces system Bill Of Materials (BOM) R M O O N FI C C Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 3 of 72 A PNX9530_PNX9531_PNX9535_1 R Front Seat Entertainment (FSE) system Rear Seat Entertainment (RSE) system DVD or CD playback device, including SoftWare (SW) navigator USB, SD card or HDD audio/video playback device JPEG viewer for digital camera images Dual video decoding and rendering device In-car video source decoding Video broadcast source decoding WiFi audio/video streaming (DLNA compliant) Bluetooth audio streaming to headphones Extensive library of picture improvement algorithms D n n n n n n n n n n n FT PA D EN NY TI A L A 3.2 Typical applications with PNX9530; PNX9531; PNX9535 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R SOT795-1 plastic ball grid array package; 456 balls; body 27 × 27 × 1.75 mm SOT795-1 PNX9535E BGA456 plastic ball grid array package; 456 balls; body 27 × 27 × 1.75 mm SOT795-1 4.1 Ordering options Main type differences PNX9530 PNX9531 PNX9535 Unit Maximum internal TM clock frequency 351 450 243 MHz Width of DDR2 interface 32 32 16 bit up to 3 up to 3 1 - C O N FI C O M Video input channels PA D EN NY TI A L Parameter PNX9530_PNX9531_PNX9535_1 © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 4 of 72 A plastic ball grid array package; 456 balls; body 27 × 27 × 1.75 mm BGA456 R BGA456 PNX9531E D PNX9530E FT Version A Description Preliminary data sheet F D D Package Name Table 2. A FT FT A A R R D D D Type number FT FT FT FT Ordering information A A A A R R D D D 4. Ordering information FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 1. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 5. Block diagram FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D FT FT A A R R D D D DDR2 memory interface (266 MHz, 16/32 bit data width) R A FT D PNX9530 PNX9531 PNX9535 R PNX9530 A MEMORY INTERFACE (DDR2) VIDEO PROCESSING DVD DESCRAMBLER 24* VIDEO COMPOSITION PROCESSOR video input (TU656, transport stream RGB) 24 INPUT ROUTER FAST GENERAL PURPOSE INTERFACE AUDIO PROCESSING AUDIO INPUT 1 audio input 2* (8 channels I2S) AUDIO INPUT 2 O AUDIO OUTPUT 2 audio output 2* (8 channels I2S) COMMUNICATION UNIT N USB INTERFACE POR_IN_N RESET_IN_N USB 2.0 (OTG) PCI XIO O I2C C JTAG video output 2 (RGB, 656 HV, sync) audio output 1* (8 channels I2S) TriMedia PROCESSOR (TM3282) COPROCESSOR video output 1 (RGB, 656 HV, sync) AUDIO OUTPUT 1 FI GPIO, TIMERS, COUNTERS, SEMAPHONES C 8 GPIO 24* MEMORY BASED SCALER M audio input 1* (8 channels I2S) OUTPUT ROUTER PA D EN NY TI A L VIDEO INPUT PROCESSOR HOST INTERFACE TM TRACE PCI 2.2 (33 MHz, 32-bit) 16 host processor interface* EJTAG MAIN CONTROL (pc communication boot management reset and clock generator) XTAL_IN SYS_RESET_OUT_N CLKOUT XTAL_OUT 27 MHz crystal 001aaj939 Showing the maximum configuration of the multifunctional GPIO interface. Not all choices may be possible at the same time (see Section 8.1). Fig 1. Block diagram of PNX9530; PNX9531; PNX9535 PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 5 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 6.1 Pinning A FT FT A A R R D D D 6. Pinning information FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A H K M 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25 A C E G J L N PA D EN NY TI A L P A F R D D B FT ball A1 index area PNX9530 PNX9531 PNX9535 T V R U W Y AA AB AC AD AE AF 001aaj940 M Transparent top view Symbol Row A Pin Symbol Pin Symbol A2 MM_D0 A3 MM_D3 A4 MM_D5 MM_DS_P0 A6 MM_DS_N0 A7 MM_DM0 A8 MM_D12 A9 MM_BA1 A10 MM_A6 A11 MM_BA2 A12 MM_A4 A13 MM_A8 A14 MM_VREF A15 MM_CKE A16 MM_CLK_P A17 MM_CLK_N A18 MM_RAS_N A19 MM_D17 A20 MM_D16 A21 MM_DS_P3 A22 MM_DS_N3 A23 MM_D22 A24 MM_D29 A25 MM_DM3 A26 MM_D31 - - - - N A5 Symbol O VDI_D2 C A1 Pin FI Pin Pin allocation table[1][2][3] C Table 3. Pin configuration for BGA456 O Fig 2. Row B B1 VDI_D1 B2 MM_D4 B3 MM_D1 B4 MM_D6 B5 MM_D8 B6 MM_D10 B7 MM_D13 B8 MM_D15 B9 MM_D11 B10 MM_A2 B11 MM_A5 B12 MM_A1 B13 MM_A7 B14 MM_A9 B15 MM_CAS_N B16 MM_A13 B17 MM_PVT B18 MM_ODT B19 MM_D19 B20 MM_D20 B21 MM_DS_P2 B22 MM_DS_N2 B23 MM_D21 B24 MM_D25 B25 MM_D24 B26 MM_D28 - - - - PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 6 of 72 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R Pin Symbol Pin Symbol Pin Symbol C1 VDI_D3 C2 MM_D2 C3 MM_DM1 C4 MM_D9 C5 MM_D7 C6 MM_DS_P1 C7 MM_DS_N1 C8 MM_D14 C9 MM_BA0 C10 n.c. C11 MM_A0 C12 MM_A3 C13 MM_A10 C14 MM_A11 C15 MM_A12 C16 MM_CS_N C17 MM_WE_N C18 MM_D18 C19 VSSA(DLL2) C20 VDDA(DLL2) C21 MM_D23 C22 MM_DM2 C23 MM_D30 C24 MM_D26 C25 MM_D27 C26 n.c. - - - - D1 VDI_D4 D2 VDI_D0 D3 VSS D4 VSSA(DDR/PLL) D5 VDDD(C) D6 VDDD(IO)(DDR) D7 VDDD(IO)(DDR) D8 VDDA(DLL0) D9 VDDD(IO)(DDR) D10 VDDD(IO)(DDR) D11 VDDD(IO)(DDR) D12 VDDD(C) D13 VDDD(IO)(DDR) D14 VDDA(DLL1) D15 VDDD(IO)(DDR) D16 VDDD(IO)(DDR) D17 VDDD(IO)(DDR) D18 VDDD(IO)(DDR) D19 VDDD(C) D20 VDDD(IO)(DDR) D21 VDDD(IO)(DDR) D22 VDDD(IO)(DDR) D23 VDDD(C) D24 VSS D25 n.c. D26 n.c. - - - - E1 VDI_D6 E2 VDI_D5 E3 VDDD(IO) E4 VDDA(DDR/PLL) E5 VSS E6 VSS E8 VSSA(DLL0) VSS E10 M E7 E9 E11 VSS E12 VSS E13 VSS E14 VSSA(DLL1) E15 VSS E16 VSS E17 VSS E18 VSS E19 VSS E20 VSS E21 VSS E23 VDDD(IO)(DDR) E24 VSS E25 n.c. - - - - F3 CLKOUT F4 VSS D FT FT A A R R D Row C F FT FT Symbol A A A R R D D D Pin Pin allocation table[1][2][3] …continued FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 3. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A FT D R A VSS C O VSS FI Row E PA D EN NY TI A L Row D VSS E26 n.c. VDI_D8 Row F N E22 VDI_D7 F2 F5 VDDD(C) F22 VSS F23 VDDD(IO)(DDR) F24 VSS F25 n.c. F26 n.c. - - - - G2 GPIO38 G3 VDI_D9 G4 VDI_D10 C Row G O F1 G1 GPIO15 G5 VDDD(IO) G22 VSS G23 VSS G24 VDO_D0 G25 VDO_D3 G26 VDO_D1 - - - - H1 VDI_CLK1 H2 VDI_D11 H3 VDI_D13 H4 GPIO14 H5 VDDD(C) H22 VDDD(IO)(DDR) H23 VSS H24 VDO_D4 H25 VDO_D2 H26 VDO_D5 - - - - J1 VDI_D14 J2 VDI_D15 J3 VDI_D12 J4 GPIO34 J5 VSS J22 VSS J23 VSS J24 VDO_D6 J25 VDO_D7 J26 VDO_D8 - - - - Row H Row J PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 7 of 72 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R Pin Symbol Pin Symbol Pin Symbol K1 GPIO10 K2 GPIO11 K3 GPIO12 K4 VSS K5 VDDD(IO) K22 VDDD(IO)(DDR) K23 VSS K24 VDO_D9 K25 VDO_D12 K26 VDO_D11 - - - - L1 VDI_CLK0 L2 GPIO32 L3 GPIO33 L4 GPIO13 L5 VDDD(IO) L11 VSS L12 VSS L13 VSS L14 VSS L15 VSS L16 VSS L22 VDDD(C) L23 VSS L24 VDO_D10 L25 VDO_D13 L26 VDO_D14 M1 GPIO30 M2 GPIO29 M3 GPIO28 M4 GPIO31 M5 VDDD(C) M11 VSS M12 VSS M13 VSS M14 VSS M15 VSS M16 VSS M22 VSS M23 VSS M24 VDO_D15 M25 VDO_D16 M26 VDO_D17 N1 VDI_CLK2 N2 GPIO17 N3 GPIO39 N4 GPIO27 N5 VSS N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VDDD(IO) N23 VSS N24 M N25 VDO_D20 N26 VDO_D19 P1 VDDA(OSC) P2 VSSA(CGU/PLL) P3 VDDA(CGU/PLL) P4 VSSA(CAB/DDS) P5 VDDA(CAB)(3V3) P11 VSS P12 VSS P13 VSS P14 VSS P23 VSS D FT FT A A R R D Row K F FT FT Symbol A A A R R D D D Pin Pin allocation table[1][2][3] …continued FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 3. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A FT D R A Row L Row N P15 VSS P16 VSS P22 VSS P24 VDO_D21 P25 VDO_CLK P26 VDO_D23 N C FI VDO_D18 O Row P PA D EN NY TI A L Row M VSSA(CAB) R3 VDDA(CAB)(1V2) R4 VDDA(CAB/DDS) Row R XTAL_O R2 R5 VSS R11 VSS R12 VSS R13 VSS R14 VSS R15 VSS R16 VSS R22 VDDD(IO) R23 VDO_D22 R24 R25 VSS R26 VDO_D25 C O R1 VDO_D24 T1 XTAL_I T2 VSSA(OSC) T3 VSSA(CAB/DDS) T4 VDDD(IO) T5 VDDD(C) T11 VSS T12 VSS T13 VSS T14 VSS T15 VSS T16 VSS T22 VDDD(C) T23 VDO_D27 T24 VDO_D26 T25 VDO_D28 T26 VDO_D29 U1 GPIO50 U2 AO12_BCK U3 GPIO49 U4 AO12_OSCLK U5 VSS U22 VSS U23 VDO_D32 U24 VDO_D30 U25 VDDD(IO) U26 VDO_D31 - - - - Row T Row U PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 8 of 72 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R Pin Symbol Pin Symbol V1 AO12_WS V2 GPIO51 V3 GPIO52 V4 GPIO44 V5 VDDD(IO) V22 VDDD(C) V23 VDO_AUX V24 VDO_D33 V25 VDO_D34 V26 VDO_D35 - - - - W1 GPIO40 W2 GPIO41 W3 GPIO45 W4 VDDD(C) W5 VSS W22 VDDD(IO) W23 VDDD(IO) W24 VDO_HOR W25 VDO_VER W26 SYS_RST_OUT_N - - - - Y1 GPIO9 Y2 GPIO46 Y3 GPIO42 Y4 GPIO43 Y5 VDDD(IO)(PCI) Y22 VDDD(C) Y23 GPIO1 Y24 GPIO2 Y25 GPIO0 Y26 GPIO3 - - - - AA1 VSS AA2 VSS AA3 VSSA(TERM)(USB) AA4 USB_VBUS AA5 VSS AA22 VDDD(C) AA23 GPIO7 AA24 GPIO6 AA25 GPIO5 AA26 GPIO4 - - - - AB1 USB_DM AB2 VSSA(REF)(USB) AB3 VSSA(USB) AB4 USB_ID AB5 VDDD(IO)(PCI) AB6 VSS AB8 VDDD(C) VDDD(IO)(PCI) AB10 M AB7 AB9 AB11 VDDD(C) AB12 VSS AB13 VDDD(C) AB14 VSS AB15 VDDD(IO)(PCI) AB16 VSS AB17 VDDD(C) AB18 VSS AB19 VDDD(IO)(PCI) AB20 VSS AB21 VDDD(IO)(PCI) AB23 VDDD(C) AB24 VDDD(IO) AB25 VSS - - - - AC3 VDDA(DRV)(USB) AC4 VSS D FT FT A A R R D Row V F Symbol A Pin FT Symbol FT A A R R D D D Pin Pin allocation table[1][2][3] …continued FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 3. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A FT D R A Row W Row AB VSS C O VSS FI Row AA PA D EN NY TI A L Row Y VSS AB26 n.c. VDDA(USB) Row AC N AB22 USB_DP AC2 AC5 VDDD(IO)(PCI) AC6 PCI_AD31 AC7 VDDD(IO)(PCI) AC8 VSS AC9 PCI_IRDY_N AC10 VDDD(IO)(PCI) AC11 PCI_AD7 AC12 VDDD(IO)(PCI) AC13 PCI_PAR AC14 VSS AC15 PCI_AD8 AC16 VDDD(IO)(PCI) AC17 PCI_AD2 AC18 VDDD(IO)(PCI) AC19 GPIO21 AC20 GPIO58 AC21 GPIO56 AC22 GPIO16 AC23 VDDD(IO) AC24 VDDD(IO) AC25 VSS AC26 n.c. - - - - AD1 GPIO48 AD2 GPIO47 AD3 USB_RREF AD4 PCI_SYS_CLK AD5 GPIO18 AD6 PCI_AD27 AD7 PCI_CLK AD8 PCI_CBE3_N AD9 PCI_AD21 AD10 PCI_AD18 AD11 PCI_TRDY_N AD12 PCI_SERR_N AD13 PCI_AD14 AD14 PCI_AD10 AD15 PCI_AD15 AD16 PCI_AD11 AD17 PCI_CBE0_N AD18 GPIO37 AD19 GPIO35 AD20 GPIO26 AD21 GPIO22 AD22 GPIO54 AD23 VSS AD24 VSS AD25 TCK AD26 RESET_IN_N - - - - C O AC1 Row AD PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 9 of 72 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R Pin Symbol Pin Symbol Pin Symbol AE1 USB_RPU AE2 VDDD(C) AE3 PCI_AD30 AE4 GPIO60 AE5 PCI_AD28 AE6 PCI_IDSEL AE7 PCI_AD23 AE8 PCI_AD24 AE9 PCI_AD19 AE10 PCI_AD16 AE11 PCI_AD13 AE12 PCI_CBE2_N AE13 PCI_STOP_N AE14 PCI_AD0 AE15 PCI_AD1 AE16 PCI_AD4 AE17 GPIO59 AE18 PCI_AD6 AE19 GPIO25 AE20 GPIO23 AE21 GPIO19 AE22 GPIO8 AE23 GPIO53 AE24 TDO AE25 TDI AE26 POR_IN_N - - - - AF1 VSS AF2 VSS AF3 PCI_AD29 AF4 PCI_INTA_N AF5 PCI_AD26 AF6 VDDA(FB)(1V2) AF7 PCI_AD25 AF8 PCI_AD22 AF9 PCI_AD20 AF10 PCI_AD17 AF11 PCI_DEVSEL_N AF12 PCI_FRAME_N AF13 PCI_PERR_N AF14 PCI_CBE1_N AF15 GPIO36 AF16 PCI_AD12 AF17 PCI_AD9 AF18 PCI_AD5 AF19 PCI_AD3 AF20 GPIO24 AF21 GPIO20 AF22 GPIO57 AF23 GPIO55 AF24 TMS AF25 SDA AF26 SCL - - - - D FT FT A A R R D Row AE F FT FT Symbol A A A R R D D D Pin A A A A R R D D D Pin allocation table[1][2][3] …continued FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 3. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A FT D R A PA D EN NY TI A L Row AF See Section 8.1 for more functions available through the multiplexed GPIO interface and its default configuration. This interface extends functionality for digital video, extended I/O, host access, PCI-bus, USB-bus, digital audio, clocks and generic functions. Please keep in mind that some combinations may be mutually exclusive, depending on the specific application. [2] See Table 6 for type specific availability of DDR SDRAM pins MM_x. [3] n.c. indicate pins, which aren’t connected internally to the die. Those pins have no electrical function; see Table 17. Pin description overview Pin category[1] Power supply pins C Digital video input interface pins O DDR SDRAM memory interface pins N Table 4. C 6.2 Pin description FI O M [1] Table number Table 5 Table 6 Table 7 Digital video output interface pins Table 8 Digital audio interface pins Table 9 Multifunctional GPIO interface pins Table 10 PCI-bus interface pins Table 11 USB-bus interface pins Table 12 JTAG interface pins Table 13 I2C-bus Table 14 interface pins Main control pins Table 15 Crystal oscillator pins Table 16 Not connected pins Table 17 [1] See Section 8.1 for multiplexed GPIO functionality for video, XIO, host interface, PCI-bus, USB-bus, audio, clocks and generic functions. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 10 of 72 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R CAB/DDS analog supply voltage VDDA(CGU/PLL) P3 PS CGU/PLL analog supply voltage VDDA(DDR/PLL) E4 PS DDR/PLL analog supply voltage VDDA(DLL0) D8 PS DLL0 analog supply voltage VDDA(DLL1) D14 PS DLL1 analog supply voltage VDDA(DLL2) C20 PS DLL2 analog supply voltage VDDA(OSC) P1 PS oscillator analog supply voltage VDDA(DRV)(USB) AC3 PS USB driver analog supply voltage VDDA(FB)(1V2) AF6 PS FB analog supply voltage (1.2 V) VDDA(USB) AC2 PS USB analog supply voltage PS core digital supply voltage Digital supply voltage pins PA D EN NY TI A L PS A R4 R VDDA(CAB/DDS) D CAB analog supply voltage (3.3 V) D5, D12, D19, D23, F5, H5, L22, M5, T5, T22, V22, W4, Y22, AA22, AB8, AB11, AB13, AB17, AB23 and AE2 VDDD(IO) E3, G5, K5, L5, N22, R22, T4, U25, V5, PS W22, W23, AB24, AC23 and AC24 I/O digital supply voltage VDDD(IO)(DDR) D6, D7, D9 to D11, D13, D15 to D18, D20 to D22, E23, F23, H22 and K22 PS DDR input/output digital supply voltage VDDD(IO)(PCI) Y5, AB5, AB9, AB15, AB19, AB21, AC5, AC7, AC10, AC12, AC16 and AC18 PS PCI input/output digital supply voltage, 5 Volt tolerant FI C O M VDDD(C) Ground supply voltage pins D PS FT P5 A VDDA(CAB)(3V3) R CAB analog supply voltage (1.2 V) D PS FT R3 FT A A R VDDA(CAB)(1V2) G D3, D24, E5 to E7, E9 to E13, E15 to E22, E24, F4, F22, F24, G22, G23, H23, J5, J22, J23, K4, K23, L11 to L16, L23, M11 to M16, M22, M23, N5, N11 to N16, N23, P11 to P16, P22, P23, R5, R11 to R16, R25, T11 to T16, U5, U22, W5, AA1, AA2, AA5, AB6, AB7, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AB25, AC4, AC8, AC14, AC25, AD23, AD24, AF1 and AF2 ground supply voltage VSSA(CAB) R2 G CAB analog ground supply voltage VSSA(CAB/DDS) P4 and T3 G CAB/DDS analog ground supply voltage VSSA(CGU/PLL) P2 G CGU/PLL analog ground supply voltage VSSA(DDR/PLL) D4 G DDR/PLL analog ground supply voltage VSSA(DLL0) E8 G DLL0 analog ground supply voltage VSSA(DLL1) E14 G DLL1 analog ground supply voltage VSSA(DLL2) C19 G DLL2 analog ground supply voltage VSSA(OSC) T2 G oscillator analog ground supply voltage C O N VSS PNX9530_PNX9531_PNX9535_1 Preliminary data sheet F D D Analog supply voltage pins A FT FT A A R R D D D Type[1] Description Pin FT FT FT FT Symbol A A A A R R D D D Pin description (power supplies) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 5. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 11 of 72 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R USB reference analog ground supply voltage VSSA(TERM)(USB) AA3 G USB termination analog ground supply voltage AB3 G USB analog ground supply voltage D FT FT A A R R D D D G F AB2 A VSSA(REF)(USB) FT Type[1] Description FT A A R R D D D Pin R A FT D Table 18 defines the pin type. R [1] FT FT FT FT Symbol VSSA(USB) A A A A R R D D D Pin description (power supplies) …continued FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 5. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors A Table 6. Pin description (DDR SDRAM memory interface) Symbol Type[1] Pin Description PNX9535 MM_A13 B16 B16 A-O - address bit 13 MM_A12 C15 C15 A-O - address bit 12 MM_A11 C14 C14 A-O - address bit 11 MM_A10 C13 C13 MM_A9 B14 B14 MM_A8 A13 A13 MM_A7 B13 B13 MM_A6 A10 A10 MM_A5 B11 B11 MM_A4 A12 A12 MM_A3 C12 MM_A2 B10 MM_A1 B12 MM_A0 C11 MM_BA2 A11 MM_BA1 A9 MM_BA0 C9 MM_CAS_N B15 MM_CKE A15 MM_CLK_N A17 MM_CLK_P A16 MM_CS_N C16 MM_D31 MM_D30 C12 O B10 C B12 C11 A11 A-O - address bit 10 A-O - address bit 9 A-O - address bit 8 A-O - address bit 7 A-O - address bit 6 A-O - address bit 5 A-O - address bit 4 A-O - address bit 3 A-O - address bit 2 A-O - address bit 1 A-O - address bit 0 FI M PA D EN NY TI A L PNX9530; PNX9531 A-O - bank address bit 2 A-O - bank address bit 1 C9 A-O - bank address bit 0 B15 A-O PU column address selector (active LOW) A15 AF-O PD clock enable A17 C-O PU negative clock A16 C-O PU positive clock C16 A-O - chip select (active LOW) A26 - D-IO - data bit 31 C23 - D-IO - data bit 30 MM_D29 A24 - D-IO - data bit 29 MM_D28 B26 - D-IO - data bit 28 MM_D27 C25 - D-IO - data bit 27 MM_D26 C24 - D-IO - data bit 26 MM_D25 B24 - D-IO - data bit 25 MM_D24 B25 - D-IO - data bit 24 MM_D23 C21 - D-IO - data bit 23 MM_D22 A23 - D-IO - data bit 22 MM_D21 B23 - D-IO - data bit 21 C O N A9 PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 12 of 72 D D D D D R R R R R D R R D A FT R - D-IO - data bit 20 MM_D19 B19 - D-IO - data bit 19 MM_D18 C18 - D-IO - data bit 18 MM_D17 A19 - D-IO - data bit 17 MM_D16 A20 - D-IO - data bit 16 MM_D15 B8 B8 D-IO - data bit 15 MM_D14 C8 C8 D-IO - data bit 14 MM_D13 B7 B7 D-IO - data bit 13 MM_D12 A8 A8 D-IO - data bit 12 MM_D11 B9 B9 D-IO - data bit 11 MM_D10 B6 B6 D-IO - data bit 10 MM_D9 C4 C4 D-IO - data bit 9 MM_D8 B5 B5 D-IO - data bit 8 MM_D7 C5 C5 D-IO - data bit 7 MM_D6 B4 B4 D-IO - data bit 6 MM_D5 A4 A4 D-IO - data bit 5 MM_D4 B2 B2 D-IO - data bit 4 MM_D3 A3 - data bit 3 C2 M D-IO MM_D2 D-IO - data bit 2 MM_D1 B3 B3 D-IO - data bit 1 MM_D0 A2 D-IO - data bit 0 MM_DM3 A25 MM_DM2 C22 MM_DM1 C3 MM_DM0 A7 MM_DS_N3 A22 MM_DS_N2 B22 MM_DS_N1 C7 MM_DS_N0 A6 MM_DS_P3 MM_DS_P2 R B20 FT FT A A R MM_D20 F D D PNX9535 A FT FT A A R R D D D PNX9530; PNX9531 R R FT FT A A R R D D D Description FT FT FT FT Type[1] Pin A A A A R R D D D Pin description (DDR SDRAM memory interface) …continued Symbol FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 6. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A FT D R - PA D EN NY TI A L C A2 FI O C2 A A3 A-O - data write enable for byte 3, i.e. MM_D[31:24] A-O - data write enable for byte 2, i.e. MM_D[23:16] A-O - data write enable for byte 1, i.e. MM_D[15:8] A-O - data write enable for byte 0, i.e. MM_D[7:0] - R-IO - negative data strobe for byte 3, i.e. MM_D[31:24] - R-IO - negative data strobe for byte 2, i.e. MM_D[23:16] C7 R-IO - negative data strobe for byte 1, i.e. MM_D[15:8] A6 R-IO - negative data strobe for byte 0, i.e. MM_D[7:0] A21 - R-IO - positive data strobe for byte 3, i.e. MM_D[31:24] B21 - R-IO - positive data strobe for byte 2, i.e. MM_D[23:16] MM_DS_P1 C6 C6 R-IO - positive data strobe for byte 1, i.e. MM_D[15:8] MM_DS_P0 A5 A5 R-IO - positive data strobe for byte 0, i.e. MM_D[7:0] MM_ODT B18 B18 AF-O - on-die termination MM_PVT B17 B17 AR - process voltage temperature compensation MM_RAS_N A18 A18 A-O PU row address selector (active LOW) MM_VREF A14 A14 AI - reference voltage[2] MM_WE_N C17 C17 A-O - write enable (active LOW) - N C3 C O A7 [1] Table 18 defines the pin type. [2] Connect to VDDD(IO)(DDR) through a 130 Ω ± 1 % voltage divider. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 13 of 72 D D D D D R R R R R D R R FT H-IO, H-OZ PU clock 0 VDI_D15 J2 F-I PU data bit 15 VDI_D14 J1 F-I PU data bit 14 VDI_D13 H3 F-I PU data bit 13 VDI_D12 J3 F-I PU data bit 12 VDI_D11 H2 F-I PU data bit 11 VDI_D10 G4 F-I PU data bit 10 VDI_D9 G3 F-I PU data bit 9 VDI_D8 F2 F-I PU data bit 8 VDI_D7 F1 F-I PU data bit 7 VDI_D6 E1 F-I PU data bit 6 VDI_D5 E2 F-I PU data bit 5 VDI_D4 D1 F-I PU data bit 4 VDI_D3 C1 F-I PU data bit 3 VDI_D2 A1 F-I PU data bit 2 F-I PU data bit 1 F-I PU data bit 0 FT D R A FT D R M PA D EN NY TI A L A O D2 See Section 8.1 for more digital video input functions available through the multiplexed GPIO interface. [2] Table 18 defines the pin type. FI [1] C FT A A R B1 VDI_D0 R D VDI_D1 D L1 Pin description (digital video output interface)[1] Symbol V23 Type[2] Description F-OZ PD auxiliary video output VDO_CLK P25 H-IO PD video clock input and output VDO_D35 V26 F-OZ PD data bit 35 VDO_D34 V25 F-OZ PD data bit 34 VDO_D33 V24 F-OZ PD data bit 33 VDO_D32 U23 F-OZ PD data bit 32 VDO_D31 U26 F-OZ PD data bit 31 VDO_D30 U24 F-OZ PD data bit 30 VDO_D29 T26 F-OZ PD data bit 29 VDO_D28 T25 F-OZ PD data bit 28 VDO_D27 T23 F-OZ PD data bit 27 VDO_D26 T24 F-OZ PD data bit 26 VDO_D25 R26 F-OZ PD data bit 25 VDO_D24 R24 F-OZ PD data bit 24 VDO_D23 P26 F-OZ PD data bit 23 VDO_D22 R23 F-OZ PD data bit 22 C O VDO_AUX Pin N Table 8. F VDI_CLK0 A clock 1 D clock 2 PU FT PU H-IO FT H-IO H1 R A A N1 VDI_CLK1 D R R VDI_CLK2 Description R A D D Type[2] D R FT FT A A R R D D D Pin FT FT FT FT Symbol A A A A R R D D D Pin description (digital video input interface)[1] Table 7. FT FT FT FT FT Software enabled video and multimedia entertainment platform PNX9530_PNX9531_PNX9535_1 Preliminary data sheet A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 14 of 72 D D D D D R R R R R A A A A A D R R VDO_D16 M25 F-OZ PD data bit 16 VDO_D15 M24 F-OZ PD data bit 15 VDO_D14 L26 F-OZ PD data bit 14 VDO_D13 L25 F-OZ PD data bit 13 VDO_D12 K25 F-OZ PD data bit 12 VDO_D11 K26 F-OZ PD data bit 11 VDO_D10 L24 F-OZ PD data bit 10 VDO_D9 K24 F-OZ PD data bit 9 VDO_D8 J26 F-OZ PD data bit 8 VDO_D7 J25 F-OZ PD data bit 7 VDO_D6 J24 F-OZ PD data bit 6 VDO_D5 H26 F-OZ PD data bit 5 VDO_D4 H24 F-OZ PD data bit 4 F-OZ PD data bit 3 F-OZ PD data bit 2 F-OZ PD data bit 1 F-OZ PD data bit 0 FT D R A FT D D data bit 17 F PD A F-OZ R M26 D VDO_D17 FT data bit 18 R data bit 19 PD A PD F-OZ D F-OZ N24 R N26 VDO_D18 D VDO_D19 FT data bit 20 Description FT PD A F-OZ R N25 D VDO_D20 FT data bit 21 A PD R F-OZ D P24 FT VDO_D21 A A A Type[2] R R R Pin D D D Symbol FT FT FT FT Pin description (digital video output interface)[1] …continued A A A A R R D D D Software enabled video and multimedia entertainment platform Table 8. FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors R A FT D R PA D EN NY TI A L M G25 H25 O VDO_D2 VDO_D0 G24 FI G26 C VDO_D1 W24 F-OZ PD horizontal synchronization VDO_VER W25 F-IO PD vertical synchronization N VDO_HOR See Section 8.1 for more digital video output functions available through the multiplexed GPIO interface. [2] Table 18 defines the pin type. O [1] Pin description (digital audio interface)[1] C Table 9. Symbol Pin Type[2] AO12_BCK U2 L-IO PD audio bit clock AO12_OSCLK U4 L-OZ PU audio oscillator clock AO12_WS V1 F-IO PD audio word select Description [1] See Section 8.1 for more digital audio functions available through the multiplexed GPIO interface. [2] Table 18 defines the pin type. Table 10. Pin description (multifunctional GPIO interface)[1] Symbol Pin Type[2] GPIO60 AE4 P-IO - general purpose input or output 60 GPIO59 AE17 P-I - general purpose input or output 59 GPIO58 AC20 P-O - general purpose input or output 58 GPIO57 AF22 P-O - general purpose input or output 57 Description PNX9530_PNX9531_PNX9535_1 Preliminary data sheet A VDO_D3 © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 15 of 72 D D D D D R R R R R A A A A A D R R FT P-O - general purpose input or output 55 GPIO54 AD22 P-O - general purpose input or output 54 GPIO53 AE23 P-O - general purpose input or output 53 GPIO52 V3 S-O PD general purpose input or output 52 GPIO51 V2 S-O PD general purpose input or output 51 GPIO50 U1 S-O PD general purpose input or output 50 GPIO49 U3 S-O PD general purpose input or output 49 GPIO48 AD1 T-O PD general purpose input or output 48 GPIO47 AD2 T-I PD general purpose input or output 47 GPIO46 Y2 L-OZ PU general purpose input or output 46 GPIO45 W3 L-IO PD general purpose input or output 45 GPIO44 V4 F-IO PD general purpose input or output 44 GPIO43 Y4 S-IO PD general purpose input or output 43 GPIO42 Y3 S-IO PD general purpose input or output 42 GPIO41 W2 F-IO PD general purpose input or output 41 GPIO40 W1 L-IO PD general purpose input or output 40 GPIO39 N3 S-I, S-O PD general purpose input or output 39 S-I PD general purpose input or output 38 P-I - general purpose input or output 37 FT D R R D A FT D D AF23 F GPIO55 A general purpose input or output 56 FT - A P-I FT AC21 R A A GPIO56 Description D R R Type[2] R A D D Pin D R FT FT A A R R D D D Symbol FT FT FT FT Pin description (multifunctional GPIO interface)[1] …continued A A A A R R D D D Software enabled video and multimedia entertainment platform Table 10. FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors R A FT D R PA D EN NY TI A L M G2 AD18 AF15 P-IO - general purpose input or output 36 GPIO35 AD19 P-IO, P-I - general purpose input or output 35 C GPIO36 FI O GPIO37 J4 GPIO33 L3 GPIO32 L2 M4 O GPIO31 N GPIO34 L-IO, L-I PU general purpose input or output 34 F-IO PU general purpose input or output 33 S-IO PU general purpose input or output 32 S-IO PU general purpose input or output 31 M1 S-IO PU general purpose input or output 30 GPIO29 M2 S-IO PU general purpose input or output 29 GPIO28 M3 L-IO PU general purpose input or output 28 GPIO27 N4 F-IO PU general purpose input or output 27 GPIO26 AD20 T-IO PU general purpose input or output 26 GPIO25 AE19 T-IO PU general purpose input or output 25 GPIO24 AF20 T-IO PU general purpose input or output 24 GPIO23 AE20 T-IO PU general purpose input or output 23 GPIO22 AD21 T-IO PU general purpose input or output 22 GPIO21 AC19 T-IO PU general purpose input or output 21 GPIO20 AF21 T-IO PU general purpose input or output 20 GPIO19 AE21 T-IO PU general purpose input or output 19 GPIO18 AD5 P-IO - general purpose input or output 18 GPIO17 N2 S-IO PU general purpose input or output 17 C GPIO30 PNX9530_PNX9531_PNX9535_1 Preliminary data sheet A GPIO38 © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 16 of 72 D D D D D R R R R R D R R FT G1 S-I PU general purpose input or output 15 GPIO14 H4 S-I PD general purpose input or output 14 GPIO13 L4 S-O PD general purpose input or output 13 GPIO12 K3 IO, OZ PD general purpose input or output 12 GPIO11 K2 L-O PD general purpose input or output 11 GPIO10 K1 F-O PD general purpose input or output 10 GPIO9 Y1 L-OZ PU general purpose input or output 9 GPIO8 AE22 T-O, T-I PU general purpose input or output 8 GPIO7 AA23 T-IO, T-D PD general purpose input or output 7 GPIO6 AA24 F-IO, F-D PD general purpose input or output 6 GPIO5 AA25 F-IO, F-D PD general purpose input or output 5 GPIO4 AA26 F-IO, F-D PD general purpose input or output 4 GPIO3 Y26 F-IO, F-D PD general purpose input or output 3 GPIO2 Y24 F-IO, F-D PU general purpose input or output 2 GPIO1 Y23 F-IO, F-D PU general purpose input or output 1 GPIO0 Y25 F-IO, F-D PU general purpose input or output 0 FT D R R D A FT D D R A FT D R M PA D EN NY TI A L A See Section 8.1 for all functions and the default configuration of the multiplexed, multifunctional GPIO interface. GPIO[6:0] can be selecteds as clocks. Data may only appear at GPIO[60:0]. [2] Table 18 defines the pin type. O [1] FI Pin description (PCI-bus interface)[1] C Table 11. Type[2] Pin PCI_AD31 AC6 P-IO - bit 31 of the PCI address and data bus AE3 P-IO - bit 30 of the PCI address and data bus AF3 P-IO - bit 29 of the PCI address and data bus PCI_AD28 AE5 P-IO - bit 28 of the PCI address and data bus PCI_AD27 AD6 P-IO - bit 27 of the PCI address and data bus PCI_AD26 AF5 P-IO - bit 26 of the PCI address and data bus PCI_AD25 AF7 P-IO - bit 25 of the PCI address and data bus PCI_AD24 AE8 P-IO - bit 24 of the PCI address and data bus PCI_AD23 AE7 P-IO - bit 23 of the PCI address and data bus PCI_AD22 AF8 P-IO - bit 22 of the PCI address and data bus PCI_AD21 AD9 P-IO - bit 21 of the PCI address and data bus PCI_AD20 AF9 P-IO - bit 20 of the PCI address and data bus PCI_AD19 AE9 P-IO - bit 19 of the PCI address and data bus PCI_AD18 AD10 P-IO - bit 18 of the PCI address and data bus PCI_AD17 AF10 P-IO - bit 17 of the PCI address and data bus PCI_AD16 AE10 P-IO - bit 16 of the PCI address and data bus PCI_AD15 AD15 P-IO - bit 15 of the PCI address and data bus C O PCI_AD29 N Symbol PCI_AD30 F GPIO15 A general purpose input or output 16 FT PU A T-O, T-OD FT AC22 R A A GPIO16 Description D R R Type[2] R A D D Pin D R FT FT A A R R D D D Symbol FT FT FT FT Pin description (multifunctional GPIO interface)[1] …continued A A A A R R D D D Table 10. FT FT FT FT FT Software enabled video and multimedia entertainment platform Description PNX9530_PNX9531_PNX9535_1 Preliminary data sheet A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 17 of 72 D D D D D R R R R R A A A A A D R R D R R A FT FT FT A A R R D D D bit 14 of the PCI address and data bus PCI_AD13 AE11 P-IO - bit 13 of the PCI address and data bus PCI_AD12 AF16 P-IO - bit 12 of the PCI address and data bus PCI_AD11 AD16 P-IO - bit 11 of the PCI address and data bus PCI_AD10 AD14 P-IO - bit 10 of the PCI address and data bus PCI_AD9 AF17 P-IO - bit 9 of the PCI address and data bus PCI_AD8 AC15 P-IO - bit 8 of the PCI address and data bus PCI_AD7 AC11 P-IO - bit 7 of the PCI address and data bus PCI_AD6 AE18 P-IO - bit 6 of the PCI address and data bus PCI_AD5 AF18 P-IO - bit 5 of the PCI address and data bus PCI_AD4 AE16 P-IO - bit 4 of the PCI address and data bus PCI_AD3 AF19 P-IO - bit 3 of the PCI address and data bus PCI_AD2 AC17 P-IO - bit 2 of the PCI address and data bus PCI_AD1 AE15 P-IO - bit 1 of the PCI address and data bus FT D R R D A FT D D - F P-IO A AD13 FT PCI_AD14 R Type[2] A Pin FT A A R R D D D Symbol Description FT FT FT FT Pin description (PCI-bus interface)[1] …continued A A A A R R D D D Software enabled video and multimedia entertainment platform Table 11. FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors R A FT D R PA D EN NY TI A L P-IO - bus command and byte enable 3 of the PCI-bus interface (active LOW) bit 0 of the PCI address and data bus PCI_CBE2_N AE12 P-IO - bus command and byte enable 2 of the PCI-bus interface (active LOW) PCI_CBE1_N - bus command and byte enable 1 of the PCI-bus interface (active LOW) - bus command and byte enable 0 of the PCI-bus interface (active LOW) M P-IO AD8 P-IO PCI_CBE0_N AD17 P-IO C AE14 PCI_CBE3_N PCI_CLK AD7 P-I - clock signal of the PCI-bus interface PCI_DEVSEL _N AF11 P-I - device select signal of the PCI-bus interface (active LOW) N FI O AF14 P-I - frame signal of the PCI-bus interface (active LOW) PCI_IDSEL AE6 P-I - initialization device select signal of the PCI-bus interface PCI_INTA_N AF4 P-I, P-OD - interrupt signal of the PCI-bus interface (active LOW) PCI_IRDY_N AC9 P-IO - initiator ready signal of the PCI-bus interface (active LOW) PCI_PAR AC13 P-IO - parity signal of the PCI-bus interface PCI_PERR_N AF13 P-IO - parity error signal of the PCI-bus interface (active LOW) PCI_SERR_N AD12 P-OD - system error signal of the PCI-bus interface (active LOW) C O PCI_FRAME_N AF12 PCI_STOP_N AE13 P-IO - stop signal of the PCI-bus interface (active LOW) PCI_SYS_CLK AD4 P-IO PU system clock signal of the PCI-bus interface PCI_TRDY_N AD11 P-IO - target ready signal of the PCI-bus interface (active LOW) [1] See Section 8.1 for more PCI-bus functions available through the multiplexed GPIO interface. [2] Table 18 defines the pin type. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet A PCI_AD0 © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 18 of 72 D D D D D R R R R R D R R D A FT U-IO - minus data I/O of the USB-bus interface AC1 U-IO - positive data I/O of the USB-bus interface USB_ID AB4 U-I - type identification input of the USB-bus interface USB_RPU AE1 U-I - pull-up resistor of the USB-bus interface USB_RREF AD3 U-IO - resistor reference of the USB-bus interface[3] USB_VBUS AA4 U-IO - bus voltage of the USB-bus interface D FT R A D R Pin description (JTAG interface) TCK AD25 T-I PU test clock input TDI AE25 T-I PU test serial data input TDO AE24 L-OZ - test serial data output TMS AF24 T-I PU test mode select input PA D EN NY TI A L Description M Table 18 defines the pin type. Pin description (I2C-bus interface) C SDA Type[1] Description AF26 I2-I, I2-OD - serial clock input and output AF25 I2-I, I2-OD - serial data input and output FI SCL Pin O Symbol Table 15. N Table 18 defines the pin type. Pin description (main control pins) Pin Type[1] CLKOUT F3 H-IO PU clock output POR_IN_N AE26 T-I PU power-on reset input (active LOW) RESET_IN_N AD26 T-I PU master reset input (active LOW) SYS_RST_OUT_N W26 H-O PU system reset output (active LOW) C O Symbol Description Table 18 defines the pin type. Table 16. Pin description (crystal oscillator pins) Symbol Pin Type[1] XTAL_I T1 AI - crystal oscillator analog input XTAL_O R1 AO - crystal oscillator analog output Description Table 18 defines the pin type. PNX9530_PNX9531_PNX9535_1 © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 19 of 72 A Connect through a 12 kΩ ± 1 % resistance to the analog ground plane, which connects to pin VSSA(USB). Type[1] FT [3] [1] D D Table 18 defines the pin type. [1] FT A A R See Section 8.1 for more USB-bus functions available through the multiplexed GPIO interface. [2] Table 14. Preliminary data sheet R D [1] Pin F AB1 USB_DP Symbol A USB_DM FT Type[2] Description R FT A A R R D D D Pin [1] R R FT FT A A R R D D D Symbol Table 13. FT FT FT FT Pin description (USB-bus interface)[1] A A A A R R D D D Table 12. FT FT FT FT FT Software enabled video and multimedia entertainment platform [1] A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R A A A A A D R R FT D F D FT FT A A R R D D not connected D C10, C26, D25, D26, E25, E26, F25, F26, AB26 and AC26 - R A PNX9535 only FT - not connected R A19 to A26, B19 to B26, C18 and C21 to C25 D n.c. A FT FT A A R R R Description PNX9530, PNX9531 and PNX9535 n.c. R A D D Type D R FT FT A A R R D D D Symbol Pin FT FT FT FT Pin description (not connected pins) A A A A R R D D D Software enabled video and multimedia entertainment platform Table 17. FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors A Table 18. Pin type description Pin types are either generic or a combination of type and function. Examples are AO and P-OD. Type Description Generic analog input pin AO analog output pin AR analog reference pin G ground pin PS power supply pin Combined Type PA D EN NY TI A L AI Address pin AF Address pin with Forced low output during power-down C Clock pin D Data pin F Fast pin (1 ns slew rate) O H M A High-speed clock pin I2C-bus pin; 3.3 V signaling, 5 V tolerant L Low-speed clock pin P PCI Local Bus 2.2 specification compliant pin; 3.3 V signaling, 5 V tolerant R stRobe pin S Slow pin (3 ns slew rate) N 5 V Tolerant input 5 V tolerant USB-bus pin C U O T FI C I2 Function I Input O Output IO Input and Output I/O Input or Output I/OD Input or Output with open Drain I/O/D Input or Output or open Drain output with input OD Open Drain output OZ 3-state Output Resistor PD pull-down PU pull-up PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 20 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 7.1 Digital video A A A A R R D D D Software enabled video and multimedia entertainment platform 7. Functional description FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A 7.1.1 Video input FT D R The PNX9530; PNX9531; PNX9535 has a versatile ViDeo Input (VDI) module with a: A • Video Input Processor (VIP) for 8-bit, 10-bit, 16-bit or 20-bit YUV capture • Fast General Purpose Interface (FGPI) for 8-bit, 16-bit or 24-bit capture. See Section 8 for configuration examples of these multiplexed interfaces. 7.1.1.1 VIP PA D EN NY TI A L The VIP module accept a wides range of different video formats. The VIP interface is composed of 24 data pins VDI_D[23:0], five control pins VDI_V[2:0], VDI_HOR, VDI_VER and three video input clock pins VDI[2:0]_CLK. The VIP captures 8-bit or 10-bit streaming digital video from a parallel interface port. O M Two parallel Digital Video (DV) ports are connected to the input of the VIP. The digital video is provided in an ITU-R 656 compliant format, in a VESA compliant format or in a format with explicit synchronization signals. Typically, the digital video is YUV 4 : 2 : 2 encoded. Additionally, support is provided for RGB Bayer encoded video. Although only two DV ports are connected to the VIP, it is capable of capturing up to 8 digital video streams in parallel. This can be achieved by utilizing digital video decoders that time-multiplex 4 digital video streams into one stream, utilizing only one single DV port. Generate video stream test pattern N Capture streams on the DV ports Decode streams Windowing of video streams; this step generates both a primary and an auxillary video stream O • • • • FI C The VIP provided functionality is divided into the following steps, from capture to writing the video streams into main memory: C • Simple horizontal scaling (half resolution); co-sited or interspersed sampling of video data • Dithering, to support translation of 10-bit video into 8-bit video • Writing the video stream to main memory; support is provided for packed, semi-planar and planar memory layouts and 2-bit, 8-bit, 10-bit and 16-bit video data. Decoding streams includes demultiplexing of multiple time-multiplexed video streams on a single logical DV port, combining the streams of two logical DV ports into a single High-Definition (HD) video stream and video image extraction. This step also includes the extraction of ancillary data that may be encoded in video blanking regions. The windowing, scaling, dithering and writing to main memory steps are performed on each of the 8 video streams, each of which may be composed of a primary video stream, an auxillary video stream and an anicillary stream. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 21 of 72 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A D FT FT A A R R D In addition to the VIP module is the FGPI interface which shares the VDI pins. The FGPI module is a high-bandwidth input data channel. The FGPI packs four 8-bit samples, two 16-bit samples or one 32-bit sample of data into one 32-bit word, which is sent to main memory via DMA. 30-bit video input formats like RGB/YUV(4 : 4 : 4) can be cpatured using the FGPI. F FT FT A A R R D D D FGPI FT FT FT FT FT Software enabled video and multimedia entertainment platform 7.1.1.2 A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A FT D • Can be used as a versatile interface with streaming data sources • Can be used as a receiver port for inter-TriMedia unidirectional message passing • Permits optional synchronization with external control signals like h-sync and v-sync PA D EN NY TI A L to capture video data • POptionally inserts timestamp information into packet sent to memory • Optionally inserts information, like message or record length, into packet sent to memory • Permits continuous data transfer using DMA transfers to two main memory buffers. 32 Fig 3. 32 DTL INITIATOR 32 DTL TARGET DTL TARGET 64 MTL DTL ADAPTER INPUT ROUTER 32 001aaj941 O VDI pads FGPI MODULE DTL INITIATOR MTL-bus N C CLOCK BLOCK DTL TARGET FI MMIO DTL DTL INITIATOR ADAPTER O 32 M MMIO/DCS-bus FPGI top level block diagram C 7.1.2 Video output The PNX9530; PNX9531; PNX9535 has a versatile ViDeo Output (VDO) module with a: • DVD-Descrambler (DVD-D) module • Quality video Composition Processor (QVCP) module • Memory Based Scaler (MBS) module. See Section 8 for configuration examples of these multiplexed interfaces. The video output stream of the QVCP can be connected directly to the ViDeo Output (VDO) port VDO_D[35:0] of the PNX9530; PNX9531; PNX9535 in order to provide one video stream, but the PNX9530; PNX9531; PNX9535 can be used also to provide two different video streams to operate two LCD screens (i.e. for rear-seat entertainmant). PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 22 of 72 A The FGPI operates in two main modes, record capture or message passing: R The full bandwidth capabilities of FGPI are not used since there are only 24 data pins allocated to FGPI in the PNX9530; PNX9531; PNX9535 device. D D D D D R R R R R A A A A A FT FT FT FT FT PNX9530; PNX9531; PNX9535 D R R FT FT FT FT Software enabled video and multimedia entertainment platform A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Therefore the user can configure the QVCP to provide a multiplexed video output stream to the VDO buffer. The VDO buffer is used to demultiplex two combined video streams from the QVCP into two 18-bit RGB or two 24-bit RGB video output streams. D FT FT A A R R D D D The PNX9530; PNX9531; PNX9535 has a ViDeo Out Buffer (VDOB) for 2 × 24-bit RGB output mode. For restrictions see Table 19. R A D R DVD-D A The PNX9530; PNX9531; PNX9535 provides Digital Versatile Disc-Descrambler (DVD-D) module providing the major processes: • Authentiction process • Key conversion process • Main data descrambling process. QVCP PA D EN NY TI A L A DVD player system consists then of a DVD-ROM drive which accepts the DVD-ROM disc and reads the information from the disc to the drive controller. The drive controller connects the disc transport with an interconnecting bus (PCI-XIO) and hence to the host system (PNX9530; PNX9531; PNX9535). The host system interacts with the DVDD module to send authorization requests, receive authorization, replies, and transfer data between the DVD-ROM Drive and the DVDD module. 7.1.2.2 FI C O M The Quality video Composition Processor (QVCP) module is a high-resolution image composition and processing pipeline that facilitates both graphics and video processing. In combination with several other modules, it provides a new generation of graphics and video capability. QVCP provides its advanced functionality using a series of layers and mixers; a series of display-data layers (pixel streams) are created and logically mixed in sequence to render the composite output picture. C O N The QVCP module contains a total number of two layers and is mainly intended to be connected to a TV, a monitor or LCD panel. Due to the independence of the layers, a number of different scenarios is possible. However, in general, the QVCP has been designed to mix one video plane and one graphic plane. It can therefore be used to display a fully composited video image consisting of graphical information, lik ePIP or menu. QVCP supports a whole range of progressive and interlaced display standards: for televisions, from standard-definition resolutions such as PAL or NTSC to all eighteen ATSC display formats such as 1080i or 720p, and for computer and LCD displays at 60 Hz and up to 1080p resolutions. The wide variety of output modes guarantees the compatibility with most present display-processor chips. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet FT 7.1.2.1 © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 23 of 72 D D D D D R R R R R D R R FT R F FT FT A A A D FT FT A A R R D D D DMA3 R VBI data A FT DMA4 D R R OUTPUT PIPELINE R A D D MIXER D R FT FT A A R R D D D layer2 FT FT FT FT mixer_out LAYER STRUCTURE DMA2 A A A A R R D D D layer1 DMA1 FT FT FT FT FT Software enabled video and multimedia entertainment platform DMA interface to main memory A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D R A PROGRAMMING AND SCREEN TIMING CONTROL MMIO interface 001aaj942 Fig 4. QVCP top level block diagram • • • • PA D EN NY TI A L In order to achieve high-quality video and graphics as demanded by future consumer products, a number of complex tasks need to be performed by the QVCP. The main functions of the video and graphics output pipeline are: Fetching of up to two video streams from memory Color expansion in case of non-full color or indexed data formats Reverse-gamma correction Video quality enhancement such as luminance sharpening, chroma transient improvement, histogram modification, skin-tone correction, blue stretch, and green enhancement mode M • Horizontal up-scaling for video and graphics images in both linear and panorama O • Adapting screen timing generation to the connected display requirements (SDTV standards, HDTV standards, progressive and interlaced formats) Color space uniqueness of all video streams Merging of thevideo streams (blend, invert and exchange) N Positioning of the various video streams (including finer positioning) O Brightness and contrast control on a for each video output stream Gamma correction and noise shaping of the final composited image Output format generation. C 7.1.2.3 FI C • • • • • • MBS The captured data of the the VIP and the FPGI will get stored in main memory in the user defined address spaces. In order to enlarge or reduce the captured video images the PNX9530; PNX9531; PNX9535 has a Memory Based Scaler (MBS). Memory based scaling is done independent of any video clocks by reading the video data from memory and writing the scaled pictures back to the memory. A single scaler can therefore be used to scale more than one video stream sequentially. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 24 of 72 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D DEINTERFACE R DATA FLOW SWITCH PIXEL STORE UNIT 6 TAPS FIR PA D EN NY TI A L DEINTERFACE COEFFICIENTS A 12 LINE DELAY UNITS D 24 PIXEL DELAY UNITS 6 TAPS FIR FT alpha MBS block diagram D A 6 TAPS FIR R %2 D ×2 6 TAPS FIR FT PIXEL FETCH UNIT FT A A R R D 6 TAPS FIR 001aaj943 The memory-based scaler can perform the following operations: M • Vertical and horizontal scaling – Linear and non-linear aspect-ratio conversion (panorama scaling) O • De-interlacing – Simple median N FI C – Majority-selection (median filtering with previous field, spatial temporal average of 2 fields, same position from next or previous field depending on whether three or two field majority selection) Remark: Majority selection is done on luma only O – Field insertion and line doubling (i.e., repeating the same line twice) – Edge-Dependent De-interlacing (EDDI), a post-processing step done on luma only Anti-flicker filtering C • • • • Conversions between 4 : 2 : 0, 4 : 2 : 2 and 4 : 4 : 4 Indexed to true color conversion Color expansion and compression (different quantizations for color components, e.g. RGB565 to RGB32) • Deplanarization and planarization • Variable color space conversion with programmable matrix coefficients (mutually exclusive with horizontal scaling) • Color-key and alpha processing – Conversion between color-key and alpha – Alpha scaling • Measurements – Histogram measurement PNX9530_PNX9531_PNX9535_1 Preliminary data sheet A FT FT A A R R D D D PIO AND TASK FT FT FT FT COEFFICIENTS A A A A R R D D D COEFFICIENTS FT FT FT FT FT Software enabled video and multimedia entertainment platform Fig 5. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 25 of 72 D D D D D R R R R R A A A A A D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D – Blacklevel measurement FT FT FT FT – Blackbar detection A A A A R R D D D Software enabled video and multimedia entertainment platform – Noise estimation FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D – UV bandwidth measurement R A FT – Task list based programming. D 7.2 Digital audio PA D EN NY TI A L • Color key to alpha and alpha to color key conversion (color re-keying) • Non-linear phase interpolation (phase LUT). The PNX9530; PNX9531; PNX9535 has digital audio inputs and outputs: • Audio Input 2 (AI2) for 8 channels and master of the synchronization • Audio Output 2 (AO2) for 8 channels and master of the synchronization. For restrictions see Table 19 and Section 7.1.1. M 7.2.1 Audio input O The PNX9530; PNX9531; PNX9535 device has an Audio Input (AI) module to receive digital audio input streams. FI C The AI module can activate up to four audio input ports. Each audio input port processes single-channel or dual-channel sources. Hence the AI module can capture up to 8 channels of audio input (4 stereo channels). C O N The AI module includes four major subsystems: a programmable sample clock generator, a serial-to-parallel converter, a Device Transaction Level (DTL) initiator interface that initiates transfer of parallel data to a DTL-to-memory bus adapter and a MMIO type low latency DTL target interface for MMIO configuration registers. The sampling clock can be used as either master or slave to the external audio. The sampling clock synchronizes the serial-to-parallel converter with the source data stream. The samples enter the serial-to-parallel converter, which reformats the data for the initiator. The initiator streams the parallel data in to the DTL-to-memory bus adapter. The AI module provides a DMA-driven serial interface to an off-chip stereo Analog-to-Digital Converter (ADC), I2S subsystem or other serial data source. AI provides all signals needed to connect to high-quality, low-cost oversampling ADCs. The AI module and external ADC (or I2S subsystem) together are capable of generating a programmable sample clock by dividing a precise oversampling clock, which will be provided by the internal clock factory of the PNX9530; PNX9531; PNX9535. The AI module has the following features: • Four channels of audio input per port • 16-bit or 32-bit samples per channel PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 26 of 72 A Special modes and features: R Most of the above functions can be performed during a single pass, though the filter quality (length) may vary depending on the performed operations. D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R A F FT Remark: This is a practical range; the actual sample rate is application dependent FT A A R R D D D • Programmable 1 Hz to 192 kHz sampling rate FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D FT D D R A network FT A A R R D • Internal or external sampling clock source • AI autonomously writes sampled audio data to memory using the internal DMA FT Remark: AC-97 codecs are not supported. PA D EN NY TI A L The PNX9530; PNX9531; PNX9535 includes 2 identical AI modules. The pins available may however differ depending on the PNX9530; PNX9531; PNX9535 configuration being used. CLOCK DIVIDER/GENERATOR AI_OSCLK SCK DIVIDER AI_SCK divider value AI_WS O serial clock different framing/capture options FI C SERIAL TO PARALLEL CONVERTER AI_SD[0] DTL INTERFACE divider value M WS DIVIDER MMIO REGISTERS LOGIC DTL DMA INTERFACE LOGIC SHIFT REGISTER SHIFT REGISTER AI_SD[2] SHIFT REGISTER AI_SD[3] SHIFT REGISTER parallel data O N AI_SD[1] 001aaj944 C Fig 6. DTL INTERFACE Audio in block diagram 7.2.2 Audio output The PNX9530; PNX9531; PNX9535 device has an Audio Output (AO) module providing a DMA-driven serial interface designed to support stereo audio Digital-to-Analog Converters (DAC). The AO module can support up to eight PCM audio channels by driving up to four external stereo DACs. The AO module provides a direct connection interface to high-quality, low-cost oversampling DACs. A precise programmable oversampling clock is featured. The AO module has four major subsystems: a programmable sample clock generator, a DMA engine, a parallel to serial converter and memory mapped registers for configuration and control. The AO connectors provide the digital audio stream, clock and control signals to external D/A converters. A block diagram of AO is illustrated in Figure 7. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 27 of 72 A • Little-endian or big-endian memory formats. R the frame sync signal (pin AI1_WS or AI2_WS) and stored in memory D • 16-bit and 32-bit mono and stereo PC standard memory data formats • Raw mode where the bits from all the active inputs are sampled by bit clock along with D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A R A Remark: AC-97 codecs are not supported. PA D EN NY TI A L The DMA engine reads 16-bit or 32-bit samples from memory using dual DMA buffers in memory. Software initially assigns two full sample buffers in memory containing an integral number of samples for all active channels. The DMA engine retrieves samples from the first buffer in memory until exhausted and continues from the second buffer in memory as a request for a new first sample buffer in memory is issued to the system controller. This is a continuous process. M The samples are given to the data serializer (parallel-to-serial converter), which sends them out in a MSB first or LSB first serial frame format that can also contain one or two codec control words of up to 16 bits. The output frame structure is programmable. N FI C O PNX9530; PNX9531; PNX9535 includes 2 identical AO modules. The pins available may however differ depending on the PNX9530; PNX9531; PNX9535 configuration being used. O C WS serial clock EXTERNAL INTERFACE MMIO REGISTERS LOGIC framing/sample options DCSBUS PARALLEL TO SERIAL CONVERTER SD[0] SHIFT REGISTER SD[1] SHIFT REGISTER SD[2] SHIFT REGISTER SD[3] SHIFT REGISTER DTL INTERFACE divider value WS DIVIDER DTL DMA INTERFACE LOGIC parallel data DTL INTERFACE 001aaj945 Fig 7. AO block diagram PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 D Control capability for highly integrated PC codecs. SCK FT 16-bit mono and stereo PC standard memory data formats divider value F D D Autonomously retrieves processed audio data from dual DMA buffers in memory SCK DIVIDER A FT FT A A R R D D D Internal or external bit clock source OSCLK FT FT FT FT Remark: This is a practical range; the actual sample rate is application dependent CLOCK DIVIDER/GENERATOR A A A A R R D D D The AO module, along with the external DACs, has the following capabilities: • Up to 8 channels of audio output • 16-bit or 32-bit samples per channel • Programmable 1 Hz to 192 kHz sampling rate FT FT FT FT FT Software enabled video and multimedia entertainment platform • • • • A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors 28 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 7.3.1 DDR SDRAM memory interface A A A A R R D D D Software enabled video and multimedia entertainment platform 7.3 Peripheral interfaces FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D The PNX9530; PNX9531; PNX9535 has a DDR controller which is used to interface to off-chip DDR2 memory devices. R A FT 16-bit or 32-bit wide data bus on DDR SDRAM memory side Three MTL ports (one for the DMA memory traffic, two for the CPU) Supports × 8 and × 16, 4 and 8 banks memory devices PA D EN NY TI A L Supports up to 2 Gb DDR SDRAM memory devices Supports 1 rank (physical banks) of memory devices Maximum of 8 open pages for a maximum address range of 256 MB Halt modes and clock gating for power consumption reduction Programmable DDR SDRAM timing parameters that support different DDR SDRAM memory devices up to 266 MHz, i.e. 533 MHz data rate M • Programmable bank mapping scheme to potentially improve bandwidth utilization • Programmable arbitration with latency or deadline guarantees with built-in performance monitors O • JEDEC compliant limited to burst length of 8. C O N FI C The DDR controller module includes an arbiter which arbitrates between the DDR burst commands coming from the three different MTL ports. After arbitration, the DDR burst command selected by the arbiter is stored in a FIFO with 5 entries. The DDR module has a refresh counter to keep track of the refresh timing. The DDR module keeps track of the open pages in the DDR memories. The DDR command generator decides upon which command (refresh, precharge, activate, read or write) to generate based on the information in the FIFO with 5 entries, the state of the refresh counter, and the state of the DDR memories as indicated by the open page table. 7.3.2 Multifunctional GPIO interface The PNX9530; PNX9531; PNX9535 has a 61-bit wide GPIO interface, which multiplexes various functions. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 29 of 72 A • • • • • • • • R The primary features of the DDR SDRAM controller include: D Remark: The DDR interface is capable to operate DDR1 memories also, but this function will not be guaranteed D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The PNX9530; PNX9531; PNX9535 has 61 pins that are capable of operating as software controlled General Purpose Input Output (GPIO) pins. Eight of them are dedicated GPIO pins. The other 53 pins are assigned to the other PNX9530; PNX9531; PNX9535 modules, like the AO module, but they can be re-used as GPIO pins, see Section 8.1. So these are designated as optional GPIO pins that can either operate in regular mode or in GPIO mode. All 61 pins have common features: F FT FT A A R R D D D GPIO FT FT FT FT FT Software enabled video and multimedia entertainment platform 7.3.2.1 A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A FT D R A • Software I/O, which sets a pin or pin group, enables a pin or a pin group and inspects pin values • Precise timestamping of internal and external events (up to 12 signals simultaneously) • Signal event sequence monitoring or signal generation (up to 4 signals simultaneously) PA D EN NY TI A L • Timer source selection for TM3282. The 61 pins have the same GPIO capabilities. However some of the dedicated GPIO pins have additional features like: • Clocks: these pins are possible clock source for pattern generation or sampling mode or they are simply used to provide a clock to peripherals on the PNX9530; PNX9531; PNX9535 system board mode M • Wake-up event: used to wake-up PNX9530; PNX9531; PNX9535 from deep-sleep O • Boot option: determines the boot settings of PNX9530; PNX9531; PNX9535 • Watchdog: this is a subset of the software I/O mode since the TM3282 CPU would FI C toggle this pin at regular intervals in order to prevent an external watchdog to reset the entire system; alternately the internal watchdog timer of PNX9530; PNX9531; PNX9535 system can be used. O N After a PNX9530; PNX9531; PNX9535 system reset has occured all the GPIO pins are set to GPIO mode and in input mode (3-state). C A simplified block diagram of the GPIO module can be found in Figure 8. It presents the major interfaces of the GPIO module: • The GPIO pins • The MTL interface used to fetch data when operating in pattern generation mode or used to store data when the GPIO module is used in sampling mode.; in both cases up to 4 FIFO memory buffers are available for one of the modes • The DCS-bus interface used to convey the MMIO register read and writes issued by the TM3282 CPU or any other master connected to PNX9530; PNX9531; PNX9535 through the PCI-bus interface • The 5 interrupt lines which are routed directly to the TM3282 CPU; 4 lines are associated with the signal monitoring while the last interrupt line is linked to the event monitoring. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 30 of 72 D D D D D R R R R R D R R R OP CTRL 0 SIGNAL MONITOR CONTROL 3 IP MUX 3 PATTERN GENERATION CONTROL 3 OP CTRL 3 A PATTERN GENERATION CONTROL 0 FT FT D D R FT D R A PA D EN NY TI A L A TSU CONTROL pins IP MUX 4 001aaj946 M PCI-bus and XIO interface O The arbiter can control up to three external PCI masters, when the host interface is not used (see Table 19). FI C The XIO interface accepts up to five chip select signals and up to 16 data pins, when the host interface is not used (see Table 19). N For a full featured list of all PCI 2.2 configurations please contact NXP; see Section 22. PCI-bus interface O 7.3.2.3 C PNX9530; PNX9531; PNX9535 includes a PCI-bus interface for easy integration into personal computer applications (where the PCI-bus is the standard for high-speed peripherals). In embedded applications the PCI-bus can interface to peripheral devices that implement functions not provided by the on-chip modules or to connected several CPUs together. The PCI-XIO module supports 33 MHz and 66 MHz according to PCI specification version 2.2. It can operate as a configuration manager or it can also act as a target to external configuration cycles when an external processor and north bridge are used in the system. Features: • Three base addresses, i.e. apertures, are supported: DRAM, MMIO and XIO • Option to enable internal PCI system arbiter which can support up to three external PCI masters • As a PCI master, it can generate all non-reserved types of single transaction PCI cycles: I/O, memory, interrupt acknowledge and configuration cycle PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 F R IP MUX 0 A D SIGNAL MONITOR CONTROL 0 A 7.3.2.2 TIMESTAMP COUNTER R GPIO module block diagram D PI REGISTERS PIO INTERFACE FT FT DTL2PIO WRAPPER D A A DCS bus FIFO CONTROL 3 R FT R R 32 × 32 RF PERIPHERAL INTERRUPT CONTROLLER 4 Fig 8. A D D DMA REQUEST CONTROL PERIPHERAL INTERRUPT CONTROLLER 0 5 FIFO CONTROL 0 D R FT FT A A R R D D D 32 × 32 RF FT FT FT FT GPIO CORE IP_1814 ADAPTER A A A A R R D D D MTL bus FT FT FT FT FT Software enabled video and multimedia entertainment platform to TM3282 A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors 31 of 72 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A FT D generated externally and input to this module R A • In PCI terminology it is a single function device. The following general PCI-bus features are not implemented in the PCI-XIO module: • As a PCI target, the device only responds to memory and configuration cycles • Subtractive decoding is not supported • There is no hard-coded legacy decoding of address space (such as VGA I/O and memory) PA D EN NY TI A L • Burst to configuration space is not supported. M The main function of the PCI-bus interface is to connect the PNX9530; PNX9531; PNX9535 on-chip MTL bus (and therefore its main memory) and its internal registers to external devices on the PCI-bus. A bus cycle on PCI that targets an address mapped into PNX9530; PNX9531; PNX9535 memory space will cause the PCI-bus interface to create a MTL bus cycle targeted at DRAM. From PNX9530; PNX9531; PNX9535, only the TM3282 CPU can cause the PCI-bus interface to create PCI-bus cycles; the other on-chip modules cannot access external hardware through the PCI-bus interface. From PCI, DRAM and most of the registers in MMIO space can be accessed by external PCI initiators. O F D D • The PCI clock (at pin PCI_SYS_CLK) and PCI_RST_N (at pin RESET_IN_N) are The PCI-bus interface implements DMA (also called block or burst transfers) and non-DMA transfers. DMA transfers are interruptible on 64-byte boundaries. FI C A FT FT A A R R D D D device; the DMA can also be used to transfer data to and from XIO devices N The following classes of operations invoked by PNX9530; PNX9531; PNX9535 cause the PCI-bus interface to act as a PCI initiator: • Transparent, single-word (or smaller) transactions caused by TM3282 loads and O stores to one of the two available the PCI-bus address aperture, PCI1 and PCI2 ??? C • Explicitly programmed single-word I/O or configuration read or write transactions • Explicitly programmed multi-word DMA transactions. The PNX9530; PNX9531; PNX9535 PCI-bus interface responds as a target to external initiators for a limited set of PCI transaction types: • Configuration R/W • Memory R/W, read line, and read multiple to the PNX9530; PNX9531; PNX9535 DRAM or MMIO apertures. PNX9530; PNX9531; PNX9535 ignores PCI transactions other than the above. The PCI-XIO module also includes an XIO interface. Both interfaces don’t execute simultaneously, see Table 19. The XIO interface uses PCI cycle to run XIO transfers before giving control back to PCI-bus. The XIO interface supports IDE, NAND and NOR © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 FT FT FT FT • A DMA engine provides high-speed transfer to and from SDRAM and an external PCI PNX9530_PNX9531_PNX9535_1 A A A A R R D D D • Linear burst mode is supported on memory transactions; other burst mode transfers are terminated after a single data transfer FT FT FT FT FT Software enabled video and multimedia entertainment platform Preliminary data sheet A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors 32 of 72 D D D D D R R R R R A A A A A FT FT FT FT FT PNX9530; PNX9531; PNX9535 D R R FT FT FT FT Software enabled video and multimedia entertainment platform A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D type Flash and Motorola devices, in an 8-bit or 16-bit wide datapath. Maximum NAND FLASH supported per profile is 128 MB. Maximum NOR FLASH supported per profile is 128 MB. PCI-XIO supports up to 5 profiles. D FT FT A A R R D D USB-bus interface D 7.3.2.4 R A PA D EN NY TI A L M O Host interface FI C Parts of the multiplexed GPIO interface can operate as the host interface. For effect on other PNX9530; PNX9531; PNX9535 features see Table 19. C O N The PNX9530; PNX9531; PNX9535 provides a high-speed interface for I2C-bus communication with a host processor to exchange data as well as command messages. Two separated channels are implemented to ease the software development by providing separated data buffers in the PNX9530; PNX9531; PNX9535 for data and command messages. The command message structure can be defined freely by the user to adapt the PNX9530; PNX9531; PNX9535 to the target system. The data/command buffer sizes can be defined independent of each other from 16 byte to several kB or MB depending on the available main memmory space. The host interface can be used in transaction modes with a data width of 16-bit or 8-bit by providing data transfer rates of up to 400 Mb/s (16-bit mode) or 200 Mb/s (8-bit mode). 7.3.3 I2C-bus interface The PNX9530; PNX9531; PNX9535 has a 5 V tolerant standard I2C-bus interface, which can work as slave or master on the bus configurable during run time. The PNX9530; PNX9531; PNX9535 can load the boot code via an external connected I2C EEPROM after reset and switch into slave mode if an external master requests the I2C-bus. The interface can run on 100 kHz as well as on 400 kHz. 7.3.4 JTAG interface The PNX9530; PNX9531; PNX9535 has a dedicated JTAG interface for software development. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 33 of 72 A 7.3.2.5 R The USB-bus interface supports the USB 2.0 HS OTG standard. It has two optional LED pins at pins USB_LED[1:0]. For availability and restrictions see Table 19. D Additionaly the PNX9530; PNX9531; PNX9535 provides the OTG functionality of USB 2.0. The On-The-Go (OTG) supplement to the USB Specification extends USB to peer-to-peer application. Using USB OTG technology the PNX9530; PNX9531; PNX9535 can be directly connected to a storeage device or host to exchange data. The OTG state machines determine the role of the device based on connector signals, and then initializes the device in the appropriate mode of operation (host or peripheral) based on how it is connected. After connecting the devices can negotiate using the OTG protocols to assume the role of host or peripheral based on the task to be accomplished. FT An USB-bus interface on dedicated I/O pins have been implemented in the PNX9530; PNX9531; PNX9535 fulfilling the USB 2.0 HS OTG specification. USB 2.0 offers the user a larger bandwidth increasing data throughput by a factor of 40 compared to USB 1.1. All the peripherals used with the previous versions of USB work perfectly with USB 2.0 while also offering a larger choice of higher performance peripherals, such as video cameras, fast storages devices, GPS receiver, etc. In addition to the 1.5 Mb/s and 12 Mb/s data rates of USB 1.1, the evolution from USB 1.1 to USB 2.0 adds an additional data rate of 480 MB/s. D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 8.1 Multiplexed GPIO functionality A FT FT A A R R D D D 8. Application design-in information FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R The PNX9530; PNX9531; PNX9535 has a versatile, software programmable GPIO interface for enhanced video and multimedia functionality. Applications can use the GPIO interface for general purpose input and output. Table 19 lists extended functionality from the GPIO interface for: A Extended I/O functions Host interface functions PA D EN NY TI A L PCI-bus functions extension USB-bus functions extension Clock signals Generic signals. M Remark: The PNX9530; PNX9531; PNX9535 uses the GPIOs in boot mode. After finishing the boot process the GPIOs are available for the multiplexed functions (see Table 19). FI C O Remark: Please note that these multiplexed functions are mutually exclusive, i.e. they may not be available at the same time depending on the software enabled configuration of the PNX9530; PNX9531; PNX9535. C O N Remark: For default configuration of GPIO pins and functionality see Table 20. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 34 of 72 A Digital audio functions R Digital video output functions D Digital video input functions FT • • • • • • • • • xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors Interfaces with mutually exclusive functionality Video input Video output Extended I/O Host PCI USB Audio[2] Clocks GPIO0 - - - - - - - CLOCK0 BOOT_MODE0 GPIO1 - - - - - - - CLOCK1 BOOT_MODE1 GPIO2 - - - - - - - CLOCK2 BOOT_MODE2 GPIO3 - - - - - - - CLOCK3 BOOT_MODE3 GPIO4 - - - - - - - CLOCK4 BOOT_MODE4 GPIO5 - - - - - - - CLOCK5 - GPIO6 - - - - - - CLOCK6 - GPIO7 - - - - - - - WAKEUP GPIO8 - - XIO_SEL4 HOSTIF_CLE - - - - - GPIO9 - - C - GPIO11 - VDO_D46 - - GPIO12 - VDO_D45 - - GPIO13 - VDO_D44 - - - - AI2_OSCLK - - - - AO2_SD3/AO2_WS - - - - AO2_SD2/AO2_BCK - - - - AO2_SD1/AO2_OSCLK - - - - AO2_SD0 - - - - - - - - - - - - - - - - - - - GPIO16 - - XIO_SEL3 HOSTIF_INT_N GPIO17 VDI_V0 - - HOSTIF_RESET_N - USB_LED0 - - - GPIO18 - - - - PCI_REQ_N - - - - GPIO19 - - XIO_D15 HOSTIF_D15 - - - - - GPIO20 - - XIO_D14 HOSTIF_D14 - - - - - GPIO21 - - XIO_D13 HOSTIF_D13 - - - - - GPIO22 - - XIO_D12 HOSTIF_D12 - - - - - GPIO23 - - XIO_D11 HOSTIF_D11 - - - - - GPIO24 - - XIO_D10 HOSTIF_D10 - - - - - GPIO25 - - XIO_D9 HOSTIF_D9 - - - - - GPIO26 - - XIO_D8 HOSTIF_D8 - - - - - D - FT GPIO15 VDI_VER FT A - R - D A R FT D R FT D A R FT FT D F A R D A R D FT A R FT D A 35 of 72 © NXP B.V. 2009. All rights reserved. GPIO14 VDI_HOR - PNX9530; PNX9531; PNX9535 - Generic D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F F T T T T Software enabled video and multimedia entertainment platform D D D D R R R R A A A - VDO_D47 - N - GPIO10 - Y L N IA PA NT M O DE FI - O Rev. 01.11C — 1 October 2009 GPIO pin C PNX9530_PNX9531_PNX9535_1 Preliminary data sheet Multiplexed GPIO functionality[1] Table 19. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors GPIO pin Interfaces with mutually exclusive functionality Video input Video output Extended I/O Host PCI USB Audio[2] Clocks Generic - - - GPIO29 VDI_D21 VDO_D41 - HOSTIF_D5 - - AI2_SD3 - - GPIO30 VDI_D20 VDO_D40 - HOSTIF_D4 - - AI2_SD2 - - GPIO31 VDI_D19 VDO_D39 - HOSTIF_D3 - - AI2_SD1 - - GPIO32 VDI_D18 VDO_D38 - HOSTIF_D2 - - AI2_SD0 - - GPIO33 VDI_D17 VDO_D37 - - - AI2_WS - - GPIO34 VDI_D16 VDO_D36 - - - AI2_BCK - - GPIO35 - - - HOSTIF_RD_OE_N PCI_GNT_B_N - - - - GPIO36 - - - HOSTIF_WR_N PCI_GNT_A_N - - - - GPIO37 - - - HOSTIF_CS_N PCI_REQ_A_N - - - - GPIO38 VDI_V2 - - - - - - - - GPIO39 VDI_V1 - - - - USB_LED1 - - - GPIO40 - - - - - - AI1_SD3/AI2_BCK - - GPIO41 - - - - - - AI1_SD2/AI2_WS - - GPIO42 - - - - - - AI1_SD1/AI2_SD0 - - GPIO43 - - - - - - AI1_SD0 - - GPIO44 - - - - - - AI1_WS - - GPIO45 - - - - - - AI1_BCK - - GPIO46 - - - - - - AI12_OSCLK - - GPIO47 - - - - - USB_VBUS_FLT - - - GPIO48 - - - - - USB_VBUS_PWE - - - GPIO49 - - - - - - AO1_SD3 - - GPIO50 - - - - - - AO1_SD2 - - GPIO51 - - - - - - AO1_SD1 - - GPIO52 - - - - - - AO1_SD0 - - HOSTIF_D1 HOSTIF_D0 Y L N IA PA NT M O DE FI N FT A D A R FT D R FT D A R FT FT D F A R D A R D FT A R FT D A PNX9530; PNX9531; PNX9535 - AO2_BCK D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F F T T T T Software enabled video and multimedia entertainment platform D D D D R R R R A A A AO2_WS - D - - FT - HOSTIF_D6 R HOSTIF_D7 VDO_D42 - O 36 of 72 © NXP B.V. 2009. All rights reserved. VDO_D43 - GPIO28 VDI_D22 C Rev. 01.11C — 1 October 2009 GPIO27 VDI_D23 C PNX9530_PNX9531_PNX9535_1 Preliminary data sheet Multiplexed GPIO functionality[1] …continued Table 19. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx GPIO pin NXP Semiconductors PNX9530_PNX9531_PNX9535_1 Preliminary data sheet Multiplexed GPIO functionality[1] …continued Table 19. Interfaces with mutually exclusive functionality PCI USB Audio[2] Clocks Generic XIO_SEL2 - - - - - - - XIO_SEL1 - - - - - - GPIO55 - - XIO_SEL0 - - - - - - GPIO56 - - XIO_ACK - - - - - - GPIO57 - - XIO_AD26 - - - - - - GPIO58 - - XIO_AD25 - - - - - - GPIO59 - - - PCI_REQ_B_N - - - - GPIO60 - - - PCI_GNT_N - - - Video input Video output Extended I/O GPIO53 - - GPIO54 - Host - - See running text of this section for the boot process. For default configuration of GPIO pins and functionality see Table 20. Additional flexible configuration is possible through dedicated register settings for the audio interface. FT D FT A R D A R FT D R FT D A R FT FT D F A R D A R D FT A R FT D A 37 of 72 © NXP B.V. 2009. All rights reserved. PNX9530; PNX9531; PNX9535 N [1] [2] D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F F T T T T Software enabled video and multimedia entertainment platform D D D D R R R R A A A O Rev. 01.11C — 1 October 2009 Y L N IA PA NT M O DE FI C C - D D D D D R R R R R D R R FT D R R Pin Function Pin Function Pin Function GPIO0 GPIO16 XIO_SEL3 GPIO32 VDI_D18 GPIO48 USB_VBUS_PWE GPIO1 GPIO1 GPIO17 VDI_V0 GPIO33 VDI_D17 GPIO49 AO1_SD3 GPIO2 GPIO2 GPIO18 PCI_REQ_N GPIO34 VDI_D16 GPIO50 AO1_SD2 GPIO3 GPIO3 GPIO19 XIO_D15 GPIO35 PCI_GNT_B_N GPIO51 AO1_SD1 GPIO4 GPIO4 GPIO20 XIO_D14 GPIO36 PCI_GNT_A_N GPIO52 AO1_SD0 GPIO5 GPIO5 GPIO21 XIO_D13 GPIO37 PCI_REQ_A_N GPIO53 XIO_SEL2 GPIO6 GPIO6 GPIO22 XIO_D12 GPIO38 VDI_V2 GPIO54 XIO_SEL1 GPIO7 GPIO7 GPIO23 XIO_D11 GPIO39 VDI_V1 GPIO55 XIO_SEL0 GPIO8 XIO_SEL4 GPIO24 XIO_D10 GPIO40 AI1_SD3 GPIO56 XIO_ACK GPIO9 AI2_OSCLK GPIO25 XIO_D9 GPIO41 AI1_SD2 GPIO57 XIO_AD26 GPIO10 AO2_SD3 GPIO26 XIO_D8 GPIO42 AI1_SD1 GPIO58 XIO_AD25 GPIO11 AO2_SD2 GPIO27 VDI_D23 GPIO43 AI1_SD0 GPIO59 PCI_REQ_B_N GPIO12 AO2_SD1 GPIO28 VDI_D22 GPIO44 AI1_WS GPIO60 PCI_GNT_N GPIO13 AO2_SD0 GPIO29 VDI_D21 GPIO45 AI1_BCK - - GPIO14 VDI_HOR GPIO30 VDI_D20 GPIO46 AI1_OSCLK - - GPIO15 VDI_VER GPIO31 VDI_D19 GPIO47 USB_VBUS_FLT - - FT FT A A Function D D R A FT D R M A 8.2 Digital video input formats O The PNX9530; PNX9531; PNX9535 accepts several digital video input formats (see Table 22). For restrictions see Table 21. FI C Restrictions on digital video input formats Restriction on Digital input formats (mutually exclusive options)[1] 8-bit and 8-bit 24-bit Dual ITU656, external and embedded sync Dual ITU656, external sync ITU656, embedded sync and TS RGB 8 in, 8 out 4 in, 4 out 8 in, 8 out 4 in, 4 out O Dual ITU656, embedded sync 2 × 10-bit N 2 × 8-bit 8 in, 8 out Host interface available available cannot be used available cannot be used Video output no restrictions no restrictions restricted to 2 × 18-bit no restrictions restricted to 2 × 18-bit C Maximum number of audio I/Os [1] For further details on availability or conflicts see Table 19. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 F D D Pin GPIO0 Table 21. A FT FT A A R R R Default configuration PA D EN NY TI A L R A D D Default configuration D R FT FT A A R R D D D Default configuration FT FT FT FT Default configuration A A A A R R D D D Default configuration FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 20. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors 38 of 72 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R - ITU_CLK - VDI_CLK2 ITU1_CLK ITU1_CLK - TS_CLK - VDI_V0 - - - - - VDI_V1 - - - - - VDI_V2 - - - TS_VALID CLK_IN VDI_HOR - ITU1_HOR ITU2_HOR TS_START HSYNC_IN VDI_VER - ITU1_VER ITU2_VER TS_STOP VSYNC_IN VDI_D0 ITU1_D0 ITU1_D0 ITU1_HOR TS_D0 R0 VDI_D1 ITU1_D1 ITU1_D1 ITU1_VER TS_D1 B0 VDI_D2 ITU1_D2 ITU1_D2 - TS_D2 G0 VDI_D3 ITU1_D3 ITU1_D3 - TS_D3 R1 VDI_D4 ITU1_D4 ITU1_D4 ITU2_D0 TS_D4 B1 VDI_D5 ITU1_D5 ITU1_D5 ITU2_D1 TS_D5 G1 VDI_D6 ITU1_D6 ITU1_D6 ITU1_D0 TS_D6 R2 VDI_D7 ITU1_D7 ITU1_D7 ITU1_D1 TS_D7 B2 VDI_D8 ITU2_D0 ITU2_D0 ITU1_D2 ITU_D0 G2 VDI_D9 ITU2_D1 ITU2_D1 ITU1_D3 ITU_D1 R3 VDI_D10 ITU2_D2 ITU2_D2 ITU1_D4 ITU_D2 B3 VDI_D11 ITU2_D3 ITU2_D3 ITU1_D5 ITU_D3 G3 VDI_D12 ITU2_D4 ITU2_D4 ITU1_D6 ITU_D4 R4 VDI_D13 ITU2_D5 ITU2_D5 ITU1_D7 ITU_D5 B4 VDI_D14 ITU2_D6 ITU2_D6 ITU1_D8 ITU_D6 G4 VDI_D15 ITU2_D7 ITU2_D7 ITU1_D9 ITU_D7 R5 VDI_D16 - - ITU2_D2 - B5 VDI_D17 - - ITU2_D3 - G5 VDI_D18 - - ITU2_D4 - R6 VDI_D19 - - ITU2_D5 - B6 VDI_D20 - - ITU2_D6 - G6 VDI_D21 - - ITU2_D7 - R7 VDI_D22 - - ITU2_D8 - B7 VDI_D23 - - ITU2_D9 - G7 D - ITU1_CLK FT ITU2_CLK ITU2_CLK A - ITU2_CLK R - VDI_CLK1 R VDI_CLK0 D RGB FT ITU656, embedded sync and TS A 24-bit Dual ITU656, external sync R 8-bit and 8-bit Dual ITU656, external and embedded sync F D D 2 × 10-bit Dual ITU656, embedded sync A FT FT A A R R D D D Digital input formats (mutually exclusive options) 2 × 8-bit FT FT FT FT Input pin A A A A R R D D D Digital video input formats[1] FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 22. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors A FT M O N FI O C A C R PA D EN NY TI A L D [1] For pinning see Table 7 and Table 19. For restrictions see Table 21. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 39 of 72 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D FT FT A A R R D D A Unit R Max D Min FT D +1.5 V VDDA(CAB)(3V3) CAB analog supply voltage (3.3 V) −0.5 +3.8 V VDDA(CAB/DDS) CAB/DDS analog supply voltage −0.5 +1.5 V VDDA(CGU/PLL) CGU/PLL analog supply voltage −0.5 +1.5 V VDDA(DDR/PLL) DDR/PLL analog supply voltage −0.5 +1.5 V VDDA(DLL0) DLL0 analog supply voltage −0.5 +1.5 V VDDA(DLL1) DLL1 analog supply voltage −0.5 +1.5 V VDDA(DLL2) DLL2 analog supply voltage −0.5 +1.5 V VDDA(OSC) oscillator analog supply voltage −0.5 +1.5 V VDDA(DRV)(USB) USB driver analog supply voltage −0.5 +4.0 V VDDA(FB)(1V2) FB analog supply voltage (1.2 V) −0.5 +1.5 V VDDA(USB) USB analog supply voltage −0.5 +4.0 V −0.5 +1.5 V −0.5 +3.8 V Digital supplies PA D EN NY TI A L −0.5 core digital supply voltage VDDD(IO) I/O digital supply voltage VDDD(IO)(DDR) DDR input/output digital supply voltage −0.5 +3.0 V VDDD(IO)(PCI) PCI input/output digital supply voltage −0.5 +5.5 V −40 +150 °C −40 +85 °C 5 V tolerant inputs −0.5 5.5 V 3.3 V tolerant inputs; with VDDD(IO) −0.5 3.8 V 1.8 V and 2.5 V tolerant inputs; with VDDD(IO)(DDR) −0.5 3.0 V storage temperature Tamb ambient temperature Input voltages input voltage C O Tstg N Temperature FI C O M VDDD(C) electrostatic discharge voltage [1] Class 2 according to JEDEC JESD22-A114. [2] Class B according to JEDEC JESD22-A115. [3] Class III following JEDEC JESD22-C101. human body model [1] - ±2000 V machine model [2] - ±200 V charge device model [3] corner pins - ±750 V all other pins - ±500 V PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 40 of 72 A CAB analog supply voltage (1.2 V) R VDDA(CAB)(1V2) VESD A FT FT A A R R D D D Conditions Analog supplies VI FT FT FT FT Table 23. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Parameter A A A A R R D D D 9. Limiting values FT FT FT FT FT Software enabled video and multimedia entertainment platform Symbol A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R D The customer PCB must be reviewed by NXP experts to check the thermal resistance of the system. 11. Static characteristics PA D EN NY TI A L Table 25. Characteristics (supply pins) Operating conditions for minimum and maximum values in Table 26 to Table 34 hold for conditions given in Table 25 and Tamb = −40°C to Tamb =+85°C, unless otherwise stated. Parameter Conditions Analog supplies Min Typ Max Unit CAB analog supply voltage (1.2 V) 1.16 1.20 1.24 V VDDA(CAB)(3V3) CAB analog supply voltage (3.3 V) 3.15 3.30 3.45 V VDDA(CAB/DDS) CAB/DDS analog supply voltage 1.16 1.20 1.24 V VDDA(CGU/PLL) CGU/PLL analog supply voltage 1.16 1.20 1.24 V VDDA(DDR/PLL) DDR/PLL analog supply voltage 1.16 1.20 1.24 V VDDA(DLL0) DLL0 analog supply voltage 1.16 1.20 1.24 V VDDA(DLL1) DLL1 analog supply voltage 1.16 1.20 1.24 V VDDA(DLL2) DLL2 analog supply voltage 1.16 1.20 1.24 V VDDA(OSC) oscillator analog supply voltage 1.16 1.20 1.24 V VDDA(DRV)(USB) USB driver analog supply voltage 3.15 3.30 3.45 V VDDA(FB)(1V2) FB analog supply voltage (1.2 V) 1.16 1.20 1.24 V VDDA(USB) USB analog supply voltage 3.15 3.30 3.60 V O N FI C O M VDDA(CAB)(1V2) C VDDD(C) core digital supply voltage 1.16 1.20 1.24 V VDDD(IO) I/O digital supply voltage 3.15 3.30 3.45 V VDDD(IO)(DDR) DDR input/output digital supply voltage normal mode (DDR2) 1.70 1.80 1.90 V 333 MHz to 400 MHz (DDR1) 2.40 2.55 2.70 V with 3.3 V supply 3.00 3.30 3.60 V with 5 V supply 4.75 5.00 5.25 V for all supplies - 2.07 - W for VDDD(C) - 1.20 - W for VDDD(IO)(DDR) - 0.54 - W for VDDD(IO) - 0.33 - W VDDD(IO)(PCI) PCI input/output digital supply voltage Power dissipation Ptot total power dissipation PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 41 of 72 A [2] R The overall Rth(j-a) can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly. An ample amount of copper area directly under the PNX9530; PNX9531; PNX9535 with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Do not use any solder-stop varnish under the chip. In addition the use of soldering glue with a high thermal conductance after curing is recommended. D [1] FT K/W A 20 R Unit D in free air Typ FT [1][2] FT A A R Conditions thermal resistance from junction to ambient Digital supplies F D D Parameter Symbol A FT FT A A R R D D D Rth(j-a) FT FT FT FT Thermal characteristics Symbol A A A A R R D D D 10. Thermal characteristics FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 24. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R D R R FT 5.3 5 V or 3.3 V −0.3 - +0.3 × VDDD V 0.9 × VDDD - - V A FT D - - 8 pF Symbol Parameter Conditions Input buffers DC HIGH-level input voltage VIL(DC) DC LOW-level input voltage VIH(AC) AC HIGH-level input voltage M VIH(DC) VIL(AC) PA D EN NY TI A L Table 27. Characteristics (DDR1 (SSTL-2); all DDR SDRAM pins, besides pin MM_VREF) All DDR1 values are expected, neither tested nor guaranteed.. AC LOW-level input voltage O Output buffers HIGH-level output voltage VOL LOW-level output voltage IOH HIGH-level output current IOL LOW-level output current Zo output impedance Typ Max [1] VREF + 0.15 - VDD + 0.30 V [1] −0.30 - VREF - 0.15 V [1][2] VREF + 0.31 - - V [1][2] - - VREF - 0.31 V VDD - 0.56 - - V - 0.56 - V 14 - - mA 14 - - mA 28 - 39 Ω N FI C VOH Min Unit In this context VREF denotes the reference voltage supplied through pin MM_VREF and VDD denotes the supply voltage VDDD(IO)(DDR). [2] These values are specified with respect to the supply voltage and not with respect to the input signal levels. C O [1] Table 28. Characteristics (DDR2 (SSTL-18); all DDR SDRAM pins, besides pin MM_VREF) All values are valid within the operating conditions. Symbol Parameter Conditions Min Typ Max Unit Input buffers DC HIGH-level input voltage [1] VREF + 0.125 - VDD + 0.30 V DC LOW-level input voltage [1] −0.30 - VREF - 0.125 V VIH(AC) AC HIGH-level input voltage [1][2] VREF + 0.25 - - V VIL(AC) AC LOW-level input voltage [1][2] - - VREF - 0.25 V VIH(DC) VIL(DC) PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 42 of 72 A ns R V D 0.1 × VDDD - FT - A 1.3 R In this context VDDD means VDDD(IO)(PCI). R See Table 18. [2] V VDDD + 0.3 D [1] F - 0.7 × VDDD A 0.7 × VDDD 3.3 V D 5V between 0.2 × VDDD and 0.6 × VDDD Unit FT input capacitance Max FT Ci Typ A fall time Min R LOW-level output voltage tf Conditions D VOL FT HIGH-level output voltage R A A VOH D R R LOW-level input voltage R A D D VIL D R FT FT A A R R D D D HIGH-level input voltage VIH FT FT FT FT Symbol Parameter A A A A R R D D D Characteristics (type P pins[1][2]) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 26. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R D R R D R D R FT FT A A R 6 - - mA IOL LOW-level output current 6 - - mA Zo output impedance 31 - 44 Ω In this context VREF denotes the reference voltage supplied through pin MM_VREF and VDD denotes the supply voltage VDDD(IO)(DDR). These values are specified with respect to the supply voltage and not with respect to the input signal levels. 2" true length rise/fall test point FI output buffer C package pin O M PA D EN NY TI A L [1] [2] 50 Ω N 001aak138 O VIH(DC) VREF VIL(DC) VIL(AC) 10 pF 001aak147 Fig 10. SSTL-2 and SSTL-18 receiver signal conditions C SSTL-2 and SSTL-18 test load conditions VIH(AC) Characteristics (type I2 pins[1]) Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage 2.3 - 5.3 V VIL LOW-level input voltage −0.3 - +1.0 V VOL LOW-level output voltage - - 0.6 V Vhys hysteresis voltage 0.25 - - V tf fall time Ci input capacitance CL = 10 pF to 400 pF 1.5 - 250 ns - - 6 pF See Table 18. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 43 of 72 A HIGH-level output current R IOH D V D V - FT - 0.28 A - - R VDD - 0.28 LOW-level output voltage D HIGH-level output voltage VOL [1] F FT D VOH Table 29. A A FT Unit Output buffers Fig 9. R FT R A Max R Typ A D D Min D R FT FT A A R R D D D Conditions FT FT FT FT Parameter A A A A R R D D D Table 28. Characteristics (DDR2 (SSTL-18); all DDR SDRAM pins, besides pin MM_VREF) …continued All values are valid within the operating conditions. FT FT FT FT FT Software enabled video and multimedia entertainment platform Symbol A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R D R R FT VDDD(IO) + 0.3 - +0.3 × VDDD(IO) V VOH HIGH-level output voltage 0.9 × VDDD(IO) - - V VOL LOW-level output voltage - - 0.1 × VDDD(IO) V IOH HIGH-level output current at VOH = VDDD(IO) - 0.4 V 16 - - mA IOL LOW-level output current at VOL = 0.4 V 16 - - mA Ipu pull-up current 25 50 85 µA Ipd pull-down current 25 50 85 µA FT - 3 pF Zo output impedance 15 20 25 Ω Min Typ Max Unit PA D EN NY TI A L - LOW-level input voltage VOH HIGH-level output voltage VOL LOW-level output voltage M HIGH-level input voltage O VIH VIL 0.7 × VDDD(IO) - VDDD(IO) + 0.3 V −0.3 - +0.3 × VDDD(IO) V 0.9 × VDDD(IO) - - V - - 0.1 × VDDD(IO) V 0.1 × VDDD(IO) - - V HIGH-level output current at VOH = VDDD(IO) - 0.4 V 4.0 - - mA IOL LOW-level output current at VOL = 0.4 V 4.0 - - mA Ipu pull-up current 25 50 85 µA Ipd pull-down current 25 50 85 µA tr rise time 0.5 - 1.5 ns tf fall time 0.5 - 1.8 ns Ci input capacitance - - 3.5 pF Zo output impedance 40 50 60 Ω [1] C O N FI hysteresis voltage C Vhys IOH See Table 18. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 44 of 72 A input capacitance R Ci D ns D ns 1.5 FT 1.0 - A - 0.5 R 0.5 fall time D rise time Conditions FT A tr Symbol Parameter A V tf Characteristics (type L pins[1]) F - −0.3 R 0.7 × VDDD(IO) LOW-level input voltage Table 31. A D HIGH-level input voltage R D VIH See Table 18. FT FT Unit VIL [1] R A A Max D R R Typ R A D D Min D R FT FT A A R R D D D Conditions FT FT FT FT Symbol Parameter A A A A R R D D D Characteristics (type H pins[1]) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 30. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R D R R FT V VOH HIGH-level output voltage 0.9 × VDDD(IO) - - V VOL LOW-level output voltage - - 0.1 × VDDD(IO) V FT pull-down current 25 50 85 µA tr rise time 1 - 2 ns tf fall time 1 - 2 ns Ci input capacitance - - 4 pF Zo output impedance 40 50 60 Ω PA D EN NY TI A L Ipd HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VOL LOW-level output voltage Vhys hysteresis voltage Ipu pull-up current Ipd pull-down current tr rise time tf fall time Ci input capacitance Zo output impedance O N FI C O VIL VOH M VIH See Table 18. [2] In this context VDDD means VDDD(IO)(DDR).^ Typ Max Unit 0.7 × VDDD - VDDD + 0.3 V −0.3 - +0.3 × VDDD V 0.9 × VDDD - - V - - 0.1 × VDDD V 0.1 × VDDD - - V 25 50 85 µA 25 50 85 µA 2 - 4 ns 2 - 4 ns - - 4.5 pF 40 50 60 Ω C [1] Min PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 45 of 72 A µA D V 85 FT - 50 A - 25 R 0.1 × VDDD(IO) pull-up current D hysteresis voltage Conditions FT A Vhys Ipu Symbol Parameter A V R +0.3 × VDDD(IO) D VDDD(IO) + 0.3 - Characteristics (type S pins[1][2]) F - −0.3 R 0.7 × VDDD(IO) LOW-level input voltage Table 33. A D HIGH-level input voltage R D VIH See Table 18. FT FT Unit VIL [1] R A A Max D R R Typ R A D D Min D R FT FT A A R R D D D Conditions FT FT FT FT Symbol Parameter A A A A R R D D D Characteristics (type F pins[1]) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 32. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R D R R FT V VOH HIGH-level output voltage 0.9 × VDDD - - V VOL LOW-level output voltage - - 0.1 × VDDD V FT pull-down current 25 50 85 µA tr rise time 2 - 4 ns tf fall time 2 - 4 ns Ci input capacitance - - 4.5 pF Zo output impedance 40 50 60 Ω Symbol Parameter PA D EN NY TI A L Ipd Conditions Analog input (pin USB_VBUS) A-device session valid voltage VA_VBUS_VLD A-device VBUS valid voltage VB_SESS_VLD B-device session valid voltage VB_SESS_END B-device session end voltage O M VA_SESS_VLD Min Typ Max Unit 0.8 - 2 V 4.4 - - V 2 - 4 V 0.2 - 0.8 V FI C Analog inputs and outputs (pins USB_DM and USB_DP) differential common mode voltage range 800 - 2500 mV VDI differential input sensitivity voltage 100 400 1100 mV VHSCM high-speed data signaling common mode voltage range (guideline for receiver) −50 +200 +500 mV O See Table 18. C [1] N VCM PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 46 of 72 A µA D V 85 FT - 50 A - 25 R 0.1 × VDDD pull-up current D hysteresis voltage Characteristics (type U pins[1]) FT A Vhys Ipu Table 35. A V R +0.3 × VDDD D - In this context VDDD means VDDD(IO)(PCI). F VDDD + 0.3 −0.3 R - LOW-level input voltage [2] A D 0.7 × VDDD R D HIGH-level input voltage VIL See Table 18. FT FT Unit VIH [1] R A A Max D R R Typ R A D D Min D R FT FT A A R R D D D Conditions FT FT FT FT Symbol Parameter A A A A R R D D D Characteristics (type T pins[1][2]) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 34. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 12. Dynamic characteristics FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D FT FT A A R R D Table 36. Characteristics (DDR SDRAM memory interface) Operating conditions for minimum and maximum values in Table 36 to Table 42 hold for conditions given in Table 25 and Tamb = +25°C, unless otherwise stated. All DDR1 values are expected, neither tested nor guaranteed.. D D R A Typ Max Unit DDR2 mode 125 - 266 MHz A Min Clock (pins MM_CLK_N and MM_CLK_P) fclk clock frequency DDR1 mode 83 - 200 MHz tsk skew time between MM_CLK_N and MM_CLK_P −10 0 +10 ps tPD propagation delay on PCB −240 0 +240 ps propagation delay on PCB O M PA D EN NY TI A L Control and data tPD Outputs rise time tf fall time C tr pins MM_A[13:0], MM_CAS_N, MM_CKE, MM_CS_N, MM_RAS_N and MM_WE_N −480 0 +480 ps pins MM_DS_N[3:0] and MM_DS_P[3:0] −120 0 +120 ps pins MM_D[31:0] and MM_DM[3:0] 0 - 240 ps DDR2 mode 80 - 120 ps DDR1 mode 40 - 120 ps FI fall time N tf rise time O tr C Inputs DDR2 mode 60 - 100 ps DDR1 mode 40 - 90 ps DDR2 mode 136 217 380 ps DDR1 mode 99 131 247 ps DDR2 mode 168 275 554 ps DDR1 mode 111 158 308 ps PNX9530_PNX9531_PNX9535_1 Preliminary data sheet R Conditions D Parameter FT Symbol © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 47 of 72 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Max Unit clock frequency pins VDI_CLK2 to VDI_CLK0 - - 157 MHz pin VDI_D2, when used as dv0_clkn - - 108 MHz pin VDI_D3, when used as dv1_clkn - - 108 MHz FT FT A A R R D D D fclk R A R A input set-up time [1] 2 - - ns th(i) input hold time [1] 2 - - ns PA D EN NY TI A L The reference clock depends on the operating mode; see Figure 11. tsu(i) O Fig 11. VDI interface timing Characteristics (VDO interface) Parameter C Min Typ Max Unit VDO_MODE.QVCP_MODE = logic 1 and VDO_MODE.QVCP_DUAL_ EDGE = logic 0 [1][2][3] - - 157 MHz VDO_MODE.QVCP_MODE = logic 1 and VDO_MODE.QVCP_DUAL_ EDGE = logic 1 [1][3] - - 81 MHz VDO_MODE.VDO_BUFFER _MODE = logic 1 [1][3] - - 30 MHz PNX9530_PNX9531_PNX9535_1 Preliminary data sheet 001aak148 Conditions FI clock frequency O fclk VALID N Clock (pin VDO_CLK) C Symbol tn(i) M VDI_D[23:0] VDI_V[1:0] © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 D tsu(i) VDI{2, 1, 0}_CLK VDI_D[3:2] FT Control and data (pins VDI_CLK2 to VDI_CLK0, VDI_D[23:0], VDI_HOR and VDI_VER) Table 38. F Typ D Min A FT Conditions FT A A R R D D D Parameter Clock [1] FT FT FT FT Symbol A A A A R R D D D Characteristics (VDI interface) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 37. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors 48 of 72 D D D D D R R R R R D R R D R FT FT FT A A A R D 3 - 9 ns Buffer: VDO_CLK referenced to pins VDO[47:0], VDO_AUX1, VDO_HOR and VDO_VER; VDO_MODE.VDO_BUFFER _MODE = logic 1 [1][3] 5 - 20 ns QVCP block: VDO_CLK referenced to pins VDO[29:0], VDO_AUX1, VDO_HOR and VDO_VER; VDO_MODE.QVCP_MODE = logic 1 ; VDO_CLK as output [1] 1.2 - 3.9 ns D [1] R A FT D R PA D EN NY TI A L A input hold time QVCP block: VDO_CLK referenced to pins VDO[29:0], VDO_AUX1, VDO_HORand VDO_VER; VDO_MODE.QVCP_MODE = logic 1 ; VDO_CLK as input D input set-up time FT tsu(i) FT A A R R D data output valid delay time [1][3] 3 - - ns VDO_VER to VDO_CLK [1][3] 2 - - ns M VDO_VER to VDO_CLK VDO_MODE.QVCP_MODE and VDO_MODE.VDO_BUFFER_MODE are mutually exclusive. [2] When pin VDO_CLK is set as an input, the AC timing of the remaining VDO pins may not allow to run at the maximum operating frequency. [3] Data are the same for both input or output mode of pin VDO_CLK. N td(QV), td(DV) O VDO_CLK FI C O [1] VDO_D[47:0] VDO_VER VDO_HOR C VALID VDO_CLK tsu(i) VDO_VER VDO_HOR th(i) VALID 001aak149 Fig 12. VDO interface timing PNX9530_PNX9531_PNX9535_1 Preliminary data sheet F Unit A Max FT Typ FT A A R R D D D data valid delay time td(QV) th(i) R R R Min Data, see Figure 12 td(DV) D D D Conditions FT FT FT FT Parameter A A A A R R D D D Characteristics (VDO interface) …continued Symbol FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 38. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 49 of 72 D D D D D R R R R R D R R D A FT R Max Unit clock frequency AI12_OSCLK and AI2_OSCLK - - 50 MHz AI1_BCK and AI2_BCK - - 27 MHz FT FT A A R R D D D R A R A AI1_BCK to AI1_WS; AI2_BCK to AI2_WS [1] 4 - 12 ns tsu(i) input set-up time AI1_SD[3:0], AI1_WS to AI1_BCK; AI2_SD[3:0], AI_WS2 to AI2_BCK [1] 4 - - ns th(i) input hold time AI1_SD[3:0], AI1_WS to AI1_BCK; AI2_SD[3:0], AI_WS2 to AI2_BCK [1] 0 - - ns PA D EN NY TI A L propagation delay O M Data are the same for both input or output mode of pins AI1_BCK or AI2_BCK (master or slave). They hold for both rising or falling edge. For functional pins see Section 8.1. tsu(i) th(i) VALID C AI1_SD[3:0] AI2_SD[3:0] AI1_WS AI2_WS VALID N O AI1_SCLK AI2_SCLK tPD FI C AI1_WS AI2_WS 001aak139 Fig 13. AI interface timing PNX9530_PNX9531_PNX9535_1 Preliminary data sheet D tPD AI1_SCLK AI2_SCLK FT Data, see Figure 13 [1] F Typ D Min A FT Conditions FT A A R R D D D fclk R R FT FT A A R R D D D Parameter Clock FT FT FT FT Symbol A A A A R R D D D Characteristics (digital audio input interface) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 39. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 50 of 72 D D D D D R R R R R D R R D A FT R Max Unit clock frequency AO12_OSCLK and AO2_OSCLK - - 50 MHz AO12_BCK and AO2_BCK - - 27 MHz FT FT A A R R D D D R A R A AO12_BCK to AO1_SD[3:0], AO2_SD[3:0], AO12_WS; AO2_BCK to AO2_SD[3:0], AO2_WS [1] 4 - 12 ns tsu(i) input set-up time AO12_WS to AO12_BCK; AO2_WS to AO2_BCK [1] 4 - - ns th(i) input hold time AO12_WS to AO12_BCK; AO2_WS to AO2_BCK [1] - ns PA D EN NY TI A L propagation delay 0 - C O M Data are the same for both input or output mode of pins AI1_BCK or AI2_BCK (master or slave). They hold for both rising or falling edge. For functional pins see Section 8.1. C AO1_SD[3:0] AO2_SD[3:0] AO12_WS AO2_WS VALID N O AO12_SCLK AO2_SCLK tPD FI AO1_SD[3:0] AO2_SD[3:0] AO12_WS AO2_WS tsu(i) th(i) VALID 001aak140 Fig 14. AO interface timing PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 D tPD AO12_SCLK AO2_SCLK FT Data, see Figure 14 [1] F Typ D Min A FT Conditions FT A A R R D D D fclk R R FT FT A A R R D D D Parameter Clock FT FT FT FT Symbol A A A A R R D D D Characteristics (digital audio output interface) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 40. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors 51 of 72 D D D D D R R R R R D R R FT D [2] - - 108 MHz CLOCK[6:0] to GPIO[7:0] [3] 2 - 10 ns CLOCK[6:0] to GPIO[60:8]] [3] 4 12 ns GPIO[7:0] to CLOCK[6:0] [3] 2 - ns GPIO[60:8] to CLOCK[6:0] [3] 5 - ns GPIO[7:0] to CLOCK[6:0] [3] 2 - ns GPIO[60:8] to CLOCK[6:0] [3] - ns FT D R A A - - PA D EN NY TI A L See Table 19. 4 - The maximum operating frequency may be lower due to the wide variation of tPD. Data are the same for both input or output mode of these pins. They hold for both rising or falling edge.. See table note in Table 10 for clock and data assignments. O M [2] [3] tPD FI C GPIO[6:0] VALID O N GPIO[61:0] C GPIO[6:0] GPIO[61:0] tsu(i) th(i) VALID 001aak142 Fig 15. GPIO interface timing PNX9530_PNX9531_PNX9535_1 Preliminary data sheet R input hold time D input set-up time FT [1] D propagation delay th(i) FT A Data, see Figure 15 tsu(i) A R R D clock frequency tPD F Unit D Max A FT Typ FT A A R R R Min Clock fclk R A D D Conditions D R FT FT A A R R D D D Parameter FT FT FT FT Symbol A A A A R R D D D Characteristics (GPIO interface)[1] FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 41. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 52 of 72 D D D D D R R R R R D R R FT D 15 - - ns 6 - - ns trst-off reset active to output float delay time pins RESET_IN_N and POR_IN_N tsu input set-up time to CLK bused signals clock at pin PCI_CLK 6 ns 2 - 6 ns - - 40 ns Data pins PA D EN NY TI A L [6][7] PCI-bus pins XIO_ACK and XIO_D[15:8] tsu(ptp) input set-up time to CLK point-to-point clock at pin PCI_CLK th input hold time from CLK clock at pin PCI_CLK [5] active to float delay time td delay time See Figure 17. PCI-bus and XIO interface. ns ns 5 - - ns 0 - - ns 0 - - ns 2 - - ns between pin PCI_CLK and pins XIO_AD[26:25], XIO_SEL[4:0] and XIO_D[15:8] [5] - - 14 ns 2 - 10 ns FI [1] [2] - N C O toff [5] M signals XIO_ACK and XIO_D[15:8] float to active delay time - - [6][7] PCI-bus ton 3 9 Valid for all XIO signals from Table 19, besides XIO_ACK. See Figure 16 for measurement conditions of minimum and maximum values. [5] See Table 19. [6] 5 V signalling: Vth = 2.4 V, Vtl = 0.4 V and Vmax = 2.0 V [7] 3.3 V signalling: Vth = 0.6 × VDDD(IO)(PCI), Vtl = 0.2 × VDDD(IO)(PCI) and Vmax = 0.4 × VDDD(IO)(PCI) C O [3] [4] pin pin 1/2 in. max output buffer Vccp 1 kΩ 10 pF output buffer pin 1/2 in. max output buffer 25 Ω 1 kΩ 001aaj947 a. Slew rate 10 pF 1/2 in. max Vccp 10 pF 001aaj948 b. Rising edge 25 Ω 001aaj949 c. Falling edge Fig 16. Type P cell test load conditions; see Table 18 PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 53 of 72 A [3][4] - R pin PCI_CLK only 2 D CLK to signal valid delay time - point-to-point ns D tval(ptp) - FT pin PCI_CLK only - A CLK to signal valid delay time - bused signals 6 R tval [3][4] D CLK low time FT tlow FT A CLK high time A R thigh R D [2] cycle time F Unit D Max A FT Typ FT A A R R R Min Clock (pins PCI_CLK and PCI_SYS_CLK) Tcy R A D D Conditions D R FT FT A A R R D D D Parameter FT FT FT FT Symbol A A A A R R D D D Characteristics (PCI-bus and XIO interface)[1] FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 42. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT th FT A A R R D tsu A A A A R R D D D Software enabled video and multimedia entertainment platform PCI CLK FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A PCI-XIO INPUTS FT toff R A td D ton PCI-XIO OUTPUTS 001aak733 Fig 17. PCI-bus and XIO interface timing Table 43. Characteristics (host interface) Parameter Conditions Max Unit T period access time, i.e. delay between two consecutive HOSTIF_CS_N falling edges [1] 40 - - ns tsu(W) write set-up time HOSTIF_D[15:0] and HOSTIF_CLE rising edge to rising edge of HOSTIF_WR_N and rising edge of HOSTIF_CS_N [1] 10 - - ns th(W) write hold time HOSTIF_D[15:0] and falling edge of HOSTIF_CLE to rising edge of HOSTIF_WR_N or rising edge of HOSTIF_CS_N [1] 5 - - ns td(WV) write valid delay time between a rising edge on HOSTIF_WR_N and a falling edge on HOSTIF_CS_N, i.e. delay between end of write and next access [1] 10 - - ns td(o) output delay time falling edge of HOSTIF_RD_OE_N and falling edge of HOSTIF_CS_N to HOSTIF_D[15:0 [2] 2.5 - 13 ns th(o) output hold time rising edge of HOSTIF_RD_OE_N and rising edge of HOSTIF_CS_N to HOSTIF_D[15:0] [2] 2.5 - 13 ns M O Typ O N FI C Min PA D EN NY TI A L Symbol HOSTIF_RD_OE_N is constant logic 1 during a write command; see Figure 18. [2] HOSTIF_WR_N is a constant logic 1 and HOSTIF_CLE is a constant logic 0 during read command. C [1] PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 54 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT td(o) FT A A R R D td(WV) th(W) A A A A R R D D D Software enabled video and multimedia entertainment platform T FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R tsu(W) A FT D R A HOSTIF_CS_N HOSTIF_WR_N HOSTIF_CLE HOSTIF_D[15:0] HOSTIF_RD_OE_N READ PA D EN NY TI A L WRITE td(o) th(o) 001aak143 Table 44. M Fig 18. Host interface timing Characteristics (reset interface[1][2], see Figure 19) Parameter tpor reset active time after power stable trst reset time Conditions Min Typ Max Unit pin POR_IN_N 1 - - ms pin RESET_IN_N 100 - - µs FI C O Symbol POR_IN_N and RESET_IN_N are asynchronous signals. [2] At power-up only POR_IN_N is required to be asserted. RESET_IN_N can be used as warm reset and left unconnected if not used as warm reset. Note that the JTAG state machines do not get reset when only RESET_IN_N is being asserted low. O N [1] C tpor VDDD(C) POR_IN_N trst RESET_IN_N 001aak760 Fig 19. Reset interface timing PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 55 of 72 D D D D D R R R R R D R R FT D clock frequency - - 400 kHz tBUF bus free time between a STOP and START condition 1 - - µs tLOW LOW period of the SCL clock 1 - - µs tHIGH HIGH period of the SCL clock 1 - - µs tf fall time of both SCL and SDA signals 20 + 0.1 × Cb - 250 ns tSU; STA set-up time for a repeated START condition 1 - - µs tHD; STA hold time (repeated) START condition 1 - - µs F Max Unit FT FT A A R R D D Typ Clock A FT FT A A R R R Min D D fclk R A D D Conditions D R FT FT A A R R D D D Parameter FT FT FT FT Symbol A A A A R R D D D Characteristics (I2C-bus interface) FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 45. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors R A Data PA D EN NY TI A L 100 - - ns 0 - - ns LOW to data out valid - - 0.5 µs HIGH to data out 1 - - ns M data valid time A tVD; DAT O SDA tLOW S tHD;DAT tHIGH tSU;DAT S P tSU;STA tSU;STO 001aak153 O tHD;STA tHD;STA FI P tf N SCL tr C tBUF C Fig 20. I2C-bus interface timing Table 46. Characteristics (JTAG interface) Symbol Parameter Conditions Min Typ Max Unit Clock fclk clock frequency boundary scan - - 25 MHz operating frequency - - 50 MHz 0 - 5 ns Data, see Figure 21 tPD propagation delay tsu(i) input set-up time 5 - - ns th(i) input hold time 3 - - ns PNX9530_PNX9531_PNX9535_1 Preliminary data sheet R data hold time D data set-up time FT tSU; DAT tHD; DAT Cb = 10 pF to 400 pF, from VIH to VIL © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 56 of 72 D D D D D R R R R R A A A A A FT FT FT FT FT PNX9530; PNX9531; PNX9535 D R R FT FT FT FT Software enabled video and multimedia entertainment platform A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D JTAG_TCK tPD D D R A FT JTAG_TDI JTAG_TMS VALID D R A JTAG_TCK tsu(i) th(i) VALID JTAG_TDO Fig 21. JTAG interface timing 13. External crystal PA D EN NY TI A L 001aak141 13.1 With external crystal HC-49U Characteristics (external crystal HC-49U, pin XTAL_I) Symbol Parameter M Table 47. Conditions Min Typ Max Unit fundamental mode - 27.000 - MHz with temperature - ±30 - 10−6 −40 - +85 °C - - 18 pF - 18 - pF - - 7 pF crystal frequency relative crystal frequency variation Tamb ambient temperature Cext external capacitance CL load capacitance Cshunt shunt capacitance RESR equivalent series resistance - - 130 Ω Pdrive drive power - - 1 mW O N FI C O fxtal ∆fxtal/fxtal Table 48. C 13.2 In oscillator mode Characteristics (in oscillator mode, pin XTAL_I) Symbol Parameter Conditions Min Typ Max Unit ∆fxtal/fxtal relative crystal frequency variation with temperature - ±30 - 10−6 δ duty cycle 45 - 55 % Tamb ambient temperature −40 - +85 °C Cshunt shunt capacitance - - 7 pF PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 57 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 14.1 Quality information A A A A R R D D D Software enabled video and multimedia entertainment platform 14. Test information FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for use in automotive applications. A FT D R C O N FI C O M PA D EN NY TI A L A PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 58 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 15. Package outline FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D FT FT A A R R D BGA456: plastic ball grid array package; 456 balls; body 27 x 27 x 1.75 mm SOT795-1 D D R A FT D R B A D A D1 ball A1 index area A A2 E1 E PA D EN NY TI A L A1 detail X C e1 e M O AA M K H F D B U R e FI T P W N N V L J G y ∅w M C e2 1/2 e O Y C AB AE AC y1 C ∅v M C A B b E C A 1 shape 2 optional (4x) C AF AD 1/2 e 3 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 X 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D D1 E E1 e e1 e2 v w y y1 mm 2.45 0.6 0.4 1.85 1.60 0.7 0.5 27.2 26.8 24.75 23.75 27.2 26.8 24.75 23.75 1 25 25 0.3 0.15 0.2 0.35 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT795-1 144E MS-034 --- EUROPEAN PROJECTION ISSUE DATE 02-11-18 05-04-26 Fig 22. Package outline SOT795-1 (BGA456) PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 59 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D Footprint information for reflow soldering of BGA456 package FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors SOT795-1 D FT FT A A R R D D D R A FT D R A Hx P FI see detail X Generic footprint pattern Refer to the package outline drawing for actual layout C solder land O N C O M Hy PA D EN NY TI A L P solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 1.00 0.450 0.450 0.600 Hx Hy 27.575 27.575 Fig 23. Soldering footprint SOT795-1 (BGA456) PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 60 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 16. Soldering of SMD packages FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D FT FT A A R R D This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. D D R A FT D R 16.1 Introduction to soldering A PA D EN NY TI A L Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board O M Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. N FI C The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation C • • • • • • O Key characteristics in both wave and reflow soldering are: The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 61 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D A A R R D Key characteristics in reflow soldering are: A A A A R R D D D Software enabled video and multimedia entertainment platform 16.4 Reflow soldering FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors FT FT • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to D D R A Table 49. PA D EN NY TI A L heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 49 and 50 SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) ≥ 350 < 350 < 2.5 Table 50. M ≥ 2.5 235 220 220 220 Lead-free process (from J-STD-020C) < 350 350 to 2000 > 2000 260 260 260 260 250 245 250 245 245 O > 2.5 Volume (mm3) N < 1.6 1.6 to 2.5 Package reflow temperature (°C) FI C O Package thickness (mm) C Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24. PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 62 of 72 A • Reflow temperature profile; this profile includes preheat, reflow (in which the board is R window for a mix of large and small components on one board D • Solder paste printing issues including smearing, release, and adjusting the process FT higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D maximum peak temperature = MSL limit, damage level A A A A R R D D D Software enabled video and multimedia entertainment platform temperature FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R A FT minimum peak temperature = minimum soldering temperature D R A peak temperature PA D EN NY TI A L time 001aac844 MSL: Moisture Sensitivity Level Fig 24. Temperature profiles for large and small components 17. Abbreviations Abbreviations O Table 51. M For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. ADC Analog-to-Digital Converter FI Description C Acronym Audio Input AI2 Audio Input 2 interface N AI AO2 BOM C CAB Audio Output Audio Output 2 interface O AO Bill Of Materials Custom Analog Block CD Compact Disc CGU Clock Generation Unit CPU Central Processing Unit DAB Digital Audio Broadcast DAC Digital-to-Analog Converter DCS Device Status and Control DDR Double Data Rate DDS Direct Digital Synthesis DLL Delay-Locked Loop DLNA Digital Living Network Alliance[1] DMA Direct Memory Access DTL Device Transaction Level PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 63 of 72 D D D D D R R R R R A A A A A D R R D R D R F FT A A D R FT FT A A R D D R A FT D R Fuse Box R FB D Enhanced JTAG D EJTAG FT Edge-Dependent De-Interlacing A DVD-Descrambler EDDI R DVD-D D Digital Versatile Disc FT FT FT DVD A A A Digital Video R R R DV D D D Description FT FT FT FT Abbreviations …continued Acronym A A A A R R D D D Software enabled video and multimedia entertainment platform Table 51. FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors First-In First-Out FIR Finite Impulse Response FSE Front Seat Entertainment GPIO General Purpose Input and Output GUI Graphical User Interface HD High-Definition HDD Hard Disc Drive HDTV High-Definition TV HS High-Speed IC Integrated Circuit IDE Integrated Drive Electronics M I2C-bus Inter-IC bus I2S Input/Output FI International Telecommunication Union C ITU Inter-IC Sound O I/O PA D EN NY TI A L Fast General Purpose Interface FIFO Joint Electron Device Engineering Council[2] JPEG Joint Photographic Experts Group JTAG Joint Test Action Group N JEDEC C LSB Liquid Crystal Display O LCD LED Light Emitting Diode Least Significant Bit LUT Look-Up Table MBS Memory Based Scaler MMIO Memory Mapped I/O MPEG Moving Picture Expert Group MSB Most Significant Bit NTSC National Television Standards Committee OSD On-Screen Display OTG On-The-Go PAL Phase Alternating Line PCI-bus Peripheral Component Interconnect-bus PI Programming Interface PIO Programming I/O PLL Phase-Locked Loop PNX9530_PNX9531_PNX9535_1 Preliminary data sheet A FGPI © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 64 of 72 D D D D D R R R R R A A A A A D R R D R D R A F R A FT D D R A FT D R SoftWare D SW FT Stub Series Terminated Logic FT Standard-Definition TV SSTL[3] A Synchronous Dynamic RAM SDTV A SDRAM R Secure Digital card R SD card D Read/Write D R/W FT Rear Seat Entertainment A Red Green Blue RSE R RGB D Random Access Memory FT FT FT RAM A A A Quality Video Composition Processor R R R QVCP D D D Description FT FT FT FT Abbreviations …continued Acronym A A A A R R D D D Software enabled video and multimedia entertainment platform Table 51. FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors Transport Stream TSU Time Stamp Unit TV TeleVision UI User Interface USB Universal Serial Bus VBI Vertical Blanking Interval VDI ViDeo Input M VDO ViDeo Output Video Electronics Standards Association FI Video Graphics Array C VGA ViDeo Out Buffer O VDOB VESA PA D EN NY TI A L TriMedia TS A TM Video Input Processor XIO eXtended I/O N VIP An international, cross-industry collaboration of consumer electronics, computing industry and mobile device companies. [2] Nowadays called JEDEC Solid State Technology Association, or simply JEDEC. [3] EIA/JESD8-9b 2002 defines this standard for DDR SDRAM interfaces. C O [1] PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 65 of 72 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R F D FT D D R A Co-sited video — The video pixel are more regularly distributed across the video memory. FT A A R R D Bluetooth — A standard for wireless radio communications. A FT FT A A R R D D D 18. Glossary FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors FT D DDR1 — Same as DDR, see Table 51. R FLASH memory — Non-volatile memory that can be electrically erased and programmed. Interspersed video — The video pixel are interspersed in memory; the VDO module makes them accessible again. UV — The U- and V-components of a YUV signal. PA D EN NY TI A L WiFi — Wireless technology used to connect portable devices to the car. YUV — The color space used in the PAL analog television standard. 19. References Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 [3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 [4] UTMI+ Specification Rev. 1.0 [5] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05 [6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) (JESD22-A114D) FI C O M [1] Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) (JESD22-A115-A) [8] Field-Induced Charged-Device Model Test Method for Electrostatic Discharge-Withstand Thresholds of Microelectronic Components (JESD22-C101C) [9] Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test (IEC 61000-4-2) C O N [7] 20. Revision history Table 52. Revision history Document ID Release date Data sheet status Change notice Supersedes PNX9530_PNX9531_PN X9535_1 Preliminary data sheet - - PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 66 of 72 A DDR2 — DDR memory with 4-fold, instead of 2-fold, prefetch for high bandwidth storage. D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Software enabled video and multimedia entertainment platform D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 21.1 Data sheet status A FT FT A A R R D D D 21. Legal information FT FT FT FT FT PNX9530; PNX9531; PNX9535 NXP Semiconductors D D R Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. A Document status[1][2] FT D R A [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions PA D EN NY TI A L Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. O M Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 21.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. N FI C Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. C O Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21.4 Licenses ICs with JPEG functionality Purchase of an NXP Semiconductors IC with JPEG functionality does not convey an implied license under any patent right to use this IC in any JPEG application, e.g. a digital still picture camera. A license under the JPEG patent of Koninklijke Philips Electronics N.V. needs to be obtained via Philips Intellectual Property and Standards (www.ip.philips.com), e-mail: info.licensing@philips.com. 21.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. TriMedia — is a trademark of NXP B.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PNX9530_PNX9531_PNX9535_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 67 of 72 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A Flexible products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59, 60 Front seat entertainment . . . . . . . . . . . . . . . . . . . . . . . . . . 3 R D D A I I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 33 Image viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 In-car video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 10 C J PA D EN NY TI A L Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Bluetooth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Boot signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Camera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21, 39 CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19, 57 M D L LED control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 35 M Main control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Main type differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Multifunctional GPIO interface . . . . . . . . . . . . 15, 29, 34, 35 Multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Multimedia entertainment . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Multimedia platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3 Multiplexed GPIO interface . . . . . . . . . . . . . . 15, 29, 34, 35 O Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 OSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 33 O N FI C O DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Digital audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15, 35 Digital camera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Digital video . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14, 21, 35 Digital video input . . . . . . . . . . . . . . . . . . . . . . . . . . . .14, 35 Digital video output . . . . . . . . . . . . . . . . . . . . . . . . . . .14, 35 DLNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Dual video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Dual video decoding . . . . . . . . . . . . . . . . . . . . . . . . . .2, 3, 5 Dual video rendering . . . . . . . . . . . . . . . . . . . . . . . . .2, 3, 5 DVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 33 C Enhanced multimedia functionality . . . . . . . . . . . . . . . . . .34 Enhanced video functionality . . . . . . . . . . . . . . . . . . . . . .34 Enjoying movies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Enjoying music . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Entertainment platform . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Extended I/O interface . . . . . . . . . . . . . . . . . . . . . . . .31, 35 External PCI master . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 F Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 5, 35 Flexible platform . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 5, 35 P Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 59 PCB footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PCI master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PCI-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 31, 35 Personal devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Picture improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin type description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3 Playback device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Portable media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 continued >> PNX9530_PNX9531_PNX9535_1 © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 68 of 72 A High-quality video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 High-speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 35 R H D GPIO interface . . . . . . . . . . . . . . . . . . . . . . . . 15, 29, 34, 35 GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FT B G R Advanced audio processing . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15, 35 Audio playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Audio streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Preliminary data sheet F D D A A FT FT A A R R D D D 5 V tolerant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2, 20, 33 FT FT FT FT Numerics A A A A R R D D D 23. Index FT FT FT FT FT Software enabled video and multimedia entertainment platform E A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R D R R R A FT R F D FT FT A A R R D D D R A FT D R SD card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Software enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Soldering footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Soldering mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 A T U PA D EN NY TI A L Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .41 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Type differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 USB 2.0 Hi-Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 2 USB-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19, 33, 35 V O N FI C O M Video broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Video capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Video clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Video decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Video entertainment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Video format scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Video formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 38 Video input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14, 21, 35 Video output . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14, 22, 35 Video playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Video quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2, 3 Video rendering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Video sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 38 Video streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 C Wakeup signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 WiFi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 PNX9530_PNX9531_PNX9535_1 Preliminary data sheet A FT FT A A R R D D D S D R FT FT A A R R D D D Rear seat entertainment . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 RGB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23, 39 FT FT FT FT R A A A A R R D D D Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 FT FT FT FT FT Software enabled video and multimedia entertainment platform W A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 69 of 72 D D D D D R R R R R D R R FT D R M FI N A O R C D 70 of 72 FT PA D EN NY TI A L A O FT D C F A FT © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 R A PNX9530_PNX9531_PNX9535_1 Preliminary data sheet D Table 48. Characteristics (in oscillator mode, pin XTAL_I) . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 49. SnPb eutectic process (from J-STD-020C) . . . 62 Table 50. Lead-free process (from J-STD-020C) . . . . . . 62 Table 51. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 52. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 66 R Table 45. Table 46. Table 47. D Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. A FT FT Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. R A A Table 28. D R R Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. R A D D Table 9. Table 10. D R FT FT A A R R D D D Table 8. FT FT FT FT Table 7. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Main type differences . . . . . . . . . . . . . . . . . . . . .4 Pin allocation table[1][2][3] . . . . . . . . . . . . . . . . . .6 Pin description overview . . . . . . . . . . . . . . . . .10 Pin description (power supplies) . . . . . . . . . . .11 Pin description (DDR SDRAM memory interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Pin description (digital video input interface)[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pin description (digital video output interface)[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pin description (digital audio interface)[1] . . . . .15 Pin description (multifunctional GPIO interface)[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Pin description (PCI-bus interface)[1] . . . . . . . .17 Pin description (USB-bus interface)[1] . . . . . . .19 Pin description (JTAG interface) . . . . . . . . . . .19 Pin description (I2C-bus interface) . . . . . . . . . .19 Pin description (main control pins) . . . . . . . . . .19 Pin description (crystal oscillator pins) . . . . . .19 Pin description (not connected pins) . . . . . . . .20 Pin type description . . . . . . . . . . . . . . . . . . . . .20 Multiplexed GPIO functionality[1] . . . . . . . . . . .35 Default configuration . . . . . . . . . . . . . . . . . . . .38 Restrictions on digital video input formats . . . .38 Digital video input formats[1] . . . . . . . . . . . . . .39 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .40 Thermal characteristics . . . . . . . . . . . . . . . . . .41 Characteristics (supply pins) . . . . . . . . . . . . . .41 Characteristics (type P pins[1][2]) . . . . . . . . . . .42 Characteristics (DDR1 (SSTL-2); all DDR SDRAM pins, besides pin MM_VREF) . . . . . .42 Characteristics (DDR2 (SSTL-18); all DDR SDRAM pins, besides pin MM_VREF) . . . . . .42 Characteristics (type I2 pins[1]) . . . . . . . . . . . .43 Characteristics (type H pins[1]) . . . . . . . . . . . . .44 Characteristics (type L pins[1]) . . . . . . . . . . . . .44 Characteristics (type F pins[1]) . . . . . . . . . . . . .45 Characteristics (type S pins[1][2]) . . . . . . . . . . .45 Characteristics (type T pins[1][2]) . . . . . . . . . . .46 Characteristics (type U pins[1]) . . . . . . . . . . . . .46 Characteristics (DDR SDRAM memory interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Characteristics (VDI interface) . . . . . . . . . . . . .48 Characteristics (VDO interface) . . . . . . . . . . . .48 Characteristics (digital audio input interface) . .50 Characteristics (digital audio output interface) .51 Characteristics (GPIO interface)[1] . . . . . . . . . .52 Characteristics (PCI-bus and XIO interface)[1] .53 Characteristics (host interface) . . . . . . . . . . . .54 Characteristics (reset interface[1][2], see Figure 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Characteristics (I2C-bus interface) . . . . . . . . . .56 Characteristics (JTAG interface) . . . . . . . . . . .56 Characteristics (external crystal HC-49U, pin XTAL_I) . . . . . . . . . . . . . . . . . . . . . . . . . . .57 A A A A R R D D D 24. Tables FT FT FT FT FT Software enabled video and multimedia entertainment platform Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors D D D D D R R R R R D R R R A FT R R FT FT A A R D D R A FT D R C O N FI C O M PA D EN NY TI A L A Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01.11C — 1 October 2009 F D D PNX9530_PNX9531_PNX9535_1 A FT FT A A R R D D D Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. D R FT FT A A R R D D D Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. FT FT FT FT Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Block diagram of PNX9530; PNX9531; PNX9535 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin configuration for BGA456 . . . . . . . . . . . . . . . .6 FPGI top level block diagram . . . . . . . . . . . . . . . .22 QVCP top level block diagram . . . . . . . . . . . . . . .24 MBS block diagram . . . . . . . . . . . . . . . . . . . . . . .25 Audio in block diagram . . . . . . . . . . . . . . . . . . . . .27 AO block diagram. . . . . . . . . . . . . . . . . . . . . . . . .28 GPIO module block diagram . . . . . . . . . . . . . . . .31 SSTL-2 and SSTL-18 test load conditions. . . . . .43 SSTL-2 and SSTL-18 receiver signal conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 VDI interface timing . . . . . . . . . . . . . . . . . . . . . . .48 VDO interface timing . . . . . . . . . . . . . . . . . . . . . .49 AI interface timing . . . . . . . . . . . . . . . . . . . . . . . .50 AO interface timing. . . . . . . . . . . . . . . . . . . . . . . .51 GPIO interface timing. . . . . . . . . . . . . . . . . . . . . .52 Type P cell test load conditions; see Table 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 PCI-bus and XIO interface timing. . . . . . . . . . . . .54 Host interface timing . . . . . . . . . . . . . . . . . . . . . .55 Reset interface timing . . . . . . . . . . . . . . . . . . . . .55 I2C-bus interface timing . . . . . . . . . . . . . . . . . . . .56 JTAG interface timing . . . . . . . . . . . . . . . . . . . . . .57 Package outline SOT795-1 (BGA456) . . . . . . . . .59 Soldering footprint SOT795-1 (BGA456) . . . . . . .60 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 A A A A R R D D D 25. Figures FT FT FT FT FT Software enabled video and multimedia entertainment platform Fig 1. A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors 71 of 72 D D D D D R R R R R D R R FT FT FT D D R O A C R All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 October 2009 Document identifier: PNX9530_PNX9531_PNX9535_1 D Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. FT N A PA D EN NY TI A L A A 41 47 57 57 57 58 58 59 61 61 61 61 62 63 66 66 66 67 67 67 67 67 67 67 68 70 71 72 R R FI F D D Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . External crystal . . . . . . . . . . . . . . . . . . . . . . . . With external crystal HC-49U. . . . . . . . . . . . . In oscillator mode . . . . . . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . © NXP B.V. 2009. A FT FT M R A A O D R R C R A D D 4 4.1 5 6 6.1 6.2 7 7.1 7.1.1 7.1.1.1 7.1.1.2 7.1.2 7.1.2.1 7.1.2.2 7.1.2.3 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3 7.3.2.4 7.3.2.5 7.3.3 7.3.4 8 8.1 8.2 9 10 D R FT FT A A R R D D D 3.2 11 12 13 13.1 13.2 14 14.1 15 16 16.1 16.2 16.3 16.4 17 18 19 20 21 21.1 21.2 21.3 21.4 21.5 22 23 24 25 26 FT FT FT FT 2.2 2.3 2.4 2.5 3 3.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Software enabled video and multimedia entertainment platform . . . . . . . . . . . . . . . . . . . 1 Dual video MPEG decoding and rendering . . . 2 Video quality . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Benefits from using PNX9530; PNX9531; PNX9535 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Typical applications with PNX9530; PNX9531; PNX9535 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional description . . . . . . . . . . . . . . . . . . 21 Digital video . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Video input . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FGPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Video output . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DVD-D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 QVCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital audio . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Audio input . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Audio output . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Peripheral interfaces . . . . . . . . . . . . . . . . . . . . 29 DDR SDRAM memory interface . . . . . . . . . . . 29 Multifunctional GPIO interface . . . . . . . . . . . . 29 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PCI-bus and XIO interface . . . . . . . . . . . . . . . 31 PCI-bus interface . . . . . . . . . . . . . . . . . . . . . . 31 USB-bus interface. . . . . . . . . . . . . . . . . . . . . . 33 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . 33 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 33 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . 33 Application design-in information . . . . . . . . . 34 Multiplexed GPIO functionality . . . . . . . . . . . . 34 Digital video input formats . . . . . . . . . . . . . . . 38 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 40 Thermal characteristics. . . . . . . . . . . . . . . . . . 41 A A A A R R D D D 26. Contents FT FT FT FT FT Software enabled video and multimedia entertainment platform 1 2 2.1 A A A A A PNX9530; PNX9531; PNX9535 NXP Semiconductors