SC18IS606PWJ

SC18IS606 2 I C-bus to SPI bridge Rev. 1.0 — 15 September 2021 1 Product data sheet General description 2 SC18IS606 is designed to serve as an interface between a standard I C-bus of a microcontroller and an SPI bus. This allows the microcontroller to communicate directly 2 2 with SPI devices through its I C-bus. SC18IS606 operates as an I C-bus targettransmitter or target-receiver and an SPI master. SC18IS606 controls all the SPI busspecific sequences, protocol, and timing. SC18IS606 has its own internal oscillator, and it supports three SPI chip select outputs that may be configured as GPIO when not used as SPI chip select. SC18IS606 is a functional replacement for SC18IS602B with the exception of: • • • • • • 2 Features and benefits • • • • • • • • • • • • 3 New pinout Three instead of four chip selects; no quasi bidirectional mode Lower operating supply voltage level (1.71 V vs 2.4 V) Data buffer increased to 1024 bytes vs 200 bytes Temperature range of -40 to +105 °C vs -40 to +85 °C Device is rotated 180 degrees in the tape pocket; pin 1 is now in Quadrant 1 2 I C-bus target interface operating up to 400 kHz SPI master operating up to 1.8 Mbit/s 1024-byte data buffer Up to three slave select outputs Up to three programmable I/O pins Operating supply voltage: 1.71 V to 3.6 V Low power mode Internal oscillator Active LOW interrupt output ESD protection exceeds 2000 V HBM per JESD22-A114 Latch-up testing is done to JEDEC Standard JESD78 that exceeds 100 mA Available in 16-pin TSSOP Applications 2 • Converting I C-bus to SPI • Adding additional SPI bus controllers to an existing system SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 4 Ordering information Table 1. Ordering information Type number SC18IS606PW Topside marking Package Name Description Version 18IS606 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package SC18IS606PW SC18IS606PWJ TSSOP16 REEL 13" Q1 *STANDARD [1] MARK SMD [1] 5 Packing method Minimum order quantity Temperature 2500 Tamb = -40 °C to +105 °C Find packing information at www.nxp.com/docs/en/packing/SOT403-1_118.pdf Block diagram VDD SCL SDA VSS I2C-BUS BUFFER CONTROL REGISTER SC18IS606 MOSI MISO SPICLK SS0 SS1 (1) SS2 SPI A0 A1 A2 RESET INT INTERRUPT CONTROL LOGIC INTERNAL OSCILLATOR aaa-039787 1. Unused slave select outputs may be used for GPIO. Figure 1. Block diagram of SC18IS606 SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 2 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 6 Pinning information 6.1 Pinning SDA 1 16 SS1/GPIO1 SCL 2 15 VREFP INT 3 14 MISO RESET 4 A2 5 A1 6 11 SPICLK A0 7 10 MOSI SS2/GPIO2 8 SC18IS606PW 13 VSS 12 VDD 9 SS0/GPIO0 aaa-039801 Figure 2. Pin configuration for TSSOP16 6.2 Pin description Table 3. Pin description 7 Symbol Pin Type Description SS0/GPIO0 9 I/O SPI slave select output 0 (active LOW) or GPIO 0 SS1/GPIO1 16 I/O SPI slave select output 1 (active LOW) or GPIO 1 RESET 4 I reset input (active LOW) VSS 13 - ground supply MISO 14 I Master In, Slave Out MOSI 10 O Master Out, Slave In SDA 1 I/O I C-bus data SCL 2 I I C-bus clock INT 3 O Interrupt output (active LOW). This pin is an open-drain pin which must be pulled HIGH with resistor and must not be held LOW at power on or reset SS2/GPIO2 8 I/O SPI slave select output 2 (active LOW) or GPIO 2 SPICLK 11 O SPI clock VDD 12 - supply voltage VREFP 15 - must connect to VDD A0 7 I address input 0 A1 6 I address input 1 A2 5 I address input 2 2 2 Functional description 2 2 SC18IS606 acts as a bridge between an I C-bus and an SPI interface. It allows an I Cbus controller device to communicate with any SPI-enabled device. SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 3 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 2 7.1 I C-bus interface 2 The I C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features: • Bidirectional data transfer between controllers and targets • Multi-controller bus (no central controller) • Arbitration between simultaneously transmitting controllers without corruption of serial data on the bus • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer 2 • The I C-bus may be used for test and diagnostic purposes 2 A typical I C-bus configuration is shown in Figure 3. (Refer to NXP Semiconductors 2 UM10204, "I C-bus specification and user manual", at www.nxp.com/documents/ user_manual/UM10204.pdf.) VDD RPU RPU SDA SCL I2C-bus I2C-BUS DEVICE SC18IS606 I2C-BUS DEVICE aaa-039802 2 Figure 3. I C-bus configuration 2 SC18IS606 device provides a byte-oriented I C-bus interface that supports data transfers 2 up to 400 kHz. When the I C-bus controller is reading data from SC18IS606, the device 2 will be a target-transmitter. SC18IS606 will be a target-receiver when the I C-bus 2 controller is sending data. At no time does SC18IS606 act as an I C-bus controller, however, it does have the ability to hold the SCL line LOW between bytes to complete its internal processes (e.g., clock stretching). 7.1.1 Addressing R/W target address 0 1 0 fixed 1 A2 A1 A0 X programmable 002aac446 Figure 4. Target address The first seven bits of the first byte sent after a START condition defines the target address of the device being accessed on the bus. The eighth bit determines the direction of the message. A ‘0’ in the least significant position of the first byte means that the controller will write information to a selected target. A ‘1’ in this position means that the controller will read information from the target. When an address is sent, each device in a system compares the first seven bits after the START condition with its address. If SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 4 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge they match, the device considers itself addressed by the controller as a target-receiver or target-transmitter, depending on the R/W bit. A target address of SC18IS606 is comprised of a fixed and a programmable part. The programmable part of the target address enables the maximum possible number of such 2 devices to be connected to the I C-bus. Since SC18IS606 has three programmable address bits (defined by the A2, A1, and A0 pins), it is possible to have eight of these devices on the same bus. The state of the A2, A1, and A0 pins are latched at reset. Changes made after reset will not alter the address. When SC18IS606 is busy after the address byte is transmitted, it will not acknowledge its address. 7.1.2 Write to data buffer All communications to or from SC18IS606 occur through the data buffer. The data buffer is 1024 bytes deep. A message begins with SC18IS606 address, followed by the Function ID. Depending upon the Function ID, zero to 1024 data bytes can follow. SC18IS606 will place the data received into a buffer and continue loading the buffer until a STOP condition is received. After the STOP condition is detected, further communications will not be acknowledged until the function designated by the Function ID has been completed. S TARGET ADDRESS W A FUNCTION ID A 0 TO 1024 BYTES A P aaa-040332 Figure 5. Write to data buffer 7.1.3 SPI read and write - Function ID 01h to 0x7h Data in the buffer will be sent to the SPI port if the Function ID is 01h to 0x7h. The Function ID contains the Slave Select (SS) to be used for the transmission on the SPI port. There are three Slave Selects that can be used, with each SS being selected by one of the bits in the Function ID. There is no restriction on the number or combination of Slave Selects that can be enabled for an SPI message. If more than one SSn pin is enabled at one time, the user should be aware of possible contention on the data outputs of the SPI slave devices. Table 4. Function ID 01h to 0x7h 7 6 5 4 3 2 1 0 0 0 0 0 0 SS2 SS1 SS0 2 The data on the SPI port will contain the same information as the I C-bus data, but without the slave address and Function ID. For example, if the message shown in 2 Figure 6 is transmitted on the I C-bus, the SPI bus will send the message shown in Figure 7. write to buffer S TARGET ADDRESS W A FUNCTION ID A DATA 1 A A DATA n A P 002aac448 2 Figure 6. I C-bus message SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 5 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge SPI data DATA 1 DATA n 002aac451 Figure 7. SPI message 2 SC18IS606 counts the number of data bytes sent to the I C-bus port and will automatically send this same number of bytes to the SPI bus. As the data is transmitted from the MOSI pin, it is also read from the MISO pin and saved in the data buffer. Therefore, the old data in the buffer is overwritten. The data in the buffer can then be read back. 2 If the data from the SPI bus needs to be returned to the I C-bus controller, the process must be completed by reading the data buffer. Section 8 gives an example of an SPI read. 7.1.4 Read from buffer A read from the data buffer requires no Function ID. The target address with the R/W bit 2 set to a ‘1’ will cause SC18IS606 to send the buffer contents to the I C-bus controller. The buffer contents are not modified during the read process. S TARGET ADDRESS R A DATA 1 A A DATA n NA P 002aac449 Figure 8. Read from buffer A typical write and read from an SPI EEPROM is shown in Section 8. After a read the interrupt line is cleared. 7.1.5 Configure SPI Interface - Function ID F0h The SPI hardware operating mode, data direction, and frequency can be changed by 2 sending a ‘Configure SPI Interface’ command to the I C-bus. S TARGET ADDRESS W A F0h A DATA A P 002aac450 Figure 9. Configure SPI Interface After SC18IS606 address is transmitted on the bus, the Configure SPI Interface Function ID (F0h) is sent followed by a byte which will define the SPI communications. The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit (CPOL) allows the user to set the clock polarity. Figure 18 and Figure 19 show the different settings of Clock Phase bit CPHA. Table 5. Configure SPI Interface (F0h) bit allocation SC18IS606 Product data sheet Bit 7 6 5 4 3 2 1 0 Symbol X X ORDER X MODE1 MODE0 F1 F0 Reset X X 0 X 0 0 0 0 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 6 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge Table 6. Configure SPI Interface (F0h) bit description Bit Symbol Description 7:6 - reserved 5 ORDER When logic 0, the MSB of the data word is transmitted first. If logic 1, the LSB of the data word is transmitted first. 4 - reserved 3:2 MODE1:MODE0 Mode selection 00 - SPICLK LOW when idle; data clocked in on leading edge (CPOL = 0, CPHA = 0) 01 - SPICLK LOW when idle; data clocked in on trailing edge (CPOL = 0, CPHA = 1) 10 - SPICLK HIGH when idle; data clocked in on trailing edge (CPOL = 1, CPHA = 0) 11 - SPICLK HIGH when idle; data clocked in on leading edge (CPOL = 1, CPHA = 1) 1:0 F1:F0 SPI clock rate 00 - 1875 kHz 01 - 455 kHz 10 - 115 kHz 11 - 58 kHz 7.1.6 Clear Interrupt - Function ID F1h An interrupt is generated by SC18IS606 after any SPI transmission has been completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear Interrupt’ command. It is not necessary to clear the interrupt; when polling the device, this function may be ignored. S TARGET ADDRESS W A F1h A P 002aac452 Figure 10. Clear Interrupt 7.1.7 Idle mode - Function ID F2h A low-power mode may be entered by sending the ‘Idle Mode’ command. S TARGET ADDRESS W A F2h A P 002aac453 Figure 11. Idle mode 2 The Idle mode will be exited when its I C-bus address is detected. 7.1.8 GPIO Write - Function ID F4h The state of the pins defined as GPIO may be changed using the Port Write function. SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 7 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge S TARGET ADDRESS W A F4h A DATA A P 002aac454 Figure 12. GPIO Write The data byte following the F4h command will determine the state of SS2, SS1, and SS0, if they are configured as GPIO. The Port Enable function will define if these pins are used as SPI Slave Selects or if they are GPIO. Table 7. GPIO Write (F0h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol X X X X X SS2 SS1 SS0 Reset X X X X X 0 0 0 7.1.9 GPIO Read - Function ID F5h The state of the pins defined as GPIO may be read into SC18IS606 data buffer using the GPIO Read function. S TARGET ADDRESS W A F5h A DATA A P 002aac455 Figure 13. GPIO Read Note that this function does not return the value of the GPIO. To receive the GPIO contents, a one-byte Read Buffer command would be required. The value of the Read Buffer command will return the following byte. Table 8. GPIO Read (F5h) bit allocation 7 6 5 4 3 2 1 0 X X X X X SS2 SS1 SS0 Data for pins not defined as GPIO are undefined. A GPIO Read is always performed to update the GPIO data in the buffer. The buffer is undefined after the GPIO data is read back from the buffer. Therefore, reading data from the GPIO always requires a two-message sequence (GPIO Read, followed by Read Buffer). 7.1.10 GPIO Enable - Function ID F6h At reset, the Slave Select pins (SS0, SS1 and SS2) are configured to be used as slave select outputs. If these pins are not required for the SPI functions, they can be used as GPIO after they are enabled as GPIO. Any combination of pins may be configured to function as GPIO or Slave Selects. After the GPIO Enable function is sent, the ports defined as GPIO will be configured as input-only. S TARGET ADDRESS W A F6h A DATA A P 002aac456 Figure 14. GPIO Enable SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 8 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge The data byte following the F6h command byte will determine which pins can be used as GPIO. A logic 1 will enable the pin as a GPIO, while a logic 0 will disable GPIO control. Table 9. GPIO Enable (F6h) bit allocation 7 6 5 4 3 2 1 0 X X X X X SS2 SS1 SS0 7.1.11 GPIO Configuration - Function ID F7h The pins defined as GPIO may be configured by software to one of three types on a pinby-pin basis. These are: push-pull, open-drain, and input-only. Two bits select the output type for each port pin. Table 10. GPIO Configuration (F7h) bit allocation 7 6 5 4 3 2 1 0 X X SS2.1 SS2.0 SS1.1 SS1.0 SS0.1 SS0.0 Table 11. GPIO Configuration (F7h) bit description Bit Symbol 7 X 6 X 5 SS2.1 4 SS2.0 3 SS1.1 2 SS1.0 1 SS0.1 0 SS0.0 Description SS2[1:0] = 00: input-only (high-impedance) SS2[1:0] = 01: push-pull SS2[1:0] = 10: input-only (high-impedance) SS2[1:0] = 11: open-drain SS1[1:0] = 00: input-only (high-impedance) SS1[1:0] = 01: push-pull SS1[1:0] = 10: input-only (high-impedance) SS1[1:0] = 11: open-drain SS0[1:0] = 00: input-only (high-impedance) SS0[1:0] = 01: push-pull SS0[1:0] = 10: input-only (high-impedance) SS0[1:0] = 11: open-drain The SSn pins defined as GPIO, for example SS0.0 and SS0.1, may be configured by software to one of three types. These are: push-pull, open-drain, and input-only. Two configuration bits in GPIO Configuration register for each pin select the type for each pin. A pin has Schmitt-triggered input that also has a glitch suppression circuit. 7.1.11.1 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a pin configured in this manner must have an external pull-up, typically a resistor tied to VDD. The open-drain pin configuration is shown in Figure 15. An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit. SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 9 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge Device uses a pseudo open-drain mode. The pin cannot be pulled up above VDD. The pins are not 5 V tolerant when VDD is grounded. GPIO pin pin latch data VSS input data glitch rejection 002aab883 Figure 15. Open-drain output configuration 7.1.11.2 Input-only configuration The input-only pin configuration is shown in Figure 16. It is a Schmitt-triggered input that also has a glitch suppression circuit. input data GPIO pin glitch rejection 002aab884 Figure 16. Input-only configuration 7.1.11.3 Push-pull output configuration The push-pull output configuration has the same pull-down structure as the open-drain but provides a continuous strong pull-up when the port latch contains a logic 1. The pushpull mode may be used when source current is needed from a pin output. The push-pull pin configuration is shown in Figure 17. A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit. open-drain enable output enable data output VDD strong pull-up strong pull-down pin configured as digital output driver VDD ESD PIN ESD VSS aaa-041527 Figure 17. Push-pull output configuration 7.1.12 Read Version: Function ID FEh This function commands the SC18IS606 to put version information into the read buffer. Once this command is issued, there will be a null terminated string place in the read buffer. The string contains the part number and a version string “SC18IS606 1.0.0” The total length is 16 bytes including a 00h null terminator. Values in the Readbuffer past the null terminator remain from a previous operation. The example above yields these SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 10 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge hex values in the first 16 locations in the read buffer: 0x53 0x43 0x31 0x38 0x49 0x53 0x36 0x30 0x36 0x20 0x31 0x2e 0x30 0x2e 0x30 0x00 7.2 SPI interface The SPI interface can support Mode 0 through Mode 3 of the SPI specification and can operate up to 1.8 Mbit/s. The SPI interface uses at least four pins: SPICLK, MOSI, MISO, and Slave Select (SSn). SSn are the slave select pins. In a typical configuration, an SPI master selects one SPI device as the current slave. There are actually three SSn pins (SS0, SS1 and SS2) to allow SC18IS606 to communicate with multiple SPI devices. SC18IS606 generates the SPICLK (SPI clock) signal in order to send and receive data. The SCLK, MOSI, and MISO are typically tied together between two or more SPI devices. Data flows from SC18IS606 (master) to slave on the MOSI pin (pin 10) and the data flows from slave to SC18IS606 (master) on the MISO pin (pin 14). 8 2 I C-bus to SPI communications example The following example describes a typical sequence of events required to read the contents of an SPI-based EEPROM. This example assumes that SC18IS606 is configured to respond to address 50h. A START condition is shown as ‘ST’, while a STOP condition is ‘SP’. The data is presented in hexadecimal format. This sequence was not included in the testing, as there is no EEPROM on the bridge board, but should work as written. A script for reading SPI Flash was tested, however. 1. The first message is used to configure the SPI port for mode and frequency. ST,50,F0,02,SP SPI frequency 115 kHz using Mode 0 2. An SPI EEPROM first requires that a Write Enable command be sent before data can be written. ST,50,04,06,SP EEPROM write enable using SS2, assuming the Write Enable is 06h 3. Clear the interrupt. This is not required if using a polling method rather than interrupts. ST,50,F1,SP Clear interrupt 4. Write the 8 data bytes. The first byte (Function ID) tells SC18IS606 which Slave Select output to use. This example uses SS2 (shown as 04h). The first byte sent to the EEPROM is normally 02h for the EEPROM write command. The next one or two bytes represent the subaddress in the EEPROM. In this example, a twobyte subaddress is used. Bytes 00 and 30 would cause the EEPROM to write to subaddress 0030h. The next eight bytes are the eight data bytes that will be written to subaddresses 0030h through 0037h. ST,50,04,02,00,30,01,02,03,04,05,06,07,08,SP Write 8 bytes using SS2 5. When an interrupt occurs, do a Clear Interrupt or wait until SC18IS606 responds to its 2 I C-bus address. ST,50,F1,SP Clear interrupt 6. Read the 8 bytes from the EEPROM. Note that we are writing a command, even though we are going to perform a read from the SPI port. The Function ID is again 04h, indicating that we are going to use SS2. The EEPROM requires that you send a 03h for a read, followed by the subaddress you would like to read. We are going to SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 11 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge read back the same data previously written, so this means that the subaddress should be 0030h. We would like to read back 8 bytes so we can send eight bytes of FFh to tell SC18IS606 to send eight more bytes on MOSI. While it is sending these eight data bytes, it is also reading the MISO pin and saving the data in the buffer. ST,50,04,03,00,30,FF,FF,FF,FF,FF,FF,FF,FF,SP Read 8 bytes using SS2 7. The interrupt can be cleared, if needed. ST,50,F1,SP Clear interrupt 8. Read back the data buffer. Note that we will actually need to read back 11 data bytes since the first three bytes sent on the SPI port were the read code (03h) and the two subaddress bytes. ST,50,00,00,00,01,02,03,04,05,06,07,08,SP Read the data buffer 2 You can see that on the I C-bus the first four bytes do not contain the data from the SPI bus. The first byte is SC18IS606 address, followed by three dummy data bytes. These dummy data bytes correspond to the three bytes sent to the EEPROM before it actually places data on the bus (command 03h, subaddress 0030h). 9 Limiting values Table 12. Limiting values [1][2] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Tamb(bias) bias ambient temperature Tstg storage temperature VI Conditions operating input voltage 5 V tolerant I/O pins; VDD ≥ 1.71 V [3] 3 V tolerant I/O all pins [5] [4] Min Max Unit -0.5 +4.6 V -55 +150 °C -65 +150 °C -0.5 +5.4 V -0.5 +3.6 V IOH(I/O) HIGH-level output current per input/output pin - 8 mA IOL(I/O) LOW-level output current per input/output pin - 20 mA II/O(tot)(max) maximum total I/O current - 120 mA - 1.5 W Ptot/pack [1] [2] [3] [4] [5] [6] total power dissipation per package [6] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. Parameters are valid over the operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Applies to all 5 V tolerant I/O pins except the 3 V tolerant pin MISO Including the voltage on outputs in 3-state mode. VDD present or not present. Based on package heat transfer, not device power consumption. SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 12 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 10 Static characteristics Table 13. Static characteristics VDD = 1.71 V to 3.6 V; Tamb = -40 °C to +105 °C, unless otherwise specified Symbol Parameter Unit VDD supply voltage 3.6 V IDD(oper) operating supply current VDD = 3.3 V - 2.1 4.0 mA IDD(idle) Idle mode supply current VDD = 3.3 V - 1.3 3.4 mA IDD(tpd) total Power-down mode supply current VDD = 3.3 V - 6 75 µA Vth(HL) HIGH-LOW threshold voltage Schmitt trigger input 0.22VDD 0.4VDD - V Vth(LH) LOW-HIGH threshold voltage Schmitt trigger input - 0.6VDD 0.7VDD V Vhys hysteresis voltage - 0.2VDD - V VOL LOW-level output voltage input capacitance at gate IIL LOW-level input current all pins IOL = 4 mA; 2.5 V ≤ VDD ≤ 3.6 V - 0.5 V IOL = 3 mA; 1.71 V ≤ VDD ≤ 2.5 V - 0.5 V - V - V all pins IOH = 4 mA; 2.5 V ≤ VDD ≤ 3.6 V VDD - 0.4 IOH = 3 mA; 1.71 V ≤ VDD ≤ 2.5 V VDD - 0.5 [2] logical 0; VI = 0.4 V ILI input leakage current all ports; VI = VIL or VIH ITHL HIGH-LOW transition current all ports; logical 1-to-0; VI = 2.0 V at VDD = 3.6 V Ipu pull-up current VI = 0 V; [3] - - - 15 pF - - -80 µA - - ±10 µA -30 - -450 µA [4] µA 2.0 V ≤ VDD ≤ 3.6 V 10 50 90 µA 1.71 V ≤ VDD ≤ 2.0 V 7 50 85 µA 0 0 0 µA VDD < VI < 5 V [1] [2] [3] [4] Typ 1.71 HIGH-level output voltage Cig Min [1] Max VOH Conditions Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. Pin capacitance is characterized but not tested. Measured with pins in high-impedance mode. Pull-up current measured across the weak pull-up resistor SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 13 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 11 Dynamic characteristics Table 14. Dynamic characteristics VDD = 1.71 V to 3.6 V; Tamb = -40 °C to +105 °C, unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit 20 ns Glitch filter tgr glitch rejection time RESET pin - - tsa signal acceptance time RESET pin 125 - any pin except RESET 50 - - ns ns SPI master interface fSPI SPI operating frequency 1.875 MHz - - 1.875 MHz TSPICYC SPI cycle time 1.875 MHz 533 - - ns tDS data set-up time 10 - - ns tDH data hold time 7 - - ns tV(Q) data output valid time - - 2 ns TSPICYC tSPIF SPICLK (CPOL = 0) (output) tSPIF SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPICLKH tSPICLKL tSPICLKL tSPICLKH tSPIR tSPIR tSPIDH MSB/LSB in tSPIDV LSB/MSB in tSPIOH tSPIDV tSPIR tSPIF MOSI (output) master MSB/LSB out master LSB/MSB out 002aac457 Figure 18. SPI master timing (CPHA = 0) SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 14 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge TSPICYC tSPIF tSPICLKL SPICLK (CPOL = 0) (output) tSPIF tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIR tSPICLKH tSPICLKL tSPIR tSPIDH MSB/LSB in tSPIDV LSB/MSB in tSPIOH tSPIDV tSPIF MOSI (output) tSPIDV tSPIR master MSB/LSB out master LSB/MSB out 002aac458 Figure 19. SPI master timing (CPHA = 1) SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 15 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 12 Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Figure 20. Package outline SOT403-1 (TSSOP16) SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 16 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 13 PCB layout Footprint information for reflow soldering of TSSOP16 package SOT403-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450 sot403-1_fr Figure 21. SOT403-1 (TSSOP16) footprint information for reflow soldering SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 17 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge Figure 22. SOT403-1 (TSSOP16) solder mask opening pattern SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 18 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge Figure 23. SOT403-1 (TSSOP16) I/O pads and solderable area SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 19 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge Figure 24. SOT403-1 (TSSOP16) Solder paste stencil SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 20 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 14 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 21 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 15 and Table 16 Table 15. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 16. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25. SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 22 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15 Abbreviations Table 17. Abbreviations Acronym Description CDM Charged Device Model CPU Central Processing Unit EEPROM Electrically Erasable Programmable Read-Only Memory ESD ElectroStatic Discharge GPIO General Purpose Input/Output HBM Human Body Model I/O Input/Output 2 I C-bus Inter-Integrated Circuit bus LSB Least Significant Bit MM Machine Model MSB Most Significant Bit SPI Serial Peripheral Interface 16 Revision history Table 18. Revision history Document ID Release date Data sheet status Change notice Supersedes SC18IS606 v.1.0 20210915 Product data sheet - - SC18IS606 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 23 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge 17 Legal information 17.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 17.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without SC18IS606 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 24 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP SC18IS606 Product data sheet Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2 I C-bus — logo is a trademark of NXP B.V. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 25 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Ordering information ..........................................2 Ordering options ................................................2 Pin description ...................................................3 Function ID 01h to 0x7h ................................... 5 Configure SPI Interface (F0h) bit allocation .......6 Configure SPI Interface (F0h) bit description ......................................................... 7 GPIO Write (F0h) bit allocation ......................... 8 GPIO Read (F5h) bit allocation ......................... 8 GPIO Enable (F6h) bit allocation ...................... 9 Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. GPIO Configuration (F7h) bit allocation .............9 GPIO Configuration (F7h) bit description .......... 9 Limiting values ................................................ 12 Static characteristics ....................................... 13 Dynamic characteristics .................................. 14 SnPb eutectic process (from J-STD-020D) ..... 22 Lead-free process (from J-STD-020D) ............ 22 Abbreviations ...................................................23 Revision history ...............................................23 Fig. 16. Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Input-only configuration ................................... 10 Push-pull output configuration .........................10 SPI master timing (CPHA = 0) ........................ 14 SPI master timing (CPHA = 1) ........................ 15 Package outline SOT403-1 (TSSOP16) ..........16 SOT403-1 (TSSOP16) footprint information for reflow soldering ..........................................17 SOT403-1 (TSSOP16) solder mask opening pattern ............................................... 18 SOT403-1 (TSSOP16) I/O pads and solderable area ............................................... 19 SOT403-1 (TSSOP16) Solder paste stencil .... 20 Temperature profiles for large and small components ..................................................... 23 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Block diagram of SC18IS606 ............................ 2 Pin configuration for TSSOP16 ......................... 3 I2C-bus configuration ........................................ 4 Target address .................................................. 4 Write to data buffer ........................................... 5 I2C-bus message .............................................. 5 SPI message .....................................................6 Read from buffer ............................................... 6 Configure SPI Interface .....................................6 Clear Interrupt ................................................... 7 Idle mode .......................................................... 7 GPIO Write ........................................................8 GPIO Read ........................................................8 GPIO Enable ..................................................... 8 Open-drain output configuration ......................10 SC18IS606 Product data sheet Fig. 22. Fig. 23. Fig. 24. Fig. 25. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 15 September 2021 © NXP B.V. 2021. All rights reserved. 26 / 27 SC18IS606 NXP Semiconductors 2 I C-bus to SPI bridge Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................1 Ordering information .......................................... 2 Ordering options ................................................ 2 Block diagram ..................................................... 2 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 3 Functional description ........................................3 I2C-bus interface ............................................... 4 Addressing ......................................................... 4 Write to data buffer ............................................5 SPI read and write - Function ID 01h to 0x7h ................................................................... 5 7.1.4 Read from buffer ............................................... 6 7.1.5 Configure SPI Interface - Function ID F0h .........6 7.1.6 Clear Interrupt - Function ID F1h .......................7 7.1.7 Idle mode - Function ID F2h ..............................7 7.1.8 GPIO Write - Function ID F4h ........................... 7 7.1.9 GPIO Read - Function ID F5h ........................... 8 7.1.10 GPIO Enable - Function ID F6h ........................ 8 7.1.11 GPIO Configuration - Function ID F7h ...............9 7.1.11.1 Open-drain output configuration ........................ 9 7.1.11.2 Input-only configuration ................................... 10 7.1.11.3 Push-pull output configuration ......................... 10 7.1.12 Read Version: Function ID FEh ....................... 10 7.2 SPI interface .................................................... 11 8 I2C-bus to SPI communications example ....... 11 9 Limiting values .................................................. 12 10 Static characteristics ........................................ 13 11 Dynamic characteristics ...................................14 12 Package outline .................................................16 13 PCB layout .........................................................17 14 Soldering of SMD packages .............................21 14.1 Introduction to soldering ............................. 14.2 Wave and reflow soldering ......................... 14.3 Wave soldering ........................................... 14.4 Reflow soldering ......................................... 15 Abbreviations .................................................... 23 16 Revision history ................................................ 23 17 Legal information .............................................. 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 September 2021 Document identifier: SC18IS606