Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5602D
Rev. 6, 01/2013
MPC5602D
100 LQFP
14 mm x 14 mm
64 LQFP
10 mm x 10 mm
MPC5602D Microcontroller
Data Sheet
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Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with the Power Architecture®
embedded category
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant
code size footprint reduction.
Up to 256 KB on-chip Code Flash supported with
Flash controller and ECC
64 KB on-chip Data Flash with ECC
Up to 16 KB on-chip SRAM with ECC
Interrupt controller (INTC) with multiple interrupt
vectors, including 20 external interrupt sources and
18 external interrupt/wakeup sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, Flash, or SRAM from multiple bus
masters
Boot assist module (BAM) supports internal Flash
programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
Up to 33 channel 12-bit analog-to-digital converter
(ADC)
2 serial peripheral interface (DSPI) modules
3 serial communication interface (LINFlex) modules
— LINFlex 1 and 2: Master capable
— LINFlex 0: Master capable and slave capable;
connected to eDMA
1 enhanced full CAN (FlexCAN) module with
configurable buffers
•
•
•
•
•
•
•
Up to 79 configurable general purpose pins
supporting input and output operations (package
dependent)
Real Time Counter (RTC) with clock source from
128 kHz or 16 MHz internal RC oscillator
supporting autonomous wakeup with 1 ms
resolution with max timeout of 2 seconds
Up to 4 periodic interrupt timers (PIT) with 32-bit
counter resolution
1 System Timer Module (STM)
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class 1 standard
Device/board boundary Scan testing supported with
per Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2009–2013. All rights reserved.
Table of Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Pad configuration during reset phases . . . . . . . . . . . . . .9
3.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .21
4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .22
4.3.2 NVUSRO[OSCILLATOR_MARGIN] field
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.3 NVUSRO[WATCHDOG_EN] field description . .22
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .22
4.5 Recommended operating conditions . . . . . . . . . . . . . .23
4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . .26
4.6.1 Package thermal characteristics . . . . . . . . . . . .26
4.6.2 Power considerations . . . . . . . . . . . . . . . . . . . .26
4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .27
4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.7.2 I/O input DC characteristics . . . . . . . . . . . . . . . .27
4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .28
4.7.4 Output pin transition times . . . . . . . . . . . . . . . . .31
4.7.5 I/O pad current specification . . . . . . . . . . . . . . .31
4.8 RESET electrical characteristics. . . . . . . . . . . . . . . . . .35
4.9 Power management electrical characteristics. . . . . . . .37
4.9.1 Voltage regulator electrical characteristics . . . .37
4.9.2 Low voltage detector electrical characteristics .40
5
6
7
4.10 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.11 Flash memory electrical characteristics. . . . . . . . . . . . 42
4.11.1 Program/Erase characteristics . . . . . . . . . . . . . 42
4.11.2 Flash power supply DC characteristics . . . . . . 44
4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 45
4.12 Electromagnetic compatibility (EMC) characteristics. . 45
4.12.1 Designing hardened software to avoid
noise problems . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 46
4.12.3 Absolute maximum ratings (electrical sensitivity)46
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 51
4.15 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.16 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 54
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.17.2 Input impedance and ADC accuracy . . . . . . . . 55
4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 60
4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 62
4.18.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . 63
4.18.3 JTAG characteristics . . . . . . . . . . . . . . . . . . . . 70
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 70
5.1.1 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.2 64 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
MPC5602D Microcontroller Data Sheet, Rev. 6
2
Freescale Semiconductor
Introduction
1
Introduction
1.1
Document overview
This document describes the device features and highlights the important electrical and physical characteristics.
1.2
Description
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the
development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control
and seat control applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture
technology and designed specifically for embedded applications.
The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power
Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit), providing
improved code density. It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with the user’s implementations.
The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access
memory (SRAM) and internal flash memory.
Table 1. MPC5602D device comparison
Device
Feature
MPC5601DxLH
MPC5601DxLL
CPU
MPC5602DxLH
MPC5602DxLL
e200z0h
Execution speed
Static – up to 48 MHz
Code flash memory
128 KB
256 KB
Data flash memory
64 KB (4 × 16 KB)
SRAM
12 KB
16 KB
eDMA
16 ch
ADC (12-bit)
16 ch
33 ch
CTU
16 ch
33 ch
16 ch
Total timer
eMIOS
I/O1
14 ch, 16-bit
28 ch, 16-bit
14 ch, 16-bit
28 ch, 16-bit
2 ch
5 ch
2 ch
5 ch
—
9 ch
—
9 ch
• Type G4
7 ch
7 ch
7 ch
7 ch
• Type H5
4 ch
7 ch
4 ch
7 ch
45
79
• Type X2
• Type
Y3
SCI (LINFlex)
3
SPI (DSPI)
2
CAN (FlexCAN)
1
GPIO6
45
79
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
3
Block diagram
Table 1. MPC5602D device comparison (continued)
Device
Feature
MPC5601DxLH
MPC5601DxLL
Debug
Package
1
2
3
4
5
6
2
MPC5602DxLH
MPC5602DxLL
64 LQFP
100 LQFP
JTAG
64 LQFP
100 LQFP
Refer to eMIOS chapter of device reference manual for information on the channel configuration and functions.
Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC
Type Y = OPWMT + OPWMB + SAIC + SAOC
Type G = MCB + IPWM + IPM + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC
Type H = IPWM + IPM + DAOC + OPWMT + OPWMB + SAIC + SAOC
I/O count based on multiplexing with peripherals
Block diagram
Figure 1 shows a top-level block diagram of the MPC5602D device series.
MPC5602D Microcontroller Data Sheet, Rev. 6
4
Freescale Semiconductor
Block diagram
SRAM
16 KB
JTAG
Code Flash
256 KB
Data Flash
64 KB
64-bit 3 x 3 Crossbar Switch
JTAG Port
Instructions
(Master)
Nexus 1
e200z0h
Data
NMI
(Master)
SIUL
Voltage
Regulator
Interrupt requests
from peripheral
blocks
NMI
Flash
Controller
(Slave)
(Slave)
(Slave)
(Master)
INTC
Clocks
SRAM
Controller
eDMA
CMU
FMPLL
RTC
STM
SWT
MC_RGM MC_CGM
PIT
ECSM
MC_ME
MC_PCU
BAM
SSCM
Peripheral Bridge
Interrupt
Request
SIUL
Reset Control
33 ch.
ADC
CTU
1x
eMIOS
3x
LINFlex
2x
DSPI
1x
FlexCAN
WKPU
External
Interrupt
Request
IMUX
Interrupt
Request
GPIO &
Pad Control
I/O
...
...
...
...
Legend:
ADC
BAM
CMU
CTU
DSPI
ECSM
eDMA
eMIOS
Flash
FlexCAN
FMPLL
IMUX
INTC
JTAG
LINFlex
Analog-to-Digital Converter
Boot Assist Module
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Error Correction Status Module
Enhanced Direct Memory Access
Enhanced Modular Input Output System
Flash memory
Controller Area Network (FlexCAN)
Frequency-Modulated Phase-Locked Loop
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
MC_CGM
MC_ME
MC_PCU
MC_RGM
NMI
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
XBAR
Clock Generation Module
Mode Entry Module
Power Control Unit
Reset Generation Module
Non-Maskable Interrupt
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
Crossbar switch
Figure 1. MPC5602D series block diagram
Table 2 summarizes the functions of all blocks present in the MPC5602D series of microcontrollers. Please note that the
presence and number of blocks varies by device and package.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
5
Block diagram
Table 2. MPC5602D series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to-digital converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
phase-locked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller (JTAGC)
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-maskable interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
MPC5602D Microcontroller Data Sheet, Rev. 6
6
Freescale Semiconductor
Package pinouts and signal descriptions
Table 2. MPC5602D series block summary (continued)
Block
Function
Real-time counter (RTC)
Provides a free-running counter and interrupt generation capability that can be
used for timekeeping applications
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR (Automotive
Open System Architecture) and operating system tasks
Software watchdog timer (SWT)
Provides protection from runaway code
Wakeup unit (WKPU)
Supports up to 18 external sources that can generate interrupts or wakeup
events, of which 1 can cause non-maskable interrupt requests or wakeup events.
3
Package pinouts and signal descriptions
3.1
Package pinouts
The available LQFP pinouts are provided in the following figures. For pin signal descriptions, please refer to Table 5.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
7
Package pinouts and signal descriptions
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PE[12]
Figure 2 shows the MPC5602D in the 100 LQFP package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
Figure 2. 100 LQFP pin configuration (top view)
MPC5602D Microcontroller Data Sheet, Rev. 6
8
Freescale Semiconductor
Package pinouts and signal descriptions
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB[2]
PC[8]
PC[4]
PC[5]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
Figure 3 shows the MPC5602D in the 64 LQFP package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[3]
PB[15]
PB[14]
PB[13]
PB[12]
PB[11]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PB[4]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB[3]
PC[9]
PA[2]
PA[1]
PA[0]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[10]
PB[0]
PB[1]
PC[6]
Figure 3. 64 LQFP pin configuration (top view)
3.2
Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are forced to tristate with the following exceptions:
•
•
•
•
•
•
3.3
PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.
PA[8] (ABS[0]) is pull-up.
RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
JTAG pads (TCK, TMS and TDI) are pull-up while TDO remains tristate.
Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).
Main oscillator pads (EXTAL, XTAL) are tristate.
Voltage supply pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
9
Package pinouts and signal descriptions
Table 3. Voltage supply pin descriptions
Pin number
Port pin
Function
64 LQFP
100 LQFP
7, 28, 34, 56
15, 37, 52, 70, 84
6, 8, 26, 33, 55
14, 16, 35, 51, 69, 83
VDD_LV 1.2V decoupling pins. Decoupling capacitor must be
connected between these pins and the nearest VSS_LV pin.1
11, 23, 57
19, 32, 85
VSS_LV 1.2V decoupling pins. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV pin.1
10, 24, 58
18, 33, 86
12
20
VDD_HV Digital supply voltage
VSS_HV Digital ground
VDD_BV Internal regulator supply voltage
1
3.4
A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable
voltage (see the recommended operating conditions in the device datasheet for details).
Pad types
In the device the following types of pads are available for system pins and functional port pins:
S = Slow1
M = Medium1 2
F = Fast1 2
I = Input only with analog feature1
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
3.5
System pins
The system pins are listed in Table 4.
Table 4. System pin descriptions
Port pin
I/O
RESET
Pad type
direction
configuration
Pin number
64 LQFP 100 LQFP
RESET Bidirectional reset with Schmitt-Trigger
characteristics and noise filter.
I/O
M
Input, weak
pull-up only
after PHASE2
9
17
EXTAL Analog output of the oscillator amplifier circuit,
when the oscillator is not in bypass mode.
Analog input for the clock generator when the
oscillator is in bypass mode.1
I/O
X
Tristate
27
36
I
X
Tristate
25
34
XTAL
1
Function
Analog input of the oscillator amplifier circuit.
Needs to be grounded if oscillator is used in
bypass mode.1
Refer to the relevant section of the device datasheet.
1. See the I/O pad electrical characteristics in the device datasheet for details.
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see the
PCR[SRC] description in the device reference manual).
MPC5602D Microcontroller Data Sheet, Rev. 6
10
Freescale Semiconductor
Package pinouts and signal descriptions
3.6
Functional ports
The functional port pins are listed in Table 5.
Port pin
PCR
Alternate
function1
Function
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions
Pad
I/O
direction2 type
Pin number
64 LQFP 100 LQFP
Port A
PA[0]
PCR[0]
AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKPU[19]3
SIUL
eMIOS_0
CGL
eMIOS_0
WKPU
I/O
I/O
O
I/O
I
M
Tristate
5
12
PA[1]
PCR[1]
AF0
AF1
AF2
AF3
—
—
GPIO[1]
E0UC[1]
—
—
NMI4
WKPU[2]3
SIUL
eMIOS_0
—
—
WKPU
WKPU
I/O
I/O
—
—
I
I
S
Tristate
4
7
PA[2]
PCR[2]
AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
MA[2]
WKPU[3]3
SIUL
eMIOS_0
—
ADC
WKPU
I/O
I/O
—
O
I
S
Tristate
3
5
PA[3]
PCR[3]
AF0
AF1
AF2
AF3
—
—
GPIO[3]
E0UC[3]
—
CS4_0
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
—
DSPI_0
SIUL
ADC
I/O
I/O
—
I/O
I
I
S
Tristate
43
68
PA[4]
PCR[4]
AF0
AF1
AF2
AF3
—
GPIO[4]
E0UC[4]
—
CS0_1
WKPU[9]3
SIUL
eMIOS_0
—
DSPI_1
WKPU
I/O
I/O
—
I/O
I
S
Tristate
20
29
PA[5]
PCR[5]
AF0
AF1
AF2
AF3
GPIO[5]
E0UC[5]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M
Tristate
51
79
PA[6]
PCR[6]
AF0
AF1
AF2
AF3
—
GPIO[6]
E0UC[6]
—
CS1_1
EIRQ[1]
SIUL
eMIOS_0
—
DSPI_1
SIUL
I/O
I/O
—
I/O
I
S
Tristate
52
80
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
11
Package pinouts and signal descriptions
Port pin
PCR
Alternate
function1
Function
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
Pin number
64 LQFP 100 LQFP
PA[7]
PCR[7]
AF0
AF1
AF2
AF3
—
—
GPIO[7]
E0UC[7]
—
—
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
—
—
SIUL
ADC
I/O
I/O
—
—
I
I
S
Tristate
44
71
PA[8]
PCR[8]
AF0
AF1
AF2
AF3
—
N/A5
GPIO[8]
E0UC[8]
E0UC[14]
—
EIRQ[3]
ABS[0]
SIUL
eMIOS_0
eMIOS_0
—
SIUL
BAM
I/O
I/O
—
—
I
I
S
Input, weak
pull-up
45
72
PA[9]
PCR[9]
AF0
AF1
AF2
AF3
N/A5
GPIO[9]
E0UC[9]
—
CS2_1
FAB
SIUL
eMIOS_0
—
DSPI_1
BAM
I/O
I/O
—
I/O
I
S
Pull-down
46
73
PA[10]
PCR[10]
AF0
AF1
AF2
AF3
—
GPIO[10]
E0UC[10]
—
LIN2TX
ADC1_S[2]
SIUL
eMIOS_0
—
LINFlex_2
ADC
I/O
I/O
—
O
I
S
Tristate
47
74
PA[11]
PCR[11]
AF0
AF1
AF2
AF3
—
—
—
GPIO[11]
E0UC[11]
—
—
EIRQ[16]
ADC1_S[3]
LIN2RX
SIUL
eMIOS_0
—
—
SIUL
ADC
LINFlex_2
I/O
I/O
—
—
I
I
I
S
Tristate
48
75
PA[12]
PCR[12]
AF0
AF1
AF2
AF3
—
—
GPIO[12]
—
—
—
EIRQ[17]
SIN_0
SIUL
—
—
—
SIUL
DSPI_0
I/O
—
—
—
I
I
S
Tristate
22
31
PA[13]
PCR[13]
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
—
CS3_1
SIUL
DSPI_0
—
DSPI_1
I/O
O
—
I/O
M
Tristate
21
30
PA[14]
PCR[14]
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
M
Tristate
19
28
MPC5602D Microcontroller Data Sheet, Rev. 6
12
Freescale Semiconductor
Package pinouts and signal descriptions
Port pin
PA[15]
PCR
PCR[15]
Alternate
function1
Function
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
E0UC[1]
WKPU[10]3
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKPU
Pin number
64 LQFP 100 LQFP
I/O
I/O
I/O
I/O
I
M
Tristate
18
27
Port B
PB[0]
PCR[16]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
—
LIN2TX
SIUL
FlexCAN_0
—
LINFlex_2
I/O
O
—
O
M
Tristate
14
23
PB[1]
PCR[17]
AF0
AF1
AF2
AF3
—
—
GPIO[17]
—
—
LIN0RX
WKPU[4]3
CAN0RX
SIUL
—
—
LINFlex_0
WKPU
FlexCAN_0
I/O
—
—
I
I
I
S
Tristate
15
24
PB[2]
PCR[18]
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
—
—
SIUL
LINFlex_0
—
—
I/O
O
—
—
M
Tristate
64
100
PB[3]
PCR[19]
AF0
AF1
AF2
AF3
—
—
GPIO[19]
—
—
—
WKPU[11]3
LIN0RX
SIUL
—
—
—
WKPU
LINFlex_0
I/O
—
—
—
I
I
S
Tristate
1
1
PB[4]
PCR[20]
AF0
AF1
AF2
AF3
—
GPIO[20]
—
—
—
ADC1_P[0]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
32
50
PB[5]
PCR[21]
AF0
AF1
AF2
AF3
—
GPIO[21]
—
—
—
ADC1_P[1]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
35
53
PB[6]
PCR[22]
AF0
AF1
AF2
AF3
—
GPIO[22]
—
—
—
ADC1_P[2]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
36
54
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
13
Package pinouts and signal descriptions
Port pin
PCR
Alternate
function1
Function
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
Pin number
64 LQFP 100 LQFP
PB[7]
PCR[23]
AF0
AF1
AF2
AF3
—
GPIO[23]
—
—
—
ADC1_P[3]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
37
55
PB[8]
PCR[24]
AF0
AF1
AF2
AF3
—
—
GPIO[24]
—
—
—
ADC1_S[4]
WKPU[25]3
SIUL
—
—
—
ADC
WKPU
I
—
—
—
I
I
I
Tristate
30
39
PB[9]
PCR[25]
AF0
AF1
AF2
AF3
—
—
GPIO[25]
—
—
—
ADC1_S[5]
WKPU[26]3
SIUL
—
—
—
ADC
WKPU
I
—
—
—
I
I
I
Tristate
29
38
PB[10]
PCR[26]
AF0
AF1
AF2
AF3
—
—
GPIO[26]
—
—
—
ADC1_S[6]
WKPU[8]3
SIUL
—
—
—
ADC
WKPU
I/O
—
—
—
I
I
J
Tristate
31
40
PB[11]
PCR[27]
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ADC1_S[12]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
I/O
I
J
Tristate
38
59
PB[12]
PCR[28]
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC1_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
39
61
PB[13]
PCR[29]
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC1_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
40
63
PB[14]
PCR[30]
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC1_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
41
65
MPC5602D Microcontroller Data Sheet, Rev. 6
14
Freescale Semiconductor
Package pinouts and signal descriptions
Port pin
PB[15]
PCR
PCR[31]
Alternate
function1
Function
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC1_X[3]
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
SIUL
eMIOS_0
—
DSPI_0
ADC
Pin number
64 LQFP 100 LQFP
I/O
I/O
—
O
I
J
Tristate
42
67
Port C
PC[0]6
PCR[32]
AF0
AF1
AF2
AF3
GPIO[32]
—
TDI
—
SIUL
—
JTAGC
—
I/O
—
I
—
M
Input, weak
pull-up
59
87
PC[1]6
PCR[33]
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
—
F
Tristate
54
82
PC[2]
PCR[34]
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
—
—
EIRQ[5]
SIUL
DSPI_1
—
—
SIUL
I/O
I/O
—
—
I
M
Tristate
50
78
PC[3]
PCR[35]
AF0
AF1
AF2
AF3
—
GPIO[35]
CS0_1
MA[0]
—
EIRQ[6]
SIUL
DSPI_1
ADC
—
SIUL
I/O
I/O
O
—
I
S
Tristate
49
77
PC[4]
PCR[36]
AF0
AF1
AF2
AF3
—
—
GPIO[36]
—
—
—
SIN_1
EIRQ[18]
SIUL
—
—
—
DSPI_1
SIUL
I/O
—
—
—
I
I
M
Tristate
62
92
PC[5]
PCR[37]
AF0
AF1
AF2
AF3
—
GPIO[37]
SOUT_1
—
—
EIRQ[7]
SIUL
DSPI_1
—
—
SIUL
I/O
O
—
—
I
M
Tristate
61
91
PC[6]
PCR[38]
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
—
—
SIUL
LINFlex_1
—
—
I/O
O
—
—
S
Tristate
16
25
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
15
Package pinouts and signal descriptions
Port pin
PCR
Alternate
function1
Function
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
Pin number
64 LQFP 100 LQFP
PC[7]
PCR[39]
AF0
AF1
AF2
AF3
—
—
GPIO[39]
—
—
—
LIN1RX
WKPU[12]3
SIUL
—
—
—
LINFlex_1
WKPU
I/O
—
—
—
I
I
S
Tristate
17
26
PC[8]
PCR[40]
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
—
SIUL
LINFlex_2
eMIOS_0
—
I/O
O
I/O
—
S
Tristate
63
99
PC[9]
PCR[41]
AF0
AF1
AF2
AF3
—
—
GPIO[41]
—
E0UC[7]
—
LIN2RX
WKPU[13]3
SIUL
—
eMIOS_0
—
LINFlex_2
WKPU
I/O
—
I/O
—
I
I
S
Tristate
2
2
PC[10]
PCR[42]
AF0
AF1
AF2
AF3
GPIO[42]
—
—
MA[1]
SIUL
—
—
ADC
I/O
—
—
O
M
Tristate
13
22
PC[11]
PCR[43]
AF0
AF1
AF2
AF3
—
GPIO[43]
—
—
MA[2]
WKPU[5]3
SIUL
—
—
ADC
WKPU
I/O
—
—
O
I
S
Tristate
—
21
PC[12]
PCR[44]
AF0
AF1
AF2
AF3
—
GPIO[44]
E0UC[12]
—
—
EIRQ[19]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
M
Tristate
—
97
PC[13]
PCR[45]
AF0
AF1
AF2
AF3
GPIO[45]
E0UC[13]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
S
Tristate
—
98
PC[14]
PCR[46]
AF0
AF1
AF2
AF3
—
GPIO[46]
E0UC[14]
—
—
EIRQ[8]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
S
Tristate
—
3
PC[15]
PCR[47]
AF0
AF1
AF2
AF3
—
GPIO[47]
E0UC[15]
—
—
EIRQ[20]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
M
Tristate
—
4
MPC5602D Microcontroller Data Sheet, Rev. 6
16
Freescale Semiconductor
Package pinouts and signal descriptions
Port pin
PCR
Alternate
function1
Function
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
Pin number
64 LQFP 100 LQFP
Port D
PD[0]
PCR[48]
AF0
AF1
AF2
AF3
—
—
GPIO[48]
—
—
—
WKPU[27]3
ADC1_P[4]
SIUL
—
—
—
WKPU
ADC
I
—
—
—
I
I
I
Tristate
—
41
PD[1]
PCR[49]
AF0
AF1
AF2
AF3
—
—
GPIO[49]
—
—
—
WKPU[28]3
ADC1_P[5]
SIUL
—
—
—
WKPU
ADC
I
—
—
—
I
I
I
Tristate
—
42
PD[2]
PCR[50]
AF0
AF1
AF2
AF3
—
GPIO[50]
—
—
—
ADC1_P[6]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
43
PD[3]
PCR[51]
AF0
AF1
AF2
AF3
—
GPIO[51]
—
—
—
ADC1_P[7]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
44
PD[4]
PCR[52]
AF0
AF1
AF2
AF3
—
GPIO[52]
—
—
—
ADC1_P[8]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
45
PD[5]
PCR[53]
AF0
AF1
AF2
AF3
—
GPIO[53]
—
—
—
ADC1_P[9]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
46
PD[6]
PCR[54]
AF0
AF1
AF2
AF3
—
GPIO[54]
—
—
—
ADC1_P[10]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
47
PD[7]
PCR[55]
AF0
AF1
AF2
AF3
—
GPIO[55]
—
—
—
ADC1_P[11]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
48
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
17
Package pinouts and signal descriptions
Port pin
PCR
Alternate
function1
Function
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
Pin number
64 LQFP 100 LQFP
PD[8]
PCR[56]
AF0
AF1
AF2
AF3
—
GPIO[56]
—
—
—
ADC1_P[12]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
49
PD[9]
PCR[57]
AF0
AF1
AF2
AF3
—
GPIO[57]
—
—
—
ADC1_P[13]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
56
PD[10]
PCR[58]
AF0
AF1
AF2
AF3
—
GPIO[58]
—
—
—
ADC1_P[14]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
57
PD[11]
PCR[59]
AF0
AF1
AF2
AF3
—
GPIO[59]
—
—
—
ADC1_P[15]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
58
PD[12]
PCR[60]
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
ADC1_S[8]
SIUL
DSPI_0
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
60
PD[13]
PCR[61]
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
ADC1_S[9]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
I/O
I/O
—
I
J
Tristate
—
62
PD[14]
PCR[62]
AF0
AF1
AF2
AF3
—
GPIO[62]
CS1_1
E0UC[26]
—
ADC1_S[10]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
64
PD[15]
PCR[63]
AF0
AF1
AF2
AF3
—
GPIO[63]
CS2_1
E0UC[27]
—
ADC1_S[11]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
66
Port E
MPC5602D Microcontroller Data Sheet, Rev. 6
18
Freescale Semiconductor
Package pinouts and signal descriptions
Port pin
PCR
Alternate
function1
Function
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
Pin number
64 LQFP 100 LQFP
PE[0]
PCR[64]
AF0
AF1
AF2
AF3
—
GPIO[64]
E0UC[16]
—
—
WKPU[6]3
SIUL
eMIOS_0
—
—
WKPU
I/O
I/O
—
—
I
S
Tristate
—
6
PE[1]
PCR[65]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M
Tristate
—
8
PE[2]
PCR[66]
AF0
AF1
AF2
AF3
—
—
GPIO[66]
E0UC[18]
—
—
EIRQ[21]
SIN_1
SIUL
eMIOS_0
—
—
SIUL
DSPI_1
I/O
I/O
—
—
I
I
M
Tristate
—
89
PE[3]
PCR[67]
AF0
AF1
AF2
AF3
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
M
Tristate
—
90
PE[4]
PCR[68]
AF0
AF1
AF2
AF3
—
GPIO[68]
E0UC[20]
SCK_1
—
EIRQ[9]
SIUL
eMIOS_0
DSPI_1
—
SIUL
I/O
I/O
I/O
—
I
M
Tristate
—
93
PE[5]
PCR[69]
AF0
AF1
AF2
AF3
GPIO[69]
E0UC[21]
CS0_1
MA[2]
SIUL
eMIOS_0
DSPI_1
ADC
I/O
I/O
I/O
O
M
Tristate
—
94
PE[6]
PCR[70]
AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC
SIUL
I/O
I/O
O
O
I
M
Tristate
—
95
PE[7]
PCR[71]
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC
SIUL
I/O
I/O
O
O
I
M
Tristate
—
96
PE[8]
PCR[72]
AF0
AF1
AF2
AF3
GPIO[72]
—
E0UC[22]
—
SIUL
—
eMIOS_0
—
I/O
—
I/O
—
M
Tristate
—
9
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
19
Package pinouts and signal descriptions
Port pin
PCR
Alternate
function1
Function
Peripheral
RESET
configuration
Table 5. Functional port pin descriptions (continued)
Pad
I/O
direction2 type
Pin number
64 LQFP 100 LQFP
PE[9]
PCR[73]
AF0
AF1
AF2
AF3
—
GPIO[73]
—
E0UC[23]
—
WKPU[7]3
SIUL
—
eMIOS_0
—
WKPU
I/O
—
I/O
—
I
S
Tristate
—
10
PE[10]
PCR[74]
AF0
AF1
AF2
AF3
—
GPIO[74]
—
CS3_1
—
EIRQ[10]
SIUL
—
DSPI_1
—
SIUL
I/O
—
O
—
I
S
Tristate
—
11
PE[11]
PCR[75]
AF0
AF1
AF2
AF3
—
GPIO[75]
E0UC[24]
CS4_1
—
WKPU[14]3
SIUL
eMIOS_0
DSPI_1
—
WKPU
I/O
I/O
O
—
I
S
Tristate
—
13
PE[12]
PCR[76]
AF0
AF1
AF2
AF3
—
—
GPIO[76]
—
—
—
ADC1_S[7]
EIRQ[11]
SIUL
—
—
—
ADC
SIUL
I/O
—
—
—
I
I
S
Tristate
—
76
Port H
PH[9]6 PCR[121]
AF0
AF1
AF2
AF3
GPIO[121]
—
TCK
—
SIUL
—
JTAGC
—
I/O
—
I
—
S
Input, weak
pull-up
60
88
PH[10]6 PCR[122]
AF0
AF1
AF2
AF3
GPIO[122]
—
TMS
—
SIUL
—
JTAGC
—
I/O
—
I
—
S
Input, weak
pull-up
53
81
1
2
3
4
5
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00 AF0; PCR.PA = 01 AF1; PCR.PA = 10 AF2; PCR.PA = 11 AF3. This is intended to select
the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the
values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
All WKPU pins also support external interrupt capability. See “wakeup unit” chapter of the device reference manual
for further details.
NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
“Not applicable” because these functions are available only while the device is booting. Refer to “BAM” chapter of
the device reference manual for details.
MPC5602D Microcontroller Data Sheet, Rev. 6
20
Freescale Semiconductor
Electrical characteristics
6
Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1 2001.
4
Electrical characteristics
4.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This can be done by the
internal pull-up or pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 6 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 6. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.3
NVUSRO register
Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device configuration, namely electrical
parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after
reset).
For a detailed description of the NVUSRO register, please refer to the device reference manual.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
21
Electrical characteristics
4.3.1
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 7 shows how NVUSRO[PAD3V5V] controls
the device configuration.
Table 7. PAD3V5V field description
Value1
1
4.3.2
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 8 shows how
NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Table 8. OSCILLATOR_MARGIN field description
Value1
1
4.3.3
Description
0
Low consumption configuration (4 MHz/8 MHz)
1
High margin configuration (4 MHz/16 MHz)
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value. Table 8 shows how
NVUSRO[WATCHDOG_EN] controls the device configuration.
Table 9. WATCHDOG_EN field description
Value1
1
4.4
Description
0
Disable after reset)
1
Enable after reset
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
Absolute maximum ratings
Table 10. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD
SR Voltage on VDD_HV pins with respect to
ground (VSS)
—
0.3
6.0
V
VSS_LV
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS)
—
VSS 0.1 VSS + 0.1
V
MPC5602D Microcontroller Data Sheet, Rev. 6
22
Freescale Semiconductor
Electrical characteristics
Table 10. Absolute maximum ratings (continued)
Value
Symbol
VDD_BV
Parameter
Conditions
SR Voltage on VDD_BV (regulator supply) pin
with respect to ground (VSS)
—
—
VDD_ADC SR Voltage on VDD_HV_ADC (ADC
reference) pin with respect to ground (VSS)
—
0.3
6.0
V
VSS 0.1 VSS + 0.1
0.3
V
6.0
V
VDD 0.3 VDD + 0.3
Relative to VDD
0.3
—
SR Voltage on any GPIO pin with respect to
ground (VSS)
Max
VDD 0.3 VDD + 0.3
Relative to VDD
VSS_ADC SR Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground (VSS)
VIN
Unit
Min
6.0
V
VDD 0.3 VDD + 0.3
Relative to VDD
IINJPAD
SR Injected input current on any pin during
overload condition
—
10
10
mA
IINJSUM
SR Absolute sum of all injected input currents
during overload condition
—
50
50
mA
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
70
mA
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
64
—
—
150
mA
—
55
150
°C
IAVGSEG SR Sum of all the static I/O current within a
supply segment1
ICORELV SR Low voltage static current sink through
VDD_BV
TSTORAGE SR Storage temperature
1
Supply segments are described in Section 4.7.5, I/O pad current specification.
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (VIN > VDD or
VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the
recommended values.
4.5
Recommended operating conditions
Table 11. Recommended operating conditions (3.3 V)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
VSS
SR — Digital ground on VSS_HV pins
—
0
0
V
VDD1
SR — Voltage on VDD_HV pins with respect to ground
(VSS)
—
3.0
3.6
V
SR — Voltage on VSS_LV (low voltage digital supply)
pins with respect to ground (VSS)
—
VSS_LV2
VSS 0.1 VSS + 0.1
V
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
23
Electrical characteristics
Table 11. Recommended operating conditions (3.3 V) (continued)
Value
Symbol
C
Parameter
VDD_BV3 SR — Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
Conditions
—
—
VDD_ADC4 SR — Voltage on VDD_HV_ADC pin (ADC reference)
with respect to ground (VSS)
—
SR — Voltage on any GPIO pin with respect to ground
(VSS)
Max
3.0
3.6
V
Relative to VDD VDD 0.1 VDD + 0.1
VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin
with respect to ground (VSS)
VIN
Unit
Min
VSS 0.1 VSS + 0.1
3.05
3.6
V
V
Relative to VDD VDD 0.1 VDD + 0.1
—
VSS 0.1
—
Relative to VDD
—
VDD + 0.1
V
IINJPAD
SR — Injected input current on any pin during overload
condition
—
5
5
mA
IINJSUM
SR — Absolute sum of all injected input currents during
overload condition
—
50
50
mA
SR — VDD slope to ensure correct power up6
—
—
0.25
V/µs
fCPU 48 MHz
40
85
°C
40
110
40
105
40
130
40
125
40
150
TVDD
TA C-Grade SR — Ambient temperature under bias
Part
TJ C-Grade SR — Junction temperature under bias
Part
TA V-Grade SR — Ambient temperature under bias
Part
TJ V-Grade SR — Junction temperature under bias
Part
TA M-Grade SR — Ambient temperature under bias
Part
TJ M-Grade SR — Junction temperature under bias
Part
1
2
3
4
5
6
100 nF capacitance needs to be provided between each VDD/VSS pair.
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
Guaranteed by device validation
Table 12. Recommended operating conditions (5.0 V)
Value
Symbol
VSS
C
Parameter
SR — Digital ground on VSS_HV pins
Conditions
—
Unit
Min
Max
0
0
V
MPC5602D Microcontroller Data Sheet, Rev. 6
24
Freescale Semiconductor
Electrical characteristics
Table 12. Recommended operating conditions (5.0 V) (continued)
Value
Symbol
VDD1
VSS_LV3
C
Parameter
SR — Voltage on VDD_HV pins with respect to ground
(VSS)
SR — Voltage on VSS_LV (low voltage digital supply) pins
with respect to ground (VSS)
VDD_BV4 SR — Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
Conditions
—
2
Voltage drop
Unit
Min
Max
4.5
5.5
3.0
5.5
VSS 0.1 VSS + 0.1
—
—
(2)
Voltage drop
4.5
5.5
3.0
5.5
V
V
V
Relative to VDD VDD 0.1 VDD + 0.1
VSS 0.1 VSS + 0.1
VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with
respect to ground (VSS
—
VDD_ADC5 SR — Voltage on VDD_HV_ADC pin (ADC reference) with
respect to ground (VSS)
—
4.5
5.5
Voltage drop(2)
3.0
5.5
V
V
Relative to VDD VDD 0.1 VDD + 0.1
VIN
SR — Voltage on any GPIO pin with respect to ground
(VSS)
—
VSS 0.1
—
Relative to VDD
—
VDD + 0.1
V
IINJPAD
SR — Injected input current on any pin during overload
condition
—
5
5
mA
IINJSUM
SR — Absolute sum of all injected input currents during
overload condition
—
50
50
mA
SR — VDD slope to ensure correct power up6
—
—
0.25
V/µs
fCPU 48 MHz
40
85
°C
40
110
40
105
40
130
40
125
40
150
TVDD
TA C-Grade SR — Ambient temperature under bias
Part
TJ C-Grade SR — Junction temperature under bias
Part
TA V-Grade SR — Ambient temperature under bias
Part
TJ V-Grade SR — Junction temperature under bias
Part
TA M-Grade SR — Ambient temperature under bias
Part
TJ M-Grade SR — Junction temperature under bias
Part
1
2
3
4
5
6
100 nF capacitance needs to be provided between each VDD/VSS pair.
Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Guaranteed by device validation
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
25
Electrical characteristics
NOTE
SRAM data retention is guaranteed with VDD_LV not below 1.08 V.
4.6
Thermal characteristics
4.6.1
Package thermal characteristics
Table 13. LQFP thermal characteristics1
Symbol C
Parameter
Conditions2
RJA CC D Thermal resistance, junction-to-ambient natural Single-layer board —1s
convection3
Value
Unit
LQFP64
72.1
°C/W
LQFP100
65.2
Four-layer board — 2s2p LQFP64
LQFP100
RJB CC D Thermal resistance,
junction-to-board4
RJC CC D Thermal resistance, junction-to-case5
Four-layer board — 2s2p LQFP64
Single-layer board — 1s
Single-layer board — 1s
Single-layer board — 1s
44.1
41.3
LQFP64
26.5
LQFP100
23.9
23.7
LQFP64
41
LQFP100
41.6
43.4
LQFP64
11.5
LQFP100
10.4
LQFP100
°C/W
°C/W
43
LQFP100
Four-layer board — 2s2p LQFP64
°C/W
26.2
LQFP100
Four-layer board — 2s2p LQFP64
JC CC D Junction-to-case thermal characterization
parameter, natural convection
51.8
LQFP100
Four-layer board — 2s2p LQFP64
JB CC D Junction-to-board thermal characterization
parameter, natural convection
57.3
°C/W
11.1
10.2
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C
3 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-7. Thermal test board
meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA.
4 Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB.
5 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
When Greek letters are not available, the symbols are typed as RthJC.
2
4.6.2
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
MPC5602D Microcontroller Data Sheet, Rev. 6
26
Freescale Semiconductor
Electrical characteristics
TJ = TA + (PD x RJA)
Eqn. 1
Where:
TA is the ambient temperature in °C.
RJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device
is configured to continuously drive external modules and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C)
Eqn. 2
K = PD x (TA + 273 °C) + RJA x PD2
Eqn. 3
Therefore, solving equations 1 and 2:
Where:
K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2
iteratively for any value of TA.
4.7
4.7.1
I/O pad electrical characteristics
I/O pad types
The device provides four main I/O pad types depending on the associated alternate functions:
•
•
•
Slow pads—These pads are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
Medium pads—These pads provide transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Input only pads—These pads are associated to ADC channels (ADC_P[X]) providing low input leakage.
Medium pads can use slow configuration to reduce electromagnetic emission except for PC[1], that is medium only, at the cost
of reducing AC performance.
4.7.2
I/O input DC characteristics
Table 14 provides input DC electrical characteristics as described in Figure 4.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
27
Electrical characteristics
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 4. Input DC electrical characteristics definition
Table 14. I/O input DC electrical characteristics
Symbol
C
Max
—
0.65VDD
—
VDD+0.4
V
VIL
SR P Input low level CMOS (Schmitt
Trigger)
—
0.4
—
0.35VDD
V
—
0.1VDD
—
—
V
TA = 40 °C
—
2
200
nA
TA = 25 °C
—
2
200
D
TA = 85 °C
—
5
300
D
TA = 105 °C
—
12
500
P
TA = 125 °C
—
70
1000
—
—
—
40
ns
—
1000
—
—
ns
CC D Digital input leakage
D
WFI
2
No injection
on adjacent
pin
SR P Digital input filtered pulse
WNFI(2) SR P Digital input not filtered pulse
4.7.3
Typ
SR P Input high level CMOS (Schmitt
Trigger)
ILKG
2
Unit
Min
VIH
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
1
Value
Conditions1
Parameter
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and
voltage.
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
Table 15 provides weak pull figures. Both pull-up and pull-down resistances are supported.
MPC5602D Microcontroller Data Sheet, Rev. 6
28
Freescale Semiconductor
Electrical characteristics
•
•
Table 16 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 17 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 15. I/O pull-up/pull-down DC electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min Typ Max
|IWPU| CC P Weak pull-up current
absolute value
C
P
|IWPD| CC P Weak pull-down current
absolute value
C
2
10
—
150
10
—
250
VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1
10
—
150
VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0
10
—
150
10
—
250
10
—
150
PAD3V5V =
12
PAD3V5V = 1(2)
VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1
P
1
VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 0
µA
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
Table 16. SLOW configuration output buffer electrical characteristics
Symbol C
Parameter
Push Pull IOH = 2 mA,
VOH CC P Output high level
SLOW configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
1
Unit
Min
Typ
Max
0.8VDD
—
—
C
IOH = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD 0.8
—
—
VOL CC P Output low level
Push Pull IOL = 2 mA,
SLOW configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
2
Value
Conditions1
—
— 0.1VDD
C
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
—
— 0.1VDD
C
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
V
V
0.5
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
29
Electrical characteristics
Table 17. MEDIUM configuration output buffer electrical characteristics
Symbol C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
Push Pull IOH = 3.8 mA,
VOH CC C Output high level
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
P
IOH = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
C
IOH = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD 0.8 —
—
C
IOH = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
VOL CC C Output low level
Push Pull IOL = 3.8 mA,
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
— 0.2VDD
P
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
— 0.1VDD
C
IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
—
— 0.1VDD
C
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
C
IOL = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
— 0.1VDD
1
2
V
V
0.5
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
MPC5602D Microcontroller Data Sheet, Rev. 6
30
Freescale Semiconductor
Electrical characteristics
4.7.4
Output pin transition times
Table 18. Output pin transition times
Symbol C
Value
Conditions1
Parameter
Unit
Min Typ Max
ttr CC D Output transition time output pin2 CL = 25 pF
SLOW configuration
T
CL = 50 pF
2
4.7.5
—
50
—
—
100
—
—
125
D
CL = 100 pF
D
CL = 25 pF
VDD = 3.3 V ± 10%, PAD3V5V = 1 —
—
50
T
CL = 50 pF
—
—
100
D
CL = 100 pF
—
—
125
VDD = 5.0 V ± 10%, PAD3V5V = 0 —
SIUL.PCRx.SRC = 1
—
—
10
—
20
—
—
40
VDD = 3.3 V ± 10%, PAD3V5V = 1 —
SIUL.PCRx.SRC = 1
—
—
12
—
25
—
—
40
ttr CC D Output transition time output
pin(2)
T
MEDIUM configuration
D
1
VDD = 5.0 V ± 10%, PAD3V5V = 0 —
CL = 25 pF
CL = 50 pF
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
D
CL = 100 pF
ns
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
CL includes device and package capacitances (CPKG < 5 pF).
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 19.
Table 20 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG
maximum value.
Table 19. I/O supply segment
Supply segment
Package
1
2
3
4
100 LQFP
pin 16 – pin 35
pin 37 – pin 69
pin 70 – pin 83
pin 84 – pin 15
64 LQFP
pin 8 – pin 26
pin 28 – pin 55
pin 56 – pin 7
—
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
31
Electrical characteristics
Table 20. I/O consumption
Symbol
ISWTSLW,2
ISWTMED(2)
IRMSSLW
C
—
20
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16
CC D Dynamic I/O current CL = 25 pF
for MEDIUM
configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
CC D Root mean square
CL = 25 pF, 2 MHz
I/O current for SLOW
CL = 25 pF, 4 MHz
configuration
CL = 100 pF, 2 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
—
—
6.6
—
—
13.4
—
—
18.3
—
—
5
—
—
8.5
CL = 100 pF, 13 MHz
—
—
11
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
CC D Root mean square
I/O current for
MEDIUM
configuration
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 25 pF, 40 MHz
SR D Sum of all the static
I/O current within a
supply segment
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz
2
Max
—
CL = 100 pF, 2 MHz
1
Typ
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 25 pF, 4 MHz
IAVGSEG
Unit
Min
CC D Dynamic I/O current CL = 25 pF
for SLOW
configuration
CL = 25 pF, 2 MHz
IRMSMED
Value
Conditions1
Parameter
VDD = 3.3 V ± 10%,
PAD3V5V = 1
mA
mA
mA
mA
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 21 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below 100%.
MPC5602D Microcontroller Data Sheet, Rev. 6
32
Freescale Semiconductor
Electrical characteristics
Table 21. I/O weight1
100 LQFP/64 LQFP
Pad
Weight 5 V
Weight 3.3 V
SRC2 = 0
SRC = 1
SRC = 0
SRC = 1
PB[3]
9%
9%
10%
10%
PC[9]
8%
8%
10%
10%
PC[14]
8%
8%
10%
10%
PC[15]
8%
11%
9%
10%
PA[2]
8%
8%
9%
9%
PE[0]
7%
7%
9%
9%
PA[1]
7%
7%
8%
8%
PE[1]
7%
10%
8%
8%
PE[8]
6%
9%
8%
8%
PE[9]
6%
6%
7%
7%
PE[10]
6%
6%
7%
7%
PA[0]
5%
7%
6%
7%
PE[11]
5%
5%
6%
6%
PC[11]
7%
7%
9%
9%
PC[10]
8%
11%
9%
10%
PB[0]
8%
11%
9%
10%
PB[1]
8%
8%
10%
10%
PC[6]
8%
8%
10%
10%
PC[7]
8%
8%
10%
10%
PA[15]
8%
11%
9%
10%
PA[14]
7%
11%
9%
9%
PA[4]
7%
7%
8%
8%
PA[13]
7%
10%
8%
9%
PA[12]
7%
7%
8%
8%
PB[9]
1%
1%
1%
1%
PB[8]
1%
1%
1%
1%
PB[10]
5%
5%
6%
6%
PD[0]
1%
1%
1%
1%
PD[1]
1%
1%
1%
1%
PD[2]
1%
1%
1%
1%
PD[3]
1%
1%
1%
1%
PD[4]
1%
1%
1%
1%
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
33
Electrical characteristics
Table 21. I/O weight1 (continued)
100 LQFP/64 LQFP
Pad
Weight 5 V
Weight 3.3 V
SRC2 = 0
SRC = 1
SRC = 0
SRC = 1
PD[5]
1%
1%
1%
1%
PD[6]
1%
1%
1%
1%
PD[7]
1%
1%
1%
1%
PD[8]
1%
1%
1%
1%
PB[4]
1%
1%
1%
1%
PB[5]
1%
1%
1%
1%
PB[6]
1%
1%
1%
1%
PB[7]
1%
1%
1%
1%
PD[9]
1%
1%
1%
1%
PD[10]
1%
1%
1%
1%
PD[11]
1%
1%
1%
1%
PB[11]
9%
9%
11%
11%
PD[12]
8%
8%
10%
10%
PB[12]
8%
8%
10%
10%
PD[13]
8%
8%
9%
9%
PB[13]
8%
8%
9%
9%
PD[14]
7%
7%
9%
9%
PB[14]
7%
7%
8%
8%
PD[15]
7%
7%
8%
8%
PB[15]
6%
6%
7%
7%
PA[3]
6%
6%
7%
7%
PA[7]
4%
4%
5%
5%
PA[8]
4%
4%
5%
5%
PA[9]
4%
4%
5%
5%
PA[10]
5%
5%
6%
6%
PA[11]
5%
5%
6%
6%
PE[12]
5%
5%
6%
6%
PC[3]
5%
5%
6%
6%
PC[2]
5%
7%
6%
6%
PA[5]
5%
6%
5%
6%
PA[6]
4%
4%
5%
5%
PC[1]
5%
17%
4%
12%
MPC5602D Microcontroller Data Sheet, Rev. 6
34
Freescale Semiconductor
Electrical characteristics
Table 21. I/O weight1 (continued)
100 LQFP/64 LQFP
Pad
1
2
4.8
Weight 5 V
Weight 3.3 V
SRC2 = 0
SRC = 1
SRC = 0
SRC = 1
PC[0]
6%
9%
7%
8%
PE[2]
7%
10%
8%
9%
PE[3]
7%
10%
9%
9%
PC[5]
8%
11%
9%
10%
PC[4]
8%
11%
9%
10%
PE[4]
8%
12%
10%
10%
PE[5]
8%
12%
10%
11%
PE[6]
9%
12%
10%
11%
PE[7]
9%
12%
10%
11%
PC[12]
9%
13%
11%
11%
PC[13]
9%
9%
11%
11%
PC[8]
9%
9%
11%
11%
PB[2]
9%
13%
11%
12%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
SRC: “Slew Rate Control” bit in SIU_PCR
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
VDD
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
device start-up phase
Figure 5. Start-up reset requirements
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
35
Electrical characteristics
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 6. Noise filtering on reset signal
Table 22. Reset electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD + 0.4
V
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
0.4
—
0.35VDD
V
VHYS
CC C Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
VOL
CC P Output low level
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
MPC5602D Microcontroller Data Sheet, Rev. 6
36
Freescale Semiconductor
Electrical characteristics
Table 22. Reset electrical characteristics (continued)
Symbol
ttr
C
Parameter
CC D Output transition time
output pin3
MEDIUM configuration
Value
Conditions1
Unit
Min
Typ
Max
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
ns
WFRST SR P RESET input filtered
pulse
—
—
—
40
ns
WNFRST SR P RESET input not filtered
pulse
—
1000
—
—
ns
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
µA
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 14
10
—
250
|IWPU| CC P Weak pull-up current
absolute value
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the device reference manual).
3 C includes device and package capacitance (C
L
PKG < 5 pF).
4 The configuration PAD3V5 = 1 when V
DD = 5 V is only transient configuration during power-up. All pads but RESET
are configured in input or in high impedance state.
1
2
4.9
4.9.1
Power management electrical characteristics
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage
ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved:
•
•
•
HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD
power pin.
BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV
power pin. Voltage values should be aligned with VDD.
LV: Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
37
Electrical characteristics
— LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
CREG2 (LV_COR/LV_CFLA)
VDD
VSS_LV
VDD_BV
Voltage Regulator
I
VSS_LVn
DEVICE
VDD_BV
CREG1 (LV_COR/LV_DFLA)
VDD_LVn
CDEC1 (Ballast decoupling)
VREF
VDD_LV
VDD_LV
DEVICE
VSS_LV
VSS_LV
VDD_LV
VSS
VDD
CDEC2
(supply/IO decoupling)
CREG3
(LV_COR/LV_PLL)
Figure 7. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see
Section 4.5, Recommended operating conditions).
Table 23. Voltage regulator electrical characteristics
Symbol
C
Parameter
CREGn
SR — Internal voltage regulator external
capacitance
RREG
SR — Stability capacitor equivalent serial
resistance
Value
Conditions1
—
Range:
10 kHz to 20 MHz
Unit
Min
Typ
Max
200
—
500
nF
—
—
0.2
MPC5602D Microcontroller Data Sheet, Rev. 6
38
Freescale Semiconductor
Electrical characteristics
Table 23. Voltage regulator electrical characteristics (continued)
Symbol
CDEC1
C
Parameter
SR — Decoupling capacitance2 ballast
4704
—
VDD_BV/VSS_LV pair:
VDD_BV = 3 V to 3.6 V
400
nF
—
—
nF
VMREG
CC T Main regulator output voltage
Before exiting from reset
—
1.32
—
V
1.16
1.28
—
—
—
150
mA
mA
After trimming
SR — Main regulator current provided to
VDD_LV domain
—
IMREGINT CC D Main regulator module current
consumption
IMREG = 200 mA
—
—
2
IMREG = 0 mA
—
—
1
VLPREG
CC P Low-power regulator output voltage
After trimming
1.16
1.28
—
V
ILPREG
SR — Low power regulator current provided
to VDD_LV domain
—
—
15
mA
ILPREG = 15 mA;
TA = 55 °C
—
—
600
µA
ILPREG = 0 mA;
TA = 55 °C
—
5
—
After trimming
1.16
1.28
—
V
—
—
5
mA
IULPREG = 5 mA;
TA = 55 °C
—
—
100
µA
IULPREG = 0 mA;
TA = 55 °C
—
2
—
—
—
3006
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
IULPREGINT CC D Ultra low power regulator module
current consumption
IDD_BV
6
1003
100
VULPREG CC P Ultra low power regulator output
voltage
5
VDD_BV/VSS_LV pair:
VDD_BV = 4.5 V to 5.5 V
10
—
4
Max
VDD/VSS pair
ILPREGINT CC D Low-power regulator module current
consumption
3
Typ
SR — Decoupling capacitance regulator
supply
IMREG
2
Unit
Min
CDEC2
P
1
Value
Conditions1
CC D In-rush average current on VDD_BV
during power-up5
—
—
—
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
This value is acceptable to guarantee operation from 4.5 V to 5.5 V.
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 µs,
depending on external capacitances to be loaded).
The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must
be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
39
Electrical characteristics
4.9.2
Low voltage detector electrical characteristics
The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well as five low voltage
detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied:
•
•
•
•
•
•
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state (refer to RGM
Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual)
LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer to RGM Destructive Event
Status (RGM_DES) Register flag F_LVD27 in device reference manual)
LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply (refer to RGM Destructive
Event Status (RGM_DES) Register flag F_LVD27_VREG in device reference manual)
LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to RGM Functional Event Status
(RGM_FES) Register flag F_LVD45 in device reference manual)
LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD1 in device reference manual)
LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD0 in device reference manual)
VDD
VLVDHVxH
VLVDHVxL
RESET
Figure 8. Low voltage detector vs reset
MPC5602D Microcontroller Data Sheet, Rev. 6
40
Freescale Semiconductor
Electrical characteristics
Table 24. Low voltage detector electrical characteristics
Symbol
C
VPORUP
SR P Supply for functional POR module
VPORH
CC P Power-on reset threshold
Value
Conditions1
Parameter
Unit
Min
Typ
Max
1.0
—
5.5
V
1.5
—
2.6
V
TA = 25 °C,
after trimming
VLVDHV3H
CC T LVDHV3 low voltage detector high threshold
—
—
2.95
V
VLVDHV3L
CC P LVDHV3 low voltage detector low threshold
2.6
—
2.9
V
VLVDHV3BH CC P LVDHV3B low voltage detector high threshold
—
—
2.95
V
VLVDHV3BL CC P LVDHV3B low voltage detector low threshold
2.6
—
2.9
V
VLVDHV5H
CC T LVDHV5 low voltage detector high threshold
—
—
4.5
V
VLVDHV5L
CC P LVDHV5 low voltage detector low threshold
3.8
—
4.4
V
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
1.08
—
1.16
V
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
1.08
—
1.16
V
1
4.10
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Power consumption
Table 25 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 25. Power consumption on VDD_BV and VDD_HV
Symbol
C
Typ
Max
—
90
1303
mA
fCPU = 8 MHz
—
7
—
mA
fCPU = 16 MHz
—
18
—
T
fCPU = 32 MHz
—
29
—
P
fCPU = 48 MHz
—
40
100
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
TA = 125 °C
—
8
15
—
14
25
—
180
7008
D
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
TA = 55 °C
—
500
—
D
TA = 85 °C
—
1
6(8)
CC D RUN mode maximum
average current
IDDRUN4
CC T RUN mode typical
average current5
T
CC C HALT mode current6
P
IDDSTOP
Unit
Min
IDDMAX2
IDDHALT
Value
Conditions1
Parameter
CC P STOP mode
current7
—
D
TA = 105 °C
—
2
9(8)
P
TA = 125 °C
—
4.5
12(8)
mA
µA
mA
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
41
Electrical characteristics
Table 25. Power consumption on VDD_BV and VDD_HV (continued) (continued)
Symbol
IDDSTDBY
1
2
3
4
5
6
7
8
9
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
CC P STANDBY mode current9 Slow internal RC oscillator TA = 25 °C
(128 kHz) running
D
TA = 55 °C
—
30
100
—
75
—
D
TA = 85 °C
—
180
700
D
TA = 105 °C
—
315
1000
P
TA = 125 °C
—
560
1700
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Running consumption does not include I/Os toggling which is highly dependent on the application. The given value
is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify
operation ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used
peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions,
use low power mode when possible.
Higher current may be sinked by device during power-up and standby exit. Please refer to in-rush average current
on Table 23.
RUN current measured with typical application with accesses on both flash memory and SRAM.
Only for the “P” classification: Code fetched from SRAM: serial IPs CAN and LIN in loop-back mode, DSPI as Master,
PLL as system clock (3 × Multiplier) peripherals on (eMIOS/CTU/ADC) and running at maximum frequency, periodic
SW/WDG timer reset enabled.
Data flash power down. Code flash in low power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock.
FlexCAN: 0 ON (clocked but no reception or transmission). LINFlex: instances: 0, 1, 2 ON (clocked but no reception
or transmission), instance: 3 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15])
with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON.
STM ON. ADC ON but no conversion except 2 analog watchdogs.
Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPVreg off,
ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.
When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.
Only for the “P” classification: ULPVreg on, HP/LPVreg off, 16 KB SRAM on, device configured for minimum
consumption, all possible modules switched off.
4.11
Flash memory electrical characteristics
The data flash operation depends strongly on the code flash operation. If code flash is switched-off, the data flash is disabled.
4.11.1
Program/Erase characteristics
Table 26 shows the program and erase characteristics.
MPC5602D Microcontroller Data Sheet, Rev. 6
42
Freescale Semiconductor
Electrical characteristics
Table 26. Program and erase specifications (code flash)
Value
Symbol
C
Parameter
Min
Typ1
Initial
max2
Max3
Unit
tdwprogram
CC C Double word (64 bits) program time4
—
22
50
500
µs
t16Kpperase
CC C 16 KB block preprogram and erase time
—
300
500
5000
ms
t32Kpperase
CC C 32 KB block preprogram and erase time
—
400
600
5000
ms
—
800
1300
7500
ms
—
—
30
30
µs
t128Kpperase CC C 128 KB block preprogram and erase time
tesus
CC C Erase suspend latency
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
Table 27. Program and erase specifications (data flash)
Value
Symbol
C
Parameter
Unit
Min
Typ1
Initial
max2
Max3
—
30
70
300
µs
t16Kpperase CC C 16 KB block preprogram and erase time
—
700
800
1500
ms
CC C 64 KB block preprogram and erase time
—
1900
2300
4800
ms
tswprogram
tBank_D
CC C Single word (32 bits) program time4
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4 Actual hardware programming times. This does not include software overhead.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
43
Electrical characteristics
Table 28. Flash module life
Value
Symbol
P/E
C
Parameter
CC C Number of program/erase
cycles per block over the
operating temperature range
(TJ)
Conditions
Unit
Min
Typ
Max
16 KB blocks
100,000
—
—
cycles
32 KB blocks
10,000 100,000
—
cycles
128 KB blocks
1,000
100,000
—
cycles
20
—
—
years
Blocks with
1,001–10,000 P/E cycles
10
—
—
Blocks with
10,001–100,000 P/E cycles
5
—
—
Retention CC C Minimum data retention at 85 °C Blocks with
average ambient temperature1 0–1,000 P/E cycles
1
Ambient temperature averaged over application duration. It is recommended not to exceed the product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units
will experience single bit corrections throughout the life of the product with no impact to product reliability.
Table 29. Flash memory read access timing
Symbol
C
Conditions1 Max Unit
Parameter
fCFREAD CC P Maximum working frequency for reading code flash memory at given
number of wait states in worst conditions
C
2 wait states
48
0 wait states
20
fDFREAD CC P Maximum working frequency for reading data flash memory at given
number of wait states in worst conditions
6 wait states
48
1
MHz
MHz
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
4.11.2
Flash power supply DC characteristics
Table 30 shows the power supply DC characteristics on external supply.
NOTE
Power supply for data flash is actually provided by code flash; this means that data flash
cannot work if code flash is not powered.
Table 30. Flash power supply DC electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min Typ Max
ICFREAD CC D Sum of the current consumption on Flash module read
and VDDBV on read access fCPU = 48 MHz
V
IDFREAD CC D DDHV
Code flash
—
—
33
mA
Data flash
—
—
4
mA
Code flash
ICFMOD CC D Sum of the current consumption on Program/Erase on-going
while reading flash registers,
VDDHV and VDDBV on matrix
IDFMOD CC D
Data flash
modification (program/erase)
fCPU = 48 MHz
—
—
33
mA
—
—
6
mA
MPC5602D Microcontroller Data Sheet, Rev. 6
44
Freescale Semiconductor
Electrical characteristics
Table 30. Flash power supply DC electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min Typ Max
CC D Sum of the current consumption on
VDDHV and VDDBV during
flash low-power mode
—
Code flash
—
— 910 µA
ICFPWD CC D Sum of the current consumption on
and VDDBV during
V
IDFPWD CC D DDHV
flash power-down mode
—
Code flash
—
— 125 µA
Data flash
—
—
IFLPW
25
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
1
4.11.3
Start-up/Switch-off timings
Table 31. Start-up time/Switch-off time
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
tFLARSTEXIT CC T Delay for flash module to exit reset mode Code flash
—
—
125
µs
Data flash
—
—
150
µs
tFLALPEXIT
CC T Delay for flash module to exit low-power
mode2
Code flash
—
—
0.5
µs
tFLAPDEXIT
CC T Delay for flash module to exit power-down Code flash
mode
Data flash
—
—
30
µs
—
—
3
30
µs
tFLALPENTRY CC T Delay for flash module to enter low-power Code flash
mode
—
—
0.5
µs
tFLAPDENTRY CC T Delay for flash module to enter
power-down mode
—
—
1.5
µs
—
4(3)
µs
Code flash
Data flash
—
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Data flash does not support low-power mode
3
If code flash is already switched-on.
1
2
4.12
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for his application.
•
Software recommendations The software flowchart must include the management of runaway conditions such as:
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
45
Electrical characteristics
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
•
4.12.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1
standard, which specifies the general conditions for EMI measurements.
Table 32. EMI radiated emission measurement1 2
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
—
0.150
—
fCPU SR — Operating frequency
—
—
48
—
MHz
VDD_LV SR — LV operating voltages
—
—
1.28
—
V
No PLL frequency
VDD = 5 V, TA = 25 °C,
modulation
100 LQFP package
Test conforming to IEC 61967-2,
± 2% PLL frequency
fOSC = 8 MHz/fCPU = 48 MHz
modulation
—
—
18
dBµ
V
—
—
14
dBµ
V
—
SR — Scan range
SEMI CC T Peak level
1
2
Max
1000 MHz
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
4.12.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
4.12.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin).
This test conforms to the AEC-Q100-002/-003/-011 standard.
MPC5602D Microcontroller Data Sheet, Rev. 6
46
Freescale Semiconductor
Electrical characteristics
Table 33. ESD absolute maximum ratings1 2
Symbol
C
Ratings
Conditions
Class
Max value
Unit
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
V
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
V
750 (corners)
V
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
4.12.3.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 34. Latch-up results
Symbol
LU
CC
C
Parameter
T Static latch-up class
Conditions
TA = 125 °C
conforming to JESD 78
Class
II level A
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
47
Electrical characteristics
4.13
Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
Table 35 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
EXTAL
C1
Crystal
EXTAL
XTAL
C2
DEVICE
VDD
I
R
EXTAL
XTAL
Resonator
DEVICE
XTAL
DEVICE
Notes:
1. XTAL/EXTAL must not be directly used to drive external circuits
2. A series resistor may be required, according to crystal oscillator supplier recommendations.
Figure 9. Crystal oscillator and resonator connection scheme
MPC5602D Microcontroller Data Sheet, Rev. 6
48
Freescale Semiconductor
Electrical characteristics
Table 35. Crystal description
Nominal
NDK crystal
frequency
reference
(MHz)
Crystal
equivalent
series
resistance
(ESR)
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2 (pF)1
Shunt
capacitance
between xtalout
and xtalin
C02 (pF)
4
NX8045GB
300
2.68
591.0
21
2.93
8
NX5032GA
300
2.46
160.7
17
3.01
10
150
2.93
86.6
15
2.91
12
120
3.11
56.5
15
2.93
16
120
3.90
25.3
10
3.00
1
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
S_MTRANS bit (ME_GS register)
‘1’
‘0’
VXTAL
1/fFXOSC
VFXOSC
90%
VFXOSCOP
10%
TFXOSCSU
valid internal clock
Figure 10. Fast external crystal oscillator (4 to 16 MHz) timing diagram
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
49
Electrical characteristics
Table 36. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol
fFXOSC
gmFXOSC
VFXOSC
C
Parameter
IFXOSC
tFXOSCSU
1
2
Unit
Min
Typ
Max
4.0
—
16.0
MHz
CC C Fast external crystal
VDD = 3.3 V ± 10%,
oscillator transconductance PAD3V5V = 1
OSCILLATOR_MARGIN = 0
2.2
—
8.2
mA/V
CC P
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
2.0
—
7.4
CC C
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
2.7
—
9.7
CC C
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
2.5
—
9.2
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
—
—
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.3
—
—
—
—
0.95
CC T Fast external crystal
oscillator consumption
—
—
2
3
mA
CC T Fast external crystal
oscillator start-up time
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6
ms
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
—
—
1.8
SR — Fast external crystal
oscillator frequency
VFXOSCOP CC P Oscillation operating point
2
Value
Conditions1
—
V
V
VIH
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
—
VDD+0.4
V
VIL
SR P Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.4
—
0.35VDD
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
MPC5602D Microcontroller Data Sheet, Rev. 6
50
Freescale Semiconductor
Electrical characteristics
4.14
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
Table 37. FMPLL electrical characteristics
Symbol
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
fPLLIN
SR — FMPLL reference clock2
—
4
—
48
MHz
PLLIN
SR — FMPLL reference clock duty
cycle(2)
—
40
—
60
%
—
16
—
48
MHz
—
256
—
512
MHz
—
245
—
533
fPLLOUT CC D FMPLL output clock frequency
fVCO3
CC P VCO frequency without
frequency modulation
VCO frequency with frequency
modulation
fCPU
SR — System clock frequency
—
—
—
48
MHz
fFREE
CC P Free-running frequency
—
20
—
150
MHz
tLOCK
CC P FMPLL lock time
Stable oscillator (fPLLIN = 16 MHz)
—
40
100
µs
fPLLIN = 16 MHz (resonator),
fPLLCLK at 48 MHz, 4,000 cycles
—
—
10
ns
TA = 25 °C
—
—
4
mA
tLTJIT CC — FMPLL long term jitter
IPLL
CC C FMPLL consumption
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.
3
Frequency modulation is considered ±4%.
1
2
4.15
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator (FIRC). This is used as the default clock at the power-up of the device.
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol
fFIRC
IFIRCRUN2,
IFIRCPWD
C
Parameter
Value
Conditions1
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
SR —
—
Unit
Min
Typ
Max
—
16
—
12
MHz
20
CC T Fast internal RC oscillator high TA = 25 °C, trimmed
frequency current in running
mode
—
—
200
µA
CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
down mode
—
—
10
µA
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
51
Electrical characteristics
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Symbol
C
Value
Conditions1
Parameter
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C
frequency and system clock
current in stop mode
Unit
Min
Typ
Max
sysclk = off
—
500
—
sysclk = 2 MHz
—
600
—
sysclk = 4 MHz
—
700
—
sysclk = 8 MHz
—
900
—
sysclk = 16 MHz
—
1250
—
µA
tFIRCSU
CC C Fast internal RC oscillator
start-up time
VDD = 5.0 V ± 10%
—
1.1
2.0
µs
FIRCPRE
CC C Fast internal RC oscillator
precision after software
trimming of fFIRC
TA = 25 °C
1
—
1
%
FIRCTRIM CC C Fast internal RC oscillator
trimming step
TA = 25 °C
—
1.6
5
—
FIRCVAR
CC C Fast internal RC oscillator
variation in temperature and
supply with respect to fFIRC at
TA = 55 °C in high-frequency
configuration
—
%
5
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
1
2
4.16
Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator (SIRC). This can be used as the reference clock for the RTC module.
Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
—
128
—
100
—
150
—
—
5
µA
CC P Slow internal RC oscillator low
frequency
SR —
TA = 25 °C, trimmed
ISIRC2,
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
tSIRCSU
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10%
time
—
8
12
µs
SIRCPRE
CC C Slow internal RC oscillator precision TA = 25 °C
after software trimming of fSIRC
2
—
2
%
SIRCTRIM
CC C Slow internal RC oscillator trimming
step
—
2.7
—
fSIRC
—
—
kHz
MPC5602D Microcontroller Data Sheet, Rev. 6
52
Freescale Semiconductor
Electrical characteristics
Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
Symbol
SIRCVAR
1
2
C
Parameter
Value
Conditions1
CC P Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
respect to fSIRC at TA = 55 °C in high
frequency configuration
Unit
Min
Typ
Max
10
—
10
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
53
Electrical characteristics
4.17
4.17.1
ADC electrical characteristics
Introduction
The device provides a 12-bit Successive Approximation Register (SAR) analog-to-digital converter.
Offset Error (EO)
Gain Error (EG)
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
5
(5)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error (EO)
Figure 11. ADC characteristics and error definitions
MPC5602D Microcontroller Data Sheet, Rev. 6
54
Freescale Semiconductor
Electrical characteristics
4.17.2
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being CS and Cp2
substantially two switched capacitances, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive
path to ground. For instance, assuming a conversion rate of 1 MHz, with CS+Cp2 equal to 3 pF, a resistance of 330 k is
obtained (REQ = 1 / (fc × (CS+Cp2)), where fc represents the conversion rate at the considered channel). To minimize the error
induced by the voltage partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of RS + RF, the external
circuit must be designed to respect the Equation 4:
Eqn. 4
RS + RF
1
V A --------------------- --- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on a resistive path.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
55
Electrical characteristics
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
Current Limiter
RF
RL
CF
VA
Channel
Selection
Sampling
RSW1
RAD
CP1
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
Figure 12. Input equivalent circuit (precise channels)
MPC5602D Microcontroller Data Sheet, Rev. 6
56
Freescale Semiconductor
Electrical characteristics
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
Current Limiter
RF
RL
CF
VA
Channel
Selection
Extended
Switch
Sampling
RSW1
RSW2
RAD
CP1
CP3
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance (two contributions, RSW1 and RSW2)
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1, CP2 and CP3)
CS: Sampling capacitance
Figure 13. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit in Figure 13): A charge sharing phenomenon is installed
when the sampling phase is started (A/D switch close).
Voltage transient on CS
VCS
VA
VA2
V
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