Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5604P
Rev. 8, 07/2012
MPC5604P
144 LQFP
20 mm x 20 mm
100 LQFP
14 mm x 14 mm
Qorivva MPC5604P
Microcontroller Data Sheet
•
•
•
•
•
•
•
•
Up to 64 MHz, single issue, 32-bit CPU core complex
(e200z0h)
— Compliant with Power Architecture embedded
category
— Variable Length Encoding (VLE)
Memory organization
— Up to 512 KB on-chip code flash memory with ECC
and erase/program controller
— Optional 64 (4 × 16) KB on-chip data flash memory
with ECC for EEPROM emulation
— Up to 40 KB on-chip SRAM with ECC
Fail safe protection
— Programmable watchdog timer
— Non-maskable interrupt
— Fault collection unit
Nexus L2+ interface
Interrupts
— 16-channel eDMA controller
— 16 priority level controller
General purpose I/Os individually programmable as input,
output or special function
2 general purpose eTimer units
— 6 timers each with up/down count capabilities
— 16-bit resolution, cascadable counters
— Quadrature decode with rotation direction flag
— Double buffer input capture and output compare
Communications interfaces
— 2 LINFlex channels (LIN 2.1)
— 4 DSPI channels with automatic chip select
generation
— 1 FlexCAN interface (2.0B Active) with 32 message
objects
—
•
•
•
•
•
•
1 safety port based on FlexCAN with 32 message
objects and up to 7.5 Mbit/s capability; usable as
second CAN when not used as safety port
— 1 FlexRay™ module (V2.1) with selectable dual or
single channel support, 32 message objects and up to
10 Mbit/s
Two 10-bit analog-to-digital converters (ADC)
— 2 × 15 input channels, 4 channels shared between the
two ADCs
— Conversion time < 1 µs including sampling time at
full precision
— Programmable Cross Triggering Unit (CTU)
— 4 analog watchdogs with interrupt capability
On-chip CAN/UART bootstrap loader with Boot Assist
Module (BAM)
1 FlexPWM unit
— 8 complementary or independent outputs with ADC
synchronization signals
— Polarity control, reload unit
— Integrated configurable dead time unit and inverter
fault input pins
— 16-bit resolution, up to 2 × fCPU
— Lockable configuration
Clock generation
— 4–40 MHz main oscillator
— 16 MHz internal RC oscillator
— Software controlled FMPLL capable of speeds as fast
as 64 MHz
Voltage supply
— 3.3 V or 5 V supply for I/Os and ADC
— On-chip single supply voltage regulator with external
ballast transistor
Operating temperature ranges: –40 to 125 °C or –40
to 105 °C
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale, Inc., 2008–2012. All rights reserved.
Table of Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High performance e200z0 core processor. . . . . .7
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Enhanced direct memory access (eDMA) . . . . . .8
1.5.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.5.5 Static random access memory (SRAM). . . . . . . .9
1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . .9
1.5.7 System status and configuration module
(SSCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.5.8 System clocks and clock generation . . . . . . . . .10
1.5.9 Frequency-modulated phase-locked loop
(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.5.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . 11
1.5.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . 11
1.5.13 System timer module (STM) . . . . . . . . . . . . . . . 11
1.5.14 Software watchdog timer (SWT) . . . . . . . . . . . . 11
1.5.15 Fault collection unit (FCU) . . . . . . . . . . . . . . . . .12
1.5.16 System integration unit – Lite (SIUL) . . . . . . . . .12
1.5.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . .12
1.5.18 Error correction status module (ECSM). . . . . . .13
1.5.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .13
1.5.20 Controller area network (FlexCAN) . . . . . . . . . .13
1.5.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . .14
1.5.22 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.5.23 Serial communication interface module
(LINFlex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.24 Deserial serial peripheral interface (DSPI) . . . .15
1.5.25 Pulse width modulator (FlexPWM) . . . . . . . . . .16
1.5.26 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.27 Analog-to-digital converter (ADC) module . . . . .17
1.5.28 Cross triggering unit (CTU) . . . . . . . . . . . . . . . .18
1.5.29 Nexus development interface (NDI). . . . . . . . . .18
1.5.30 Cyclic redundancy check (CRC) . . . . . . . . . . . .19
1.5.31 IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . .19
1.5.32 On-chip voltage regulator (VREG). . . . . . . . . . .19
Package pinouts and signal descriptions . . . . . . . . . . . . . . . .20
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.1 Power supply and reference voltage pins . . . . .21
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2.3 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . .
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .
3.4 Recommended operating conditions . . . . . . . . . . . . . .
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Package thermal characteristics . . . . . . . . . . .
3.5.2 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . .
3.6 Electromagnetic interference (EMI) characteristics . . .
3.7 Electrostatic discharge (ESD) characteristics . . . . . . .
3.8 Power management electrical characteristics . . . . . . .
3.8.1 Voltage regulator electrical characteristics . . . .
3.8.2 Voltage monitor electrical characteristics . . . . .
3.9 Power up/down sequencing . . . . . . . . . . . . . . . . . . . .
3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . .
3.10.1 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . .
3.10.2 DC electrical characteristics (5 V) . . . . . . . . . .
3.10.3 DC electrical characteristics (3.3 V) . . . . . . . . .
3.10.4 Input DC electrical characteristics definition . .
3.10.5 I/O pad current specification. . . . . . . . . . . . . . .
3.11 Main oscillator electrical characteristics . . . . . . . . . . .
3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . .
3.13 16 MHz RC oscillator electrical characteristics . . . . . .
3.14 Analog-to-digital converter (ADC) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1 Input impedance and ADC accuracy . . . . . . . .
3.14.2 ADC conversion characteristics . . . . . . . . . . . .
3.15 Flash memory electrical characteristics. . . . . . . . . . . .
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . .
3.17 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . .
3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . .
3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . .
3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . .
3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . .
4.1.1 144 LQFP mechanical outline drawing . . . . . .
4.1.2 100 LQFP mechanical outline drawing . . . . . .
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix AAbbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
24
38
38
38
39
42
46
46
47
48
48
49
49
52
53
55
55
55
57
58
59
64
65
67
67
68
72
74
75
75
76
76
78
81
83
84
90
90
90
92
96
97
98
MPC5604P Microcontroller Data Sheet, Rev. 8
2
Freescale
1
Introduction
1.1
Document overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5603P/4P series of
microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical
characteristics. For functional characteristics, refer to the device reference manual.
1.2
Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive
application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis
applications—specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as airbag
applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture
technology.
The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture
embedded category. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with users implementations.
1.3
Device comparison
Table 1 provides a summary of different members of the MPC5604P family and their features to enable a comparison among
the family members and an understanding of the range of functionality offered within this family.
Table 1. MPC5604P device comparison
Feature
Code flash memory (with ECC)
MPC5603P
MPC5604P
384 KB
512 KB
Data flash memory / EE option (with ECC)
SRAM (with ECC)
64 KB (optional feature)
36 KB
40 KB
Processor core
32-bit e200z0h
Instruction set
VLE (variable length encoding)
CPU performance
0–64 MHz
FMPLL (frequency-modulated phase-locked loop)
module
INTC (interrupt controller) channels
PIT (periodic interrupt timer)
1
16
Optional feature
FlexCAN (controller area network)
Safety port
147
1 (includes four 32-bit timers)
eDMA (enhanced direct memory access) channels
FlexRay
2
22,3
Yes (via second FlexCAN module)
FCU (fault collection unit)
Yes
CTU (cross triggering unit)
Yes
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
3
Table 1. MPC5604P device comparison (continued)
Feature
MPC5603P
eTimer
MPC5604P
2 (16-bit, 6 channels)
FlexPWM (pulse-width modulation) channels
8 (capturing on X-channels)
2 (10-bit, 15-channel4)
ADC (analog-to-digital converter)
LINFlex
2
DSPI (deserial serial peripheral interface)
4
CRC (cyclic redundancy check) unit
Yes
JTAG controller
Yes
Nexus port controller (NPC)
Supply
Yes (Level 2+)
Digital power supply
3.3 V or 5 V single supply with external transistor
Analog power supply
3.3 V or 5 V
Internal RC oscillator
16 MHz
External crystal oscillator
Packages
Temperature
4–40 MHz
100 LQFP
144 LQFP
Standard ambient temperature
–40 to 125 °C
1
32 message buffers, selectable single or dual channel support
Each FlexCAN module has 32 message buffers.
3 One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.
4 Four channels shared between the two ADCs
2
1.4
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604P MCU.
MPC5604P Microcontroller Data Sheet, Rev. 8
4
Freescale
External ballast
e200z0 Core
1.2 V regulator
control
32-bit
general
purpose
registers
XOSC
Integer
execution
unit
16 MHz
RC oscillator
FMPLL_0
(System)
Special
purpose
registers
Exception
handler
Instruction
unit
Variable
length
encoded
instructions
Branch
prediction
unit
Load/store
unit
FMPLL_1
(FlexRay, MotCtrl)
JTAG
Nexus port
controller
Interrupt
controller
Nexus 2+
eDMA
16 channels
Instruction
32-bit
Master
FlexRay
Data
32-bit
Master
Master
Crossbar switch (XBAR, AMBA 2.0 v6 AHB)
ECSM
SIUL
BAM
MC_ME
MC_CGM
MC_RGM
SWT
STM
SRAM
(with ECC)
CRC
Data Flash
(with ECC)
WKPU
Code Flash
(with ECC)
Slave
PIT
Slave
Slave
FCU
Safety port
FlexCAN
2×
LINFlex
4×
DSPI
2×
eTimer (6 ch)
SSCM
Channels
0–10
10-bit
ADC_1
Shared
channels
11–14
10-bit
ADC_0
Channels
0–10
1.2 V Rail VREG
CTU
FlexPWM
Peripheral bridge
Legend:
ADC
BAM
CRC
CTU
DSPI
ECSM
eDMA
eTimer
FCU
Flash
FlexCAN
FlexPWM
FMPLL
INTC
JTAG
Analog-to-digital converter
Boot assist module
Cyclic redundancy check
Cross triggering unit
Deserial serial peripheral interface
Error correction status module
Enhanced direct memory access
Enhanced timer
Fault collection unit
Flash memory
Controller area network
Flexible pulse width modulation
Frequency-modulated phase-locked loop
Interrupt controller
JTAG controller
LINFlex
MC_CGM
MC_ME
MC_PCU
MC_RGM
PIT
SIUL
SRAM
SSCM
STM
SWT
WKPU
XOSC
XBAR
Serial communication interface (LIN support)
Clock generation module
Mode entry module
Power control unit
Reset generation module
Periodic interrupt timer
System integration unit Lite
Static random-access memory
System status and configuration module
System timer module
Software watchdog timer
Wakeup unit
External oscillator
Crossbar switch
Figure 1. MPC5604P block diagram
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
5
Table 2. MPC5604P series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM)
Block of read-only memory containing VLE code which is executed according to
the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Controller area network (FlexCAN) Supports the standard CAN communications protocol
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width
Cyclic redundancy check (CRC)
CRC checksum generator
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels
Enhanced timer (eTimer)
Provides enhanced programmable up/down modulo counting
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
External oscillator (XOSC)
Provides an output clock used as input reference for FMPLL_0 or as reference
clock for specific modules depending on system needs
Fault collection unit (FCU)
Provides functional safety to the device
Flash memory
Provides non-volatile storage for program code, constants and variables
Frequency-modulated
phase-locked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with minimum load on CPU
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Peripheral bridge (PBRIDGE)
Interface between the system bus and on-chip peripherals
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
MPC5604P Microcontroller Data Sheet, Rev. 8
6
Freescale
Table 2. MPC5604P series block summary (continued)
Block
Function
Pulse width modulator (FlexPWM) Contains four PWM submodules, each of which is capable of controlling a single
half-bridge power stage and two fault input channels
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR1 and operating
system tasks
System watchdog timer (SWT)
Provides protection from runaway code
Wakeup unit (WKPU)
Supports up to 18 external sources that can generate interrupts or wakeup
events, 1 of which can cause non-maskable interrupt requests or wakeup events
1
AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)
1.5
Feature details
1.5.1
High performance e200z0 core processor
The e200z0 Power Architecture core provides the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
High performance e200z0 core processor for managing peripherals and interrupts
Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
Harvard architecture
Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
— Results in smaller code size footprint
— Minimizes impact on performance
Branch processing acceleration using lookahead instruction buffer
Load/store unit
— 1 cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
Thirty-two 32-bit general purpose registers (GPRs)
Separate instruction bus and load/store bus Harvard architecture
Hardware vectored interrupt support
Reservation instructions for implementing read-modify-write constructs
Long cycle time instructions, except for guarded loads, do not increase interrupt latency
Extensive system development support through Nexus debug port
Non-maskable interrupt support
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
7
1.5.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus width and a 32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
port, arbitration logic will select the higher priority master and grant it ownership of the slave port. All other masters requesting
that slave port will be stalled until the higher priority master completes its transactions. Requesting masters will be treated with
equal priority and will be granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted
access.
The crossbar provides the following features:
•
•
•
•
•
1.5.3
4 master ports:
— e200z0 core complex Instruction port
— e200z0 core complex Load/Store Data port
— eDMA
— FlexRay
3 slave ports:
— Flash memory (code flash and data flash)
— SRAM
— Peripheral bridge
32-bit internal address, 32-bit internal data paths
Fixed Priority Arbitration based on Port Master
Temporary dynamic priority elevation of masters
Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is utilized to minimize the overall block size.
The eDMA module provides the following features:
•
•
•
•
•
•
•
•
1.5.4
16 channels support independent 8, 16 or 32-bit single value or block transfers
Supports variable sized queues and circular queues
Source and destination address registers are independently configured to either post-increment or to remain constant
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
transfer
DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer and CTU
Programmable DMA channel multiplexer for assignment of any DMA source to any available DMA channel with as
many as 30 request sources
eDMA abort operation through software
Flash memory
The MPC5604P provides as much as 576 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM)
can be used for instruction and/or data storage. The flash memory module interfaces the system bus to a dedicated flash memory
MPC5604P Microcontroller Data Sheet, Rev. 8
8
Freescale
array controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit wide prefetch buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory
array accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states.
The flash memory module provides the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
As much as 576 KB flash memory
— 8 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 3×128 KB) code flash
— 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash
— Full Read While Write (RWW) capability between code and data flash
Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to
prefetch code or data or both)
Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page buffer miss at 64 MHz
Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
Hardware and software configurable read and write access protections on a per-master basis
Configurable access timing allowing use in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (up to 31 additional cycles) allowing use for
emulation of other memory types.
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page sizes
— Code flash memory: 128 bits (4 words)
— Data flash memory: 32 bits (1 word)
ECC with single-bit correction, double-bit detection for data integrity
— Code flash memory: 64-bit ECC
— Data flash memory: 64-bit ECC
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Censorship protection scheme to prevent flash memory content visibility
Hardware support for EEPROM emulation
1.5.5
Static random access memory (SRAM)
The MPC5604P SRAM module provides up to 40 KB of general-purpose memory.
ECC handling is done on a 32-bit boundary and is completely software compatible with MPC55xx family devices with an
e200z6 core and 64-bit wide ECC.
The SRAM module provides the following features:
•
•
•
•
Supports read/write accesses mapped to the SRAM from any master
Up to 40 KB general purpose SRAM
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back
with a read to same memory block
1.5.6
Interrupt controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems. The INTC handles 147 selectable-priority interrupt sources.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
9
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR has to be executed. It also provides a wide number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol (PCP) for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so
that all tasks which share the same resource can not preempt each other.
The INTC provides the following features:
•
•
•
•
•
1.5.7
Unique 9-bit vector for each separate interrupt source
8 software triggerable interrupt sources
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Ability to modify the ISR or task priority: modifying the priority can be used to implement the Priority Ceiling Protocol
for accessing shared resources.
2 external high priority interrupts directly accessing the main core and I/O processor (IOP) critical interrupt mechanism
System status and configuration module (SSCM)
The system status and configuration module (SSCM) provides central device functionality.
The SSCM includes these features:
•
•
•
1.5.8
System configuration and status
— Memory sizes/status
— Device mode and security status
— Determine boot vector
— Search code flash for bootable sector
— DMA status
Debug status port enable and selection
Bus and peripheral abort enable/disable
System clocks and clock generation
The following list summarizes the system clock and clock generation on the MPC5604P:
•
•
•
•
•
•
1.5.9
Lock detect circuitry continuously monitors lock status
Loss of clock (LOC) detection for PLL outputs
Programmable output clock divider (1, 2, 4, 8)
FlexPWM module and eTimer module can run on an independent clock source
On-chip oscillator with automatic level control
Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by user application
Frequency-modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further, the FMPLL supports
programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all
software configurable.
The PLL has the following major features:
•
Input clock frequency: 4–40 MHz
MPC5604P Microcontroller Data Sheet, Rev. 8
10
Freescale
•
•
•
•
•
•
Maximum output frequency: 64 MHz
Voltage controlled oscillator (VCO)—frequency 256–512 MHz
Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
Frequency-modulated PLL
— Modulation enabled/disabled through software
— Triangle wave modulation
Programmable modulation depth (±0.25% to ±4% deviation from center frequency): programmable modulation
frequency dependent on reference frequency
Self-clocked mode (SCM) operation
1.5.10
Main oscillator
The main oscillator provides these features:
•
•
•
Input frequency range: 4–40 MHz
Crystal input mode or oscillator input mode
PLL reference
1.5.11
Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a capacitor. The voltage
at the capacitor is compared by the stable bandgap reference voltage.
The RC oscillator provides these features:
•
•
•
•
Nominal frequency 16 MHz
±5% variation over voltage and temperature after process trim
Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the
PLL
RC oscillator is used as the default system clock during startup
1.5.12
Periodic interrupt timer (PIT)
The PIT module implements these features:
•
•
•
•
4 general purpose interrupt timers
32-bit counter resolution
Clocked by system clock frequency
Each channel can be used as trigger for a DMA request
1.5.13
System timer module (STM)
The STM module implements these features:
•
•
•
•
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
1.5.14
Software watchdog timer (SWT)
The SWT has the following features:
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
11
•
•
•
•
•
•
•
32-bit time-out register to set the time-out period
Programmable selection of system or oscillator clock for timer operation
Programmable selection of window mode or regular servicing
Programmable selection of reset or interrupt on an initial time-out
Master access protection
Hard and soft configuration lock bits
Reset configuration inputs allow timer to be enabled out of reset
1.5.15
Fault collection unit (FCU)
The FCU provides an independent fault reporting mechanism even if the CPU is malfunctioning.
The FCU module has the following features:
•
•
•
•
•
FCU status register reporting the device status
Continuous monitoring of critical fault signals
User selection of critical signals from different fault sources inside the device
Critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device
and/or other circuitry (for example, safety relay or FlexRay transceiver)
Faults are latched into a register
1.5.16
System integration unit – Lite (SIUL)
The MPC5604P SIUL controls MCU pad configuration, external interrupt, general purpose I/O (GPIO), and internal peripheral
multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and
discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
•
•
•
•
•
•
•
Centralized general purpose input output (GPIO) control of as many as 80 input/output pins and 26 analog input-only
pads (package dependent)
All GPIO pins can be independently configured to support pull-up, pull down, or no pull
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
All peripheral pins (except ADC channels) can be alternatively configured as both general purpose input or output pins
ADC channels support alternative configuration as general purpose inputs
Direct readback of the pin value is supported on all pins through the SIUL
Configurable digital input filter that can be applied to some general purpose input pins for noise elimination: as many
as 4 internal functions can be multiplexed onto 1 pin
1.5.17
Boot and censorship
Different booting modes are available in the MPC5604P: booting from internal flash memory and booting via a serial link.
The default booting scheme uses the internal flash memory (an internal pull-down is used to select this mode). Optionally, the
user can boot via FlexCAN or LINFlex (using the boot assist module software).
A censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile memory.
MPC5604P Microcontroller Data Sheet, Rev. 8
12
Freescale
1.5.17.1
Boot assist module (BAM)
The BAM is a block of read-only one-time programmed memory and is identical for all MPC560xP devices that are based on
the e200z0h core. The BAM program is executed every time the device is powered on if the alternate boot mode has been
selected by the user.
The BAM provides the following features:
•
•
Serial bootloading via FlexCAN or LINFlex
Ability to accept a password via the used serial communication channel to grant the legitimate user access to the
non-volatile memory
1.5.18
Error correction status module (ECSM)
The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform
configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,
and information on platform memory errors reported by error-correcting codes and/or generic access error information for
certain processor cores.
The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes
these features:
•
•
Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented
For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the
MPC5604P.
The sources of the ECC errors are:
•
•
Flash memory
SRAM
1.5.19
Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
•
•
•
•
•
Duplicated periphery
Master access privilege level per peripheral (per master: read access enable; write access enable)
Write buffering for peripherals
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
1.5.20
Controller area network (FlexCAN)
The MPC5604P MCU contains one controller area network (FlexCAN) module. This module is a communication controller
implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in
the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module contains 32 message
buffers.
The FlexCAN module provides the following features:
•
Full implementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— Up to 8-bytes data length
— Programmable bit rate up to 1 Mbit/s
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
13
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32 message buffers of up to 8-bytes data length
Each message buffer configurable as Rx or Tx, all supporting standard and extended messages
Programmable loop-back mode supporting self-test operation
3 programmable mask registers
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
Receive features
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a six-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
Programmable clock source
— System clock
— Direct oscillator clock to avoid PLL jitter
1.5.21
Safety port (FlexCAN)
The MPC5604P MCU has a second CAN controller synthesized to run at high bit rates to be used as a safety port. The CAN
module of the safety port provides the following features:
•
•
•
•
Identical to the FlexCAN module
Bit rate as fast as 7.5 Mbit/s at 60 MHz CPU clock using direct connection between CAN modules (no physical
transceiver required)
32 message buffers of up to 8 bytes data length
Can be used as a second independent CAN module
1.5.22
FlexRay
The FlexRay module provides the following features:
•
•
•
•
•
•
•
Full implementation of FlexRay Protocol Specification 2.1
32 configurable message buffers can be handled
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
Message buffers configurable as Tx, Rx or RxFIFO
Message buffer size configurable
Message filtering for all message buffers based on FrameID, cycle count and message ID
Programmable acceptance filters for RxFIFO message buffers
MPC5604P Microcontroller Data Sheet, Rev. 8
14
Freescale
1.5.23
Serial communication interface module (LINFlex)
The LINFlex (local interconnect network flexible) on the MPC5604P features the following:
•
•
•
•
•
•
Supports LIN Master mode, LIN Slave mode and UART mode
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
Handles LIN frame transmission and reception without CPU intervention
LIN features
— Autonomous LIN frame handling
— Message buffer to store Identifier and as much as 8 data bytes
— Supports message length as long as 64 bytes
— Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing, checksum, and time-out)
— Classic or extended checksum calculation
— Configurable Break duration as long as 36-bit times
— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
— Interrupt-driven operation with 16 interrupt sources
LIN slave mode features
— Autonomous LIN header handling
— Autonomous LIN response handling
UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
— Parity, Noise and Framing errors
— Interrupt-driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— 2 receiver wake-up methods
1.5.24
Deserial serial peripheral interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for communication between the
MPC5604P MCU and external devices.
The DSPI modules provide these features:
•
•
•
•
•
•
•
•
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
Up to 20 chip select lines available
— 8 on DSPI_0
— 4 each on DSPI_1, DSPI_2 and DSPI_3
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
15
•
•
•
•
•
8 clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for deglitching
FIFOs for buffering as many as 5 transfers on the transmit and receive side
Queueing operation possible through use of the eDMA
General purpose I/O functionality on pins when not used for SPI
1.5.25
Pulse width modulator (FlexPWM)
The pulse width modulator module (PWM) contains four PWM submodules, each capable of controlling a single half-bridge
power stage. There are also four fault channels.
This PWM is capable of controlling most motor types: AC induction motors (ACIM), permanent magnet AC motors (PMAC),
both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper
motors.
The FlexPWM block implements the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit resolution for center, edge-aligned, and asymmetrical PWMs
Maximum operating clock frequency of 120 MHz
PWM outputs can operate as complementary pairs or independent channels
Can accept signed numbers for PWM generation
Independent control of both edges of each PWM output
Synchronization to external hardware or other PWM supported
Double buffered PWM registers
— Integral reload rates from 1 to 16
— Half cycle reload capability
Multiple ADC trigger events can be generated per PWM cycle via hardware
Write protection for critical registers
Fault inputs can be assigned to control multiple PWM outputs
Programmable filters for fault inputs
Independently programmable PWM output polarity
Independent top and bottom deadtime insertion
Each complementary pair can operate with its own PWM frequency and deadtime values
Individual software-control for each PWM output
All outputs can be programmed to change simultaneously via a “Force Out” event
PWMX pin can optionally output a third PWM signal from each submodule
Channels not used for PWM generation can be used for buffered output compare functions
Channels not used for PWM generation can be used for input capture functions
Enhanced dual-edge capture functionality
eDMA support with automatic reload
2 fault inputs
Capture capability for PWMA, PWMB, and PWMX channels not supported
1.5.26
eTimer
The MPC5604P includes two eTimer modules. Each module provides six 16-bit general purpose up/down timer/counter units
with the following features:
•
•
Maximum operating clock frequency of 120 MHz
Individual channel capability
MPC5604P Microcontroller Data Sheet, Rev. 8
16
Freescale
•
•
•
•
•
•
•
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
— External event counting: max. count rate = peripheral clock/2
— Internal clock counting: max. count rate = peripheral clock
Counters are:
— Cascadable
— Preloadable
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Pins available as GPIO when timer functionality not in use
1.5.27
Analog-to-digital converter (ADC) module
The ADC module provides the following features:
Analog part:
•
2 on-chip AD converters
— 10-bit AD resolution
— 1 sample and hold unit per ADC
— Conversion time, including sampling time, less than 1 µs (at full precision)
— Typical sampling time is 150 ns min. (at full precision)
— Differential non-linearity error (DNL) ±1 LSB
— Integral non-linearity error (INL) ±1.5 LSB
— TUE
2.7 V
VSS_HV_ADC0 SR ADC_0 ground and low reference
voltage with respect to ground (VSS)
—
VDD_HV_ADC14 SR 3.3 V / 5.0 V ADC_0 supply and high VDD_HV_REG <
reference voltage with respect to
2.7 V
ground (VSS)
VDD_HV_REG >
2.7 V
VIN
–0.3
VDD_HV_REG +
0.3
V
6.0
–0.1
0.1
V
–0.3
VDD_HV_REG +
0.3
V
6.0
—
–0.1
0.1
V
SR Slope characteristics on all VDD
during power up5 with respect to
ground (VSS)
—
3.0
500 x 103
(0.5 [V/µs])
V/s
SR Voltage on any pin with respect to
ground (VSS_HV_IOx) with respect to
ground (VSS)
—
–0.3
6.0
V
VSS_HV_ADC1 SR ADC_1 ground and low reference
voltage with respect to ground (VSS)
TVDD
VDD_HV_IOx + 0.3
Relative to
VDD_HV_IOx
Relative to
VDD_HV_IOx
VDD_HV_IOx + 0.
3
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
39
Table 7. Absolute maximum ratings1 (continued)
Value
Symbol
Parameter
Conditions
Min
VINAN0
VINAN1
3
4
5
6
7
SR ADC1 analog input voltage7
VDD_HV_REG > VSS_HV_ADV0 VDD_HV_ADV0 +
2.7 V
0.3
0.3
V
VDD_HV_REG <
2.7 V
V
VSS_HV_ADV0
VDD_HV_ADV0
VDD_HV_REG > VSS_HV_ADV1 VDD_HV_ADV1 +
2.7 V
0.3
0.3
V
VDD_HV_REG <
2.7 V
VSS_HV_ADV1
VDD_HV_ADV1
V
SR Injected input current on any pin
during overload condition
—
–10
10
mA
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
–50
50
mA
IVDD_LV
SR Low voltage static current sink
through VDD_LV
—
—
155
mA
SR Storage temperature
—
–55
150
°C
SR Junction temperature under bias
—
–40
150
°C
TJ
2
ADC0 and shared ADC0/1 analog
input voltage6
Unit
IINJPAD
TSTG
1
SR
Max2
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device
stress have not yet been determined.
The difference between each couple of voltage supplies must be less than 300 mV,
|VDD_HV_IOy – VDD_HV_IOx | < 300 mV.
The difference between ADC voltage supplies must be less than 100 mV, |VDD_HV_ADC1 – VDD_HV_ADC0| < 100 mV.
Guaranteed by device validation
Not allowed to refer this voltage to VDD_HV_ADV1, VSS_HV_ADV1
Not allowed to refer this voltage to VDD_HV_ADV0, VSS_HV_ADV0
Figure 4 shows the constraints of the different power supplies.
MPC5604P Microcontroller Data Sheet, Rev. 8
40
Freescale
VDD_HV_xxx
6.0 V
VDD_HV_IOx
–0.3 V
–0.3 V
6.0 V
Figure 4. Power supplies constraints (–0.3 V VDD_HV_IOx 6.0 V)
The MPC5604P supply architecture allows of having ADC supply managed independently from standard VDD_HV supply.
Figure 5 shows the constraints of the ADC power supply.
VDD_HV_ADCx
6.0 V
VDD_HV_REG
–0.3 V
–0.3 V
2.7 V
6.0 V
Figure 5. Independent ADC supply (–0.3 V VDD_HV_REG 6.0 V)
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
41
3.4
Recommended operating conditions
Table 8. Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Min
Max1
Unit
SR Device ground
—
0
0
V
VDD_HV_IOx2
SR 5.0 V input/output supply
voltage
—
4.5
5.5
V
VSS_HV_IOx
SR Input/output ground voltage
—
0
0
V
VDD_HV_FL
SR 5.0 V code and data flash
supply voltage
—
4.5
5.5
V
VSS
VSS_HV_FL
VDD_HV_OSC
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
SR Code and data flash ground
—
0
0
V
SR 5.0 V crystal oscillator amplifier
supply voltage
—
4.5
5.5
V
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
VSS_HV_OSC
SR 5.0 V crystal oscillator amplifier
reference voltage
—
0
0
V
VDD_HV_REG
SR 5.0 V voltage regulator supply
voltage
—
4.5
5.5
V
VDD_HV_ADC03
SR 5.0 V ADC_0 supply and high
reference voltage
Relative to
VDD_HV_IOx
—
Relative to
VDD_HV_REG
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
4.5
5.5
VDD_HV_REG – 0.1
—
V
VSS_HV_ADC0
SR ADC_0 ground and low
reference voltage
—
0
0
V
VDD_HV_ADC13
SR 5.0 V ADC_1 supply and high
reference voltage
—
4.5
5.5
V
VDD_HV_REG – 0.1
—
—
0
0
V
—
—
—
V
—
0
0
V
CC Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
SR Ambient temperature under
bias
—
–40
125
°C
VSS_HV_ADC1
SR ADC_1 ground and low
reference voltage
VDD_LV_REGCOR4,5 CC Internal supply voltage
VSS_LV_REGCOR4 SR Internal reference voltage
VDD_LV_CORx
4,5
VSS_LV_CORx4
TA
Relative to
VDD_HV_REG
1
Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full
functionality. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
2 The difference between each couple of voltage supplies must be less than 100 mV, |V
DD_HV_IOy – VDD_HV_IOx | <
100 mV.
3
The difference between ADC voltage supplies must be less than 100 mV, |VDD_HV_ADC1 VDD_HV_ADC0| < 100 mV.
MPC5604P Microcontroller Data Sheet, Rev. 8
42
Freescale
4
To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced
by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must
be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected
to the external ballast emitter.
5
The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the
low voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 9. Recommended operating conditions (3.3 V)
Value
Symbol
VSS
Parameter
Conditions
Min
Max1
Unit
SR Device ground
—
0
0
V
SR 3.3 V input/output supply
voltage
—
3.0
3.6
V
VSS_HV_IOx
SR Input/output ground voltage
—
0
0
V
VDD_HV_FL
SR 3.3 V code and data flash
supply voltage
—
3.0
3.6
V
VDD_HV_IOx
2
VSS_HV_FL
VDD_HV_OSC
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
SR Code and data flash ground
—
0
0
V
SR 3.3 V crystal oscillator amplifier
supply voltage
—
3.0
3.6
V
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
VSS_HV_OSC
SR 3.3 V crystal oscillator amplifier
reference voltage
—
0
0
V
VDD_HV_REG
SR 3.3 V voltage regulator supply
voltage
—
3.0
3.6
V
VDD_HV_ADC03
SR 3.3 V ADC_0 supply and high
reference voltage
Relative to
VDD_HV_IOx
—
Relative to
VDD_HV_REG
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
3.0
5.5
VDD_HV_REG – 0.1
5.5
V
VSS_HV_ADC0
SR ADC_0 ground and low
reference voltage
—
0
0
V
VDD_HV_ADC13
SR 3.3 V ADC_1 supply and high
reference voltage
—
3.0
5.5
V
VDD_HV_REG – 0.1
5.5
—
0
0
V
—
—
—
V
VSS_HV_ADC1
SR ADC_1 ground and low
reference voltage
VDD_LV_REGCOR4,5 CC Internal supply voltage
Relative to
VDD_HV_REG
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
43
Table 9. Recommended operating conditions (3.3 V) (continued)
Value
Symbol
Parameter
VDD_LV_CORx
VSS_LV_CORx4
TA
1
2
3
4
5
Unit
Min
Max1
—
0
0
V
CC Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
SR Ambient temperature under
bias
—
–40
125
°C
VSS_LV_REGCOR4 SR Internal reference voltage
4,5
Conditions
Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full
functionality. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | <
100 mV.
The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_ADC1 – VDD_HV_ADC0|
< 100 mV. As long as that condition is met, ADC_0 and ADC_1 can be operated at 5 V with the rest of the device
operating at 3.3 V.
To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced
by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must
be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected
to the external ballast emitter.
The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the
low voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
MPC5604P Microcontroller Data Sheet, Rev. 8
44
Freescale
Figure 6 shows the constraints of the different power supplies.
VDD_HV_xxx
5.5 V
3.3 V
3.0 V
VDD_HV_IOx
3.0 V
5.5 V
3.3 V
Note: IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when
PAD3V5V is low, and in the range of 4.5–5.5 V when PAD3V5V is high.
Figure 6. Power supplies constraints (3.0 V VDD_HV_IOx 5.5 V)
The MPC5604P supply architecture allows the ADC supply to be managed independently from the standard VDD_HV supply.
Figure 7 shows the constraints of the ADC power supply.
VDD_HV_ADCx
5.5 V
3.0 V
VDD_HV_REG
3.0 V
5.5 V
Figure 7. Independent ADC supply (3.0 V VDD_HV_REG 5.5 V)
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
45
3.5
Thermal characteristics
3.5.1
Package thermal characteristics
Table 10. Thermal characteristics for 144-pin LQFP
Symbol
RJA
RJB
Parameter
Conditions
Thermal resistance junction-to-ambient,
natural convection1
2
Thermal resistance junction-to-board
Typical value Unit
Single layer board—1s
54.2
°C/W
Four layer board—2s2p
44.4
°C/W
Four layer board—2s2p
29.9
°C/W
9.3
°C/W
Operating conditions
30.2
°C/W
Operating conditions
0.8
°C/W
RJCtop Thermal resistance junction-to-case (top)3 Single layer board—1s
JB
JC
1
2
3
4
5
Junction-to-board, natural convection4
Junction-to-case, natural
convection5
Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board
meets JEDEC specification for this package.
Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets
JEDEC specification for the specified package.
Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold
plate temperature is used for the case temperature. Reported value includes the thermal resistance
of the interface layer.
Thermal characterization parameter indicating the temperature difference between the board and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JB.
Thermal characterization parameter indicating the temperature difference between the case and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JC.
Table 11. Thermal characteristics for 100-pin LQFP
Symbol
RJA
RJB
Parameter
JC
Typical value Unit
Thermal resistance junction-to-ambient,
natural convection1
Single layer board—1s
47.3
°C/W
Four layer board—2s2p
35.3
°C/W
Thermal resistance junction-to-board2
Four layer board—2s2p
19.1
°C/W
Single layer board—1s
9.7
°C/W
Operating conditions
19.1
°C/W
Operating conditions
0.8
°C/W
RJCtop Thermal resistance junction-to-case
JB
Conditions
Junction-to-board, natural
Junction-to-case, natural
(top)3
convection4
convection5
1
Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board
meets JEDEC specification for this package.
2 Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets
JEDEC specification for the specified package.
3 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold
plate temperature is used for the case temperature. Reported value includes the thermal resistance
of the interface layer.
4
Thermal characterization parameter indicating the temperature difference between the board and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JB.
MPC5604P Microcontroller Data Sheet, Rev. 8
46
Freescale
5
3.5.2
Thermal characterization parameter indicating the temperature difference between the case and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JC.
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
TJ = TA + (RJA * PD)
Eqn. 1
where:
= ambient temperature for the package (°C)
TA
RJA
= junction to ambient thermal resistance (°C/W)
PD
= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
RJA = RJC + RCA
Eqn. 2
where:
= junction to ambient thermal resistance (°C/W)
RJA
RJC
= junction to case thermal resistance (°C/W)
RCA = case to ambient thermal resistance (°C/W)
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using Equation 3:
TJ = TT + (JT x PD)
Eqn. 3
where:
= thermocouple temperature on top of the package (°C)
TT
JT
= thermal characterization parameter (°C/W)
PD
= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
47
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
U.S.A.
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1.
2.
3.
3.6
C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller
Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic
Packaging and Production, pp. 53–58, March 1998.
B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in
Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
Electromagnetic interference (EMI) characteristics
Table 12. EMI testing specifications
Symbol
VEME
3.7
Parameter
Conditions
Clocks
Level
Unit
(Max)
Frequency
150 kHz–150 MHz
Radiated emissions Device configuration, test
fOSC 8 MHz
conditions and EM testing per fCPU 64 MHz
150–1000 MHz
No PLL frequency
standard IEC61967-2
modulation
IEC Level
Supply voltage = 5 V DC
150 kHz–150 MHz
Ambient temperature = 25 °C fOSC 8 MHz
fCPU 64 MHz
Worst-case orientation
150–1000 MHz
1% PLL frequency
modulation
IEC Level
16
dBµV
15
M
—
15
dBµV
14
M
—
Electrostatic discharge (ESD) characteristics
Table 13. ESD ratings1,2
Symbol
Parameter
Conditions
Value
Unit
VESD(HBM)
SR Electrostatic discharge (Human Body Model)
—
2000
V
VESD(CDM)
SR Electrostatic discharge (Charged Device Model)
—
750 (corners)
V
500 (other)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
MPC5604P Microcontroller Data Sheet, Rev. 8
48
Freescale
3.8
3.8.1
Power management electrical characteristics
Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN ballast to be connected as shown in Figure 8. Table 14 contains all
approved NPN ballast components. Capacitances should be placed on the board as near as possible to the associated pins. Care
should also be taken to limit the serial inductance of the VDD_HV_REG, BCTRL and VDD_LV_CORx pins to less than LReg, see
Table 15.
NOTE
The voltage regulator output cannot be used to drive external circuits. Output pins are used
only for decoupling capacitances.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is
not possible to provide VDD_LV_COR through external regulator.
For the MPC5604P microcontroller, capacitors, with total values not below CDEC1, should be placed between
VDD_LV_CORx/VSS_LV_CORx close to external ballast transistor emitter. 4 capacitors, with total values not below CDEC2, should
be placed close to microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the
VDD_LV_REGCOR/VSS_LV_REGCOR pair . Additionally, capacitors with total values not below CDEC3, should be placed between
the VDD_HV_REG/VSS_HV_REG pins close to ballast collector. Capacitors values have to take into account capacitor accuracy,
aging and variation versus temperature.
All reported information are valid for voltage and temperature ranges described in recommended operating condition, Table 8
and Table 9.
VDD_HV_REG
CDEC3
MPC5604P
BJT(1)
BCTRL
RB
VDD_LV_COR
CDEC2
1
CDEC1
Refer to Table 14.
Figure 8. Configuration with resistor on base
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
49
Table 14. Approved NPN ballast components (configuration with resistor on base)
Part
Manufacturer
Approved derivatives1
BCP68
ON Semi
BCP68
NXP
BCP68-25
Infineon
BCP68-25
BCX68
Infineon
BCX68-10;BCX68-16;BCX68-25
BC868
NXP
BC868
BC817
Infineon
BC817-16;BC817-25;BC817SU;
NXP
BC817-16;BC817-25
ST
BCP56-16
Infineon
BCP56-10;BCP56-16
ON Semi
BCP56-10
NXP
BCP56-10;BCP56-16
BCP56
1
For automotive applications please check with the appropriate transistor vendor for automotive grade
certification
Table 15. Voltage regulator electrical characteristics (configuration with resistor on base)
Value
Symbol
C
Parameter
Conditions
Unit
Min
VDD_LV_REGCOR CC P Output voltage under maximum Post-trimming
load run supply current
configuration
RB
CDEC1
Typ Max
1.15
—
1.32
V
18
—
22
k
—
µF
SR — External resistance on bipolar
junction transistor (BJT) base
—
SR — External decoupling/stability
ceramic capacitor
BJT from Table 14. 3
19.5
capacitances (i.e. X7R or X8R
capacitors) with nominal value
of 10 µF
30
BJT BC817, one capacitance
of 22 µF
22
14.3
µF
MPC5604P Microcontroller Data Sheet, Rev. 8
50
Freescale
Table 15. Voltage regulator electrical characteristics (configuration with resistor on base) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
RREG
SR — Resulting ESR of all three
capacitors of CDEC1
Resulting ESR of the unique
capacitor CDEC1
Typ Max
BJT from Table 14. 3x10 µF.
Absolute maximum value
between 100 kHz and 10 MHz
—
—
50
m
BJT BC817, 1x 22 µF.
Absolute maximum value
between 100 kHz and 10 MHz
10
—
40
m
CDEC2
SR — External decoupling/stability
ceramic capacitor
4 capacitances (i.e. X7R or
1200 1760
X8R capacitors) with nominal
value of 440 nF
—
nF
CDEC3
SR — External decoupling/stability
ceramic capacitor on
VDD_HV_REG
3 capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF; CDEC3 has to
be equal or greater than
CDEC1
LReg
SR — Resulting ESL of VDD_HV_REG, —
BCTRL and VDD_LV_CORx pins
19.5
30
—
µF
—
—
15
nH
VDD_HV_REG
CDEC3
MPC5604P
BCP56,
BCP68,
BCX68,
BC817
BCTRL
VDD_LV_COR
CDEC2
CDEC1
Figure 9. Configuration without resistor on base
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
51
Table 16. Voltage regulator electrical characteristics (configuration without resistor on base)
Value
Symbol
C
Parameter
Conditions
Unit
Min
VDD_LV_REGCOR CC P Output voltage under maximum Post-trimming
load run supply current
configuration
3.8.2
1.15
1.32
V
—
CDEC1
SR — External decoupling/stability
ceramic capacitor
RREG
SR — Resulting ESR of all four CDEC1 Absolute maximum value
between 100 kHz and 10 MHz
CDEC2
SR — External decoupling/stability
ceramic capacitor
CDEC3
SR — External decoupling/stability
ceramic capacitor on
VDD_HV_REG
LReg
Typ Max
4 capacitances
4 capacitances of 100 nF each
40
56
—
—
—
45
400
—
—
40
—
—
—
—
15
µF
m
nF
µF
—
SR — Resulting ESL of VDD_HV_REG, —
BCTRL and VDD_LV_CORx pins
nH
Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization, as well as three low voltage
detectors to monitor the VDD and the VDD_LV voltage while device is supplied:
•
•
•
•
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range
LVDLVCOR monitors low voltage digital power domain
Table 17. Low voltage monitor electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Max
—
1.5
2.7
V
TA = 25 °C
1.0
—
V
VPORH
T
Power-on reset threshold
VPORUP
P
Supply for functional POR module
VREGLVDMOK_H
P
Regulator low voltage detector high threshold
—
—
2.95
V
VREGLVDMOK_L
P
Regulator low voltage detector low threshold
—
2.6
—
V
VFLLVDMOK_H
P
Flash low voltage detector high threshold
—
—
2.95
V
VFLLVDMOK_L
P
Flash low voltage detector low threshold
—
2.6
—
V
VIOLVDMOK_H
P
I/O low voltage detector high threshold
—
—
2.95
V
VIOLVDMOK_L
P
I/O low voltage detector low threshold
—
2.6
—
V
MPC5604P Microcontroller Data Sheet, Rev. 8
52
Freescale
Table 17. Low voltage monitor electrical characteristics (continued)
Symbol
1
C
Value
Conditions1
Parameter
Unit
Min
Max
VIOLVDM5OK_H
P
I/O 5V low voltage detector high threshold
—
—
4.4
V
VIOLVDM5OK_L
P
I/O 5V low voltage detector low threshold
—
3.8
—
V
VMLVDDOK_H
P
Digital supply low voltage detector high
—
—
1.145
V
VMLVDDOK_L
P
Digital supply low voltage detector low
—
1.08
—
V
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
3.9
Power up/down sequencing
To prevent an overstress event or a malfunction within and outside the device, the MPC5604P implements the following
sequence to ensure each module is started only when all conditions for switching it ON are available:
•
•
•
A POWER_ON module working on voltage regulator supply controls the correct start-up of the regulator. This is a
key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5V. Associated
POWER_ON (or POR) signal is active low.
Several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage
regulator, I/Os, flash memory and low voltage domain). LVDs are gated low when POWER_ON is active.
A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active
high and released to all modules including I/Os, flash memory and RC16 oscillator needed during power-up phase and
reset phase. When POWER_OK is low the associated module are set into a safe state.
VPORH
VDD_HV_REG
VLVDHV3H
3.3V
VPOR_UP
0V
3.3V
POWER_ON
0V
3.3V
LVDM (HV)
0V
VMLVDOK_H
VDD_LV_REGCOR
1.2V
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
Internal Reset Generation Module
FSM
1.2V
0V
~1us
P0
P1
1.2V
0V
Figure 10. Power-up typical sequence
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
53
VLVDHV3L
VDD_HV_REG
3.3V
VPORH
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
Internal Reset Generation Module
FSM
IDLE
1.2V
0V
P0
Figure 11. Power-down typical sequence
VLVDHV3L
VLVDHV3H
3.3V
VDD_HV_REG
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
IDLE
P0
P1
1.2V
0V
Figure 12. Brown-out typical sequence
MPC5604P Microcontroller Data Sheet, Rev. 8
54
Freescale
3.10
DC electrical characteristics
3.10.1
NVUSRO register
Portions of the device configuration, such as high voltage supply, and watchdog enable/disable after reset are controlled via bit
values in the non-volatile user options (NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference manual.
3.10.1.1
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 18 shows how NVUSRO[PAD3V5V]
controls the device configuration.
Table 18. PAD3V5V field description
Value1
1
3.10.2
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
Default manufacturing value before flash initialization is ‘1’ (3.3 V).
DC electrical characteristics (5 V)
Table 19 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V, NVUSRO[PAD3V5V] = 0); see Figure 13.
Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)
Value
Symbol C
VIL
VIH
Parameter
Conditions
Unit
Min
Max
D Low level input voltage
—
–0.11
—
V
P
—
—
0.35 VDD_HV_IOx
V
P High level input voltage
—
0.65 VDD_HV_IOx
—
V
VDD_HV_IOx +
0.11
V
D
—
—
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
V
VOL_S
P Slow, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_S
P Slow, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_M
P Medium, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_M
P Medium, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_F
P Fast, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_F
P Fast, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_SYM P Symmetric, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_SYM P Symmetric, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VIN = VIL
–130
—
µA
VIN = VIH
—
–10
IPU
P Equivalent pull-up current
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
55
Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) (continued)
Value
Symbol C
IPD
1
Parameter
Conditions
P Equivalent pull-down current
Unit
Min
Max
VIN = VIL
10
—
VIN = VIH
—
130
µA
IIL
P Input leakage current (all
bidirectional ports)
TA = –40 to 125 °C
–1
1
µA
IIL
P Input leakage current (all ADC
input-only ports)
TA = –40 to 125 °C
–0.5
0.5
µA
CIN
D Input capacitance
—
—
10
pF
IPU
D RESET, equivalent pull-up current
VIN = VIL
–130
—
VIN = VIH
—
–10
µA
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 7.
Table 20. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)
Value
Symbol
IDD_LV_CORx
C
Parameter
Max
40 MHz
62
77
64 MHz
71
88
40 MHz
45
56
64 MHz
52
65
VDD_LV_CORx
externally forced at 1.3 V
64 MHz
60
75
HALT mode4
VDD_LV_CORx
externally forced at 1.3 V
—
1.5
10
STOP mode5
VDD_LV_CORx
externally forced at 1.3 V
—
1
10
Flash during read
VDD_HV_FL at 5.0 V
—
10
12
Flash during erase operation on 1 VDD_HV_FL at 5.0 V
flash module
—
15
19
ADC_1
3.5
5
ADC_0
3
4
ADC_1
0.8
1
RUN—Maximum mode1
T
IDD_ADC
T
T
VDD_LV_CORx
externally forced at 1.3 V
mode2
RUN—Maximum mode
Supply current
P
Unit
Typ
RUN—Typical
IDD_FLASH
Conditions
3
ADC—Maximum mode1
ADC—Typical mode2
VDD_HV_ADC0 at 5.0 V
VDD_HV_ADC1 at 5.0 V
fADC = 16 MHz
ADC_0
IDD_OSC
T
Oscillator
VDD_OSC at 5.0 V
8 MHz
mA
0.005 0.006
2.6
3.2
1
Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O
supply current excluded.
2 Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.
MPC5604P Microcontroller Data Sheet, Rev. 8
56
Freescale
3
Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum
frequency, all peripherals enabled.
4
Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
5
STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories
OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
3.10.3
DC electrical characteristics (3.3 V)
Table 21 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V, NVUSRO[PAD3V5V] = 1); see
Figure 13.
Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)1
Value
Symbol C
VIL
VIH
Parameter
Conditions
Unit
Min
Max
D Low level input voltage
—
–0.12
—
V
P
—
—
0.35 VDD_HV_IOx
V
P High level input voltage
—
0.65 VDD_HV_IOx
—
V
VDD_HV_IOx +
0.12
V
D
—
—
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
V
VOL_S
P Slow, low level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_S
P Slow, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
VOL_M
P Medium, low level output voltage
IOL = 2 mA
—
0.5
V
VOH_M
P Medium, high level output voltage
IOH = –2 mA
VDD_HV_IOx – 0.8
—
V
VOL_F
P Fast, low level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_F
P Fast, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
VOL_SYM P Symmetric, low level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_SYM P Symmetric, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
VIN = VIL
–130
—
µA
VIN = VIH
—
–10
VIN = VIL
10
—
VIN = VIH
—
130
IPU
IPD
1
P Equivalent pull-up current
P Equivalent pull-down current
µA
IIL
P Input leakage current (all
bidirectional ports)
TA = –40 to 125 °C
—
1
µA
IIL
P Input leakage current (all ADC
input-only ports)
TA = –40 to 125 °C
—
0.5
µA
CIN
D Input capacitance
—
—
10
pF
IPU
D RESET, equivalent pull-up current
VIN = VIL
–130
—
VIN = VIH
—
–10
µA
These specifications are design targets and subject to change per device characterization.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
57
2
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 7.
Table 22. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)
Value
Symbol
C
Parameter
RUN—Maximum mode1
IDD_LV_CORx T
RUN—Typical
IDD_FLASH
IDD_ADC
T
T
Supply current
P
Conditions
VDD_LV_CORx
externally forced at 1.3 V
mode2
Unit
Typ
Max
40 MHz
62
77
64 MHz
71
89
40 MHz
45
56
64 MHz
53
66
RUN—Maximum mode3
VDD_LV_CORx
externally forced at 1.3 V
64 MHz
60
75
HALT mode4
VDD_LV_CORx
externally forced at 1.3 V
—
1.5
10
STOP mode5
VDD_LV_CORx
externally forced at 1.3 V
—
1
10
Flash during read on single mode
VDD_HV_FL at 3.3 V
—
8
10
Flash during erase operation on
single mode
VDD_HV_FL at 3.3 V
—
10
12
ADC—Maximum mode1
VDD_HV_ADC0 at 3.3 V
VDD_HV_ADC1 at 3.3 V
fADC = 16 MHz
ADC_1
2.5
4
ADC_0
2
4
ADC_1
0.8
1
ADC—Typical mode
2
mA
ADC_0 0.005 0.006
IDD_OSC
1
2
3
4
5
T
Oscillator
VDD_OSC at 3.3 V
8 MHz
2.4
3
Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O
supply current excluded.
Typical mode: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.
Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum
frequency, all peripherals enabled.
Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories
OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
3.10.4
Input DC electrical characteristics definition
Figure 13 shows the DC electrical characteristics behavior as function of time.
MPC5604P Microcontroller Data Sheet, Rev. 8
58
Freescale
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 13. Input DC electrical characteristics definition
3.10.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 23.
Table 23. I/O supply segment
Supply segment
Package
1
2
3
4
5
6
7
144
LQFP
pin8 – pin20 pin23 – pin38 pin39 – pin55 pin58 – pin68 pin73 – pin89 pin92 – pin125 pin128 – pin5
100
LQFP
pin15 – pin26 pin27 – pin38 pin41 – pin46 pin51 – pin61 pin64 – pin86 pin89 – pin10
—
Table 24 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below 100%.
Table 24. I/O weight
144 LQFP
100 LQFP
Pad
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
NMI
1%
1%
1%
1%
PAD[6]
6%
5%
14%
13%
PAD[49]
5%
4%
14%
12%
PAD[84]
14%
10%
—
—
PAD[85]
9%
7%
—
—
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
59
Table 24. I/O weight (continued)
144 LQFP
100 LQFP
Pad
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
PAD[86]
9%
6%
—
—
MODO[0]
12%
8%
—
—
PAD[7]
4%
4%
11%
10%
PAD[36]
5%
4%
11%
9%
PAD[8]
5%
4%
10%
9%
PAD[37]
5%
4%
10%
9%
PAD[5]
5%
4%
9%
8%
PAD[39]
5%
4%
9%
8%
PAD[35]
5%
4%
8%
7%
PAD[87]
12%
9%
—
—
PAD[88]
9%
6%
—
—
PAD[89]
10%
7%
—
—
PAD[90]
15%
11%
—
—
PAD[91]
6%
5%
—
—
PAD[57]
8%
7%
8%
7%
PAD[56]
13%
11%
13%
11%
PAD[53]
14%
12%
14%
12%
PAD[54]
15%
13%
15%
13%
PAD[55]
25%
22%
25%
22%
PAD[96]
27%
24%
—
—
PAD[65]
1%
1%
1%
1%
PAD[67]
1%
1%
—
—
PAD[33]
1%
1%
1%
1%
PAD[68]
1%
1%
—
—
PAD[23]
1%
1%
1%
1%
PAD[69]
1%
1%
—
—
PAD[34]
1%
1%
1%
1%
PAD[70]
1%
1%
—
—
PAD[24]
1%
1%
1%
1%
PAD[71]
1%
1%
—
—
PAD[66]
1%
1%
1%
1%
PAD[25]
1%
1%
1%
1%
PAD[26]
1%
1%
1%
1%
MPC5604P Microcontroller Data Sheet, Rev. 8
60
Freescale
Table 24. I/O weight (continued)
144 LQFP
100 LQFP
Pad
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
PAD[27]
1%
1%
1%
1%
PAD[28]
1%
1%
1%
1%
PAD[63]
1%
1%
1%
1%
PAD[72]
1%
1%
—
—
PAD[29]
1%
1%
1%
1%
PAD[73]
1%
1%
—
—
PAD[31]
1%
1%
1%
1%
PAD[74]
1%
1%
—
—
PAD[30]
1%
1%
1%
1%
PAD[75]
1%
1%
—
—
PAD[32]
1%
1%
1%
1%
PAD[76]
1%
1%
—
—
PAD[64]
1%
1%
1%
1%
PAD[0]
23%
20%
23%
20%
PAD[1]
21%
18%
21%
18%
PAD[107]
20%
17%
—
—
PAD[58]
19%
16%
19%
16%
PAD[106]
18%
16%
—
—
PAD[59]
17%
15%
17%
15%
PAD[105]
16%
14%
—
—
PAD[43]
15%
13%
15%
13%
PAD[104]
14%
13%
—
—
PAD[44]
13%
12%
13%
12%
PAD[103]
12%
11%
—
—
PAD[2]
11%
10%
11%
10%
PAD[101]
11%
9%
—
—
PAD[21]
10%
8%
10%
8%
TMS
1%
1%
1%
1%
TCK
1%
1%
1%
1%
PAD[20]
16%
11%
16%
11%
PAD[3]
4%
3%
4%
3%
PAD[61]
9%
8%
9%
8%
PAD[102]
11%
10%
—
—
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
61
Table 24. I/O weight (continued)
144 LQFP
100 LQFP
Pad
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
PAD[60]
11%
10%
11%
10%
PAD[100]
12%
10%
—
—
PAD[45]
12%
10%
12%
10%
PAD[98]
12%
11%
—
—
PAD[46]
12%
11%
12%
11%
PAD[99]
13%
11%
—
—
PAD[62]
13%
11%
13%
11%
PAD[92]
13%
12%
—
—
VPP_TEST
1%
1%
1%
1%
PAD[4]
14%
12%
14%
12%
PAD[16]
13%
12%
13%
12%
PAD[17]
13%
11%
13%
11%
PAD[42]
13%
11%
13%
11%
PAD[93]
12%
11%
—
—
PAD[95]
12%
11%
—
—
PAD[18]
12%
10%
12%
10%
PAD[94]
11%
10%
—
—
PAD[19]
11%
10%
11%
10%
PAD[77]
10%
9%
—
—
PAD[10]
10%
9%
10%
9%
PAD[78]
9%
8%
—
—
PAD[11]
9%
8%
9%
8%
PAD[79]
8%
7%
—
—
PAD[12]
7%
7%
7%
7%
PAD[41]
7%
6%
7%
6%
PAD[47]
5%
4%
5%
4%
PAD[48]
4%
4%
4%
4%
PAD[51]
4%
4%
4%
4%
PAD[52]
5%
4%
5%
4%
PAD[40]
5%
5%
6%
5%
PAD[80]
9%
8%
—
—
PAD[9]
10%
9%
11%
10%
PAD[81]
10%
9%
—
—
MPC5604P Microcontroller Data Sheet, Rev. 8
62
Freescale
Table 24. I/O weight (continued)
144 LQFP
100 LQFP
Pad
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
PAD[13]
10%
9%
12%
11%
PAD[82]
10%
9%
—
—
PAD[22]
10%
9%
13%
12%
PAD[83]
10%
9%
—
—
PAD[50]
10%
9%
14%
12%
PAD[97]
10%
9%
—
—
PAD[38]
10%
9%
14%
13%
PAD[14]
9%
8%
14%
13%
PAD[15]
9%
8%
15%
13%
Table 25. I/O consumption
Symbol
ISWTSLW,2
ISWTMED(2)
ISWTFST(2)
IRMSSLW
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
CC D Dynamic I/O current CL = 25 pF
for SLOW
configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
20
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16
CC D Dynamic I/O current CL = 25 pF
for MEDIUM
configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
CC D Dynamic I/O current CL = 25 pF
for FAST
configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
110
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
50
CC D Root medium square CL = 25 pF, 2 MHz
I/O current for SLOW
CL = 25 pF, 4 MHz
configuration
CL = 100 pF, 2 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 2 MHz
mA
mA
mA
mA
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
63
Table 25. I/O consumption (continued)
Symbol
IRMSMED
C
Typ
Max
—
—
6.6
—
—
13.4
—
—
18.3
—
—
5
—
—
8.5
—
—
11
—
—
22
—
—
33
—
—
56
—
—
14
—
—
20
CL = 100 pF, 40 MHz
—
—
35
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
CC D Root medium square CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%,
I/O current for
PAD3V5V = 0
CL = 25 pF, 40 MHz
MEDIUM
configuration
CL = 100 pF, 13 MHz
CL = 25 pF, 40 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 13 MHz
CC D Root medium square CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%,
I/O current for FAST
PAD3V5V = 0
CL = 25 pF, 64 MHz
configuration
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
IAVGSEG
1
2
3.11
SR D Sum of all the static
I/O current within a
supply segment
Unit
Min
CL = 25 pF, 13 MHz
IRMSFST
Value
Conditions1
Parameter
VDD = 3.3 V ± 10%,
PAD3V5V = 1
mA
mA
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Main oscillator electrical characteristics
The MPC5604P provides an oscillator/resonator driver.
Table 26. Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)
Value
Symbol
fOSC
C
Parameter
SR — Oscillator frequency
Unit
Min
Max
4
40
MHz
6.5
25
mA/V
gm
—
P Transconductance
VOSC
—
T Oscillation amplitude on XTAL pin
1
—
V
T Start-up time1,2
8
—
ms
tOSCSU —
1
The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and
excessive capacitive loads can cause long start-up time.
2 Value captured when amplitude reaches 90% of XTAL
MPC5604P Microcontroller Data Sheet, Rev. 8
64
Freescale
Table 27. Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)
Value
Symbol
fOSC
gm
VOSC
C
Parameter
Unit
Min
Max
S — Oscillator frequency
R
4
40
MHz
— P Transconductance
4
20
mA/V
—
1
—
V
8
—
ms
tOSCSU —
T Oscillation amplitude on XTAL pin
1,2
T Start-up time
1
The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and
excessive capacitive loads can cause long start-up time.
2
Value captured when amplitude reaches 90% of XTAL
Table 28. Input clock characteristics
Value
Symbol
Unit
Min
Typ
Max
fOSC
SR Oscillator frequency
4
—
40
MHz
fCLK
SR Frequency in bypass
—
—
64
MHz
trCLK
SR Rise/fall time in bypass
—
—
1
ns
47.5
50
52.5
%
tDC
3.12
Parameter
SR Duty cycle
FMPLL electrical characteristics
Table 29. FMPLL electrical characteristics
Symbol
C
fref_crystal D PLL reference frequency range2
fref_ext
fPLLIN
fFMPLLOUT D Clock frequency range in normal mode
P Free-running frequency
tCYC
D System clock period
fLORL
fLORH
D Loss of reference frequency window
fSCM
D Self-clocked mode frequency4,5
3
Unit
Min
Max
4
40
MHz
—
4
16
MHz
—
16
120
MHz
Measured using clock
division — typically /16
20
150
MHz
—
—
1 / fSYS
ns
Lower limit
1.6
3.7
MHz
Upper limit
24
56
20
150
Crystal reference
D Phase detector input frequency range (after
pre-divider)
fFREE
Value
Conditions1
Parameter
—
MHz
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
65
Table 29. FMPLL electrical characteristics (continued)
Symbol
CJITTER
C
Parameter
Short-term jitter10
T CLKOUT period
jitter6,7,8,9
Value
Conditions1
fSYS maximum
Long-term jitter (avg. fPLLIN = 16 MHz
over 2 ms interval)
(resonator), fPLLCLK at
64 MHz, 4,000 cycles
Unit
Min
Max
4
4
% fCLKOUT
—
10
ns
tlpll
D PLL lock time 11, 12
—
—
200
µs
tdc
D Duty cycle of reference
—
40
60
%
fLCK
D Frequency LOCK range
—
6
6
% fSYS
fUL
D Frequency un-LOCK range
—
-18
18
% fSYS
Center spread
±0.25
±4.013
% fSYS
Down spread
0.5
8.0
—
70
fCS
fDS
fMOD
D Modulation depth
D Modulation frequency14
—
kHz
1
VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified
Considering operation with PLL not bypassed
3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked
mode.
4 Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
5 f
VCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
6 This value is determined by the crystal manufacturer and board design.
7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
8 Proper PC board layout procedures must be followed to achieve specifications.
9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
JITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10 Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11
This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
12 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
13 This value is true when operating at frequencies above 60 MHz, otherwise f
CS is 2% (above 64 MHz).
14 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
2
MPC5604P Microcontroller Data Sheet, Rev. 8
66
Freescale
3.13
16 MHz RC oscillator electrical characteristics
Table 30. 16 MHz RC oscillator electrical characteristics
Value
Symbol
fRC
C
Parameter
P RC oscillator frequency
Conditions
Unit
Min
Typ
Max
TA = 25 °C
—
16
—
MHz
—
–5
—
5
%
RCMVAR
P Fast internal RC oscillator variation over temperature and
supply with respect to fRC at TA = 25 °C in high-frequency
configuration
RCMTRIM
T Post Trim Accuracy: The variation of the PTF1 from the
16 MHz
TA = 25 °C
–1
—
1
%
RCMSTEP
T Fast internal RC oscillator trimming step
TA = 25 °C
—
1.6
—
%
1
PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature
3.14
Analog-to-digital converter (ADC) electrical characteristics
The device provides a 10-bit successive approximation register (SAR) analog-to-digital converter.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
67
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(5)
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Figure 14. ADC characteristics and error definitions
3.14.1
Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be
measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
MPC5604P Microcontroller Data Sheet, Rev. 8
68
Freescale
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS and CP2 being
substantially two switched capacitances, with a frequency equal to the ADC conversion rate, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS+CP2 equal to 3 pF, a resistance of 330 k is obtained
(REQ = 1 / (fc × (CS+CP2)), where fc represents the conversion rate at the considered channel). To minimize the error induced
by the voltage partitioning between this resistance (sampled voltage on CS+CP2) and the sum of RS + RF, the external circuit
must be designed to respect the Equation 4:
Eqn. 4
RS + RF
1
V A --------------------- --- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive path.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
Channel
Selection
Sampling
RSW1
RAD
CP1
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
Figure 15. Input equivalent circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 15): A charge sharing phenomenon
is installed when the sampling phase is started (A/D switch closed).
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
69
Voltage Transient on CS
VCS
VA
VA2
V
工商网监
湘ICP备2023018690号
