NXP Semiconductors
Data Sheet: Technical Data
Document Number MPC5744P
Rev. 6.1, 11/2017
MPC5744P
MPC5744P Data Sheet
32-bit MCU suitable for ISO26262 ASILD chassis and safety applications
Features
• The MPC5744P microcontroller is based on the Power
Architecture® developed by NXP. It targets chassis
and safety applications and other applications requiring
a high Automotive Safety Integrity Level (ASIL). The
MPC5744P is a SafeAssure solution.
• This document provides electrical specifications, pin
assignments, and package diagram information for the
MPC5744P series of microcontroller units (MCUs).
For functional characteristics and the programming
model, see the MPC5744P Reference Manual.
• Junction temperature: The upper limit is 150°C or
165°C depending on the device marking.
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Introduction.......................................................................................... 3
3.12 Main oscillator electrical characteristics................................... 69
1.1
Features......................................................................................3
3.13 PLLDIG electrical characteristics............................................. 72
1.2
Block Diagram...........................................................................5
3.14 16 MHz Internal RC Oscillator (IRCOSC) electrical
2 Pinouts..................................................................................................6
specifications............................................................................. 73
2.1
Package pinouts and ballmap.................................................... 6
3.15 ADC electrical characteristics................................................... 74
2.2
Pin/ball descriptions ................................................................. 8
3.16 Flash memory specifications..................................................... 77
2.2.1
Pin/ball startup and reset states................................. 8
3.16.1
Maximum junction temperature 150°C.....................77
2.2.2
Power supply and reference voltage pins/balls......... 9
3.16.2
Maximum junction temperature 165°C.....................80
2.2.3
System pins/balls.......................................................12
3.16.3
Flash memory read wait-state and address-pipeline
2.2.4
LVDS pins/balls........................................................13
control settings.......................................................... 84
2.2.5
Generic pins/balls......................................................14
3.17 SGEN electrical characteristics................................................. 85
2.2.6
Peripheral input muxing............................................43
3.18 RESET sequence duration.........................................................86
3 Electrical characteristics.......................................................................55
3.19 AC specifications.......................................................................86
3.1
Introduction............................................................................... 55
3.19.1
Reset pad (EXT_POR, RESET) electrical
3.2
165°C junction temperature option........................................... 55
3.3
Absolute maximum ratings....................................................... 55
3.19.2
WKUP/NMI timing...................................................89
3.4
Recommended operating conditions......................................... 57
3.19.3
Debug/JTAG/Nexus/Aurora timing..........................89
3.5
Thermal characteristics..............................................................58
3.19.4
External interrupt timing (IRQ pin).......................... 96
3.5.1
General notes for specifications at maximum
3.19.5
SPI timing................................................................. 97
junction temperature................................................. 59
3.19.6
LFAST...................................................................... 102
3.6
Electromagnetic compatibility (EMC)...................................... 60
3.19.7
FlexRay..................................................................... 106
3.7
Electrostatic discharge (ESD) characteristics............................62
3.19.8
Ethernet switching specifications..............................109
3.8
Voltage regulator electrical characteristics............................... 62
4 Obtaining package dimensions.............................................................111
3.9
DC electrical characteristics...................................................... 65
5 Ordering information............................................................................112
3.10 Supply current characteristics....................................................67
6 Document revision history................................................................... 113
characteristics............................................................87
3.11 Temperature sensor................................................................... 69
MPC5744P Data Sheet, Rev. 6.1, 11/2017
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NXP Semiconductors
Introduction
1 Introduction
1.1 Features
The following table summarizes the features of the MPC5744P.
Table 1. MPC5744P feature summary
Feature
Details
CPU
Power Architecture
2 x e200z4 in delayed lock step
Architecture
Harvard
Execution speed
0 MHz to 200 MHz (+2% FM)
Embedded FPU
Yes
Core MPU
24 regions
Instruction Set PPC
No
Instruction Set VLE
Yes
Instruction cache
8 KB, EDC
Data cache
4 KB, EDC
Data local memory
64 KB, ECC
System MPU
Yes (16 regions)
Buses
Core bus
AHB, 32-bit address, 64-bit data, e2e ECC
Internal periphery bus
32-bit address, 32-bit data
Crossbar
Master x slave ports
4x5
Memory—see Table 2 for additional details
Code/data flash memory
2.5 MB, ECC, RWW
Data flash memory
Supported with RWW
SRAM
384 KB, ECC
Overlay access to SRAM from Flash Memory Controller
Yes
Modules
Interrupt controller
32 interrupt priority levels, 16 SW programmable interrupts
PIT
1 module with 4 channels
System Timer Module (STM)
1 module with 4 channels
Software Watchdog Timer (SWT)
Yes
eDMA
32 channels, in delayed lock step
FlexRay
1 module with 64 message buffer, dual channel
FlexCAN
3 modules with 64 message buffer
LINFlexD (UART and LIN with DMA support)
2 modules
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
3
Introduction
Table 1. MPC5744P feature summary (continued)
Feature
Details
Clockout
Yes
Fault Control and Collection Unit (FCCU)
Yes
Cross Triggering Unit (CTU)
2 modules
eTimer
3 modules with 6 channels
FlexPWM
2 modules with 4 x (2+1) channels
Analog-to-digital converter (ADC)
4 modules with 12-bit ADC, each with 16 channels (25
external channels including shared channels plus internal
channels)
Sine-wave generator (SGEN)
32 point
SPI
4 modules
As many as 8 chip selects
CRC Unit
Yes
SENT
2 modules with 2 channels
Interprocessor serial link interface (SIPI)
Yes
Junction temperature sensor
Yes (replicated module)
Digital I/Os
≥ 16
Peripheral register protection
Yes
Ethernet
Yes
Error Injection Module (EIM)
Yes
Supply
Device Power Supply
3.3 V with external ballast transistor
3.3 V with external 1.25 V low drop-out (LDO) regulator
ADC Analog Reference voltage
3.15 V to 5.5 V
Clocking
Phase Lock Loop (PLL)
1 x PLL and 1 coupled FMPLL
Internal RC Oscillator
16 MHz
External Crystal Oscillator
8 MHz to 40 MHz
Low power modes
HALT and STOP
Yes
Debug
Nexus
Level 3+, MDO and Aurora interface
Package
LQFP
144 pins, 0.5 mm pitch, 20 mm x 20 mm outline
MAPBGA
257 MAPBGA, 0.8 mm pitch, 14 mm x 14 mm outline
Temperature
Temperature range (junction)
-40°C to +150°C, option for 165°C
Ambient temperature range (LQFP)
-40°C to +125°C, 135°C option (with 165°C junction option)
Ambient temperature range (BGA)
-40°C to +125°C, 135°C option (with 165°C junction option)
MPC5744P Data Sheet, Rev. 6.1, 11/2017
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NXP Semiconductors
Introduction
Table 2. Flash memory and SRAM sizes of MPC5744P, MPC5743P, MPC5742P, and
MPC5741P
Part number
Flash memory
SRAM
MPC5744P
2.5 MB
384 KB
MPC5743P
2.0 MB
256 KB
MPC5742P
1.5 MB
192 KB
MPC5741P
1.0 MB
128 KB
1.2 Block Diagram
The following figure is a top-level diagram that shows the functional organization of the
system.
Figure 1. System Block Diagram
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
5
Pinouts
2 Pinouts
2.1 Package pinouts and ballmap
The following figures show the LQFP pinout and the BGA ballmap.
Figure 2. 144LQFP pinout
MPC5744P Data Sheet, Rev. 6.1, 11/2017
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NXP Semiconductors
Pinouts
Figure 3. 257MAPBGA ballmap
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
7
Pinouts
2.2 Pin/ball descriptions
The following sections provide signal descriptions and related information about the
functionality and configuration of the device. Note that this section is under development.
2.2.1 Pin/ball startup and reset states
The following table provides startup state and reset state information for device pins/
balls.
The startup state and subsequent states of the following pins/balls cannot be configured
by the user:
• JCOMP
• TMS
• TCK
• XTAL/EXTAL
• FCCU_F[0] and FCCU_F[1]
• EXT_POR_B
• RESET_B
The user can configure the state after reset of the following pins/balls by programming
the applicable MSCRs/IMCRs:
• GPIOs
• Analog inputs
• TDI
• TDO
• NMI_B
• FAB
• ABS[0]
• ABS[2]
Table 3. Pin/ball startup and reset states
Pin/ball
Startup state1, 2
State during reset
State after reset
144LQFP
257MAPBGA
Note3
GPIOs
hi-z
hi-z
hi-z
Note3
Analog inputs4
hi-z
hi-z
hi-z
Note3
Note3
JCOMP (TRST)
hi-z
input, weak pull-down
input, weak pull-down
Note5
Note5
TDI
hi-z
input, weak pull-up
input, weak pull-up
Note5
Note5
TDO
hi-z
output, hi-z
output, hi-z
Note5
Note5
input, weak pull-up
Note5
Note5
TMS6
hi-z
input, weak pull-up
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MPC5744P Data Sheet, Rev. 6.1, 11/2017
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NXP Semiconductors
Pinouts
Table 3. Pin/ball startup and reset states (continued)
Pin/ball
Startup state1, 2
State during reset
State after reset
144LQFP
257MAPBGA
TCK6
hi-z
input, weak pull-up
input, weak pull-up
Note5
Note5
XTAL/EXTAL
hi-z
hi-z
hi-z
Note5
Note5
FCCU_F[0]6
hi-z
input, hi-z
output/input, hi-z
38
R2
FCCU_F[1]6
hi-z
input, hi-z
output/input, hi-z
141
C4
Note5
EXT_POR_B
hi-z
input, weak pull-down
input, weak pull-down
Note5
RESET_B
hi-z
input, weak pull-down
input, weak pull-down
Note5
Note5
NMI_B
hi-z
input, weak pull-up
input,weak pull-up
Note5
Note5
FAB
hi-z
input, weak pull-down
input, weak pull-down
Note5
Note5
ABS[2]
hi-z
input, weak pull-down
input, weak pull-down
Note5
Note5
ABS[0]
hi-z
input, weak pull-down
input, weak pull-down
Note5
Note5
1. Startup state is exited when the core and high-voltage supplies reach minimum levels.
2. Pads marked “high impedance” for POR will be in either high-impedance or weak low drive state when VDD_LV_CORE is
off and HV_VDD_IO is below 1.5 V.
3. See Generic pins/balls.
4. Not all non-supply or reference pins on the device are explicitly defined in this table.
5. See System pins/balls.
6. This pin/ball is dedicated to and directly connected to a peripheral module pin.
2.2.2 Power supply and reference voltage pins/balls
Table 4. Power supply and reference voltage pins/balls
Supply
Symbol
VDD_LV_COR
Type
Power
Package
Description
Low voltage power Supply
144LQFP
257MAPBGA
18
F6
39
F7
70
F8
93
F9
131
F10
135
F11
F12
G6
G12
H6
H12
J6
J12
K6
K12
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
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9
Pinouts
Table 4. Power supply and reference voltage pins/balls (continued)
Supply
Symbol
Type
Package
Description
144LQFP
257MAPBGA
L6
L12
M6
M7
M8
M9
M10
M11
M12
VSS_LV_COR
Ground
Low voltage ground. PLL Ground is also connected to low
voltage ground for core logic on 144LQFP (pin 35).
17
B1
35
G7
40
G8
71
G9
94
G10
96
G11
132
H7
137
H8
H9
H10
H11
J7
J8
J9
J10
J11
K7
K8
K9
K10
K11
L7
L8
L9
L10
L11
VDD_LV_PLL
Power
PLL low voltage Supply
36
P4
VSS_LV_PLL
Ground
PLL low voltage Ground
35
N4
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
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NXP Semiconductors
Pinouts
Table 4. Power supply and reference voltage pins/balls (continued)
Supply
Symbol
VDD_HV_IO
Type
Power
Package
Description
High voltage Power Supply for I/O
144LQFP
257MAPBGA
6
A9
21
B2
72
B16
91
D8
126
D14
G2
M2
T2
T16
U14
VSS_HV_IO
Ground
High voltage Ground Supply for I/O
7
A1
22
A2
90
A16
127
A17
B1
B9
B17
C3
C15
D9
H2
N2
R3
R15
T1
T17
U1
U2
U16
U17
Power
PMU high voltage Supply
72
U14
VDD_HV_OSC
Power
Power Supply for the oscillator
27
M1
VSS_HV_OSC
Ground
Ground Supply for the oscillator
28
P1
VDD_HV_FLA
Power
Power Supply and decoupling pin for flash memory
97
H16
VDD_HV_ADV
Power
High voltage Supply for ADC, TSENS, SGEN (3.3 V)
58
T10
VSS_HV_ADV
Ground
High voltage Ground for ADC
59
U9
VDD_HV_PMU
VDD_HV_PMU_AUX
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
11
Pinouts
Table 4. Power supply and reference voltage pins/balls (continued)
Supply
Symbol
Type
VDD_HV_ADRE0
Supply
Package
Description
144LQFP
257MAPBGA
50
R7
51
T7
56
R9
57
T9
High voltage Supply for digital portion of ADC pads
Voltage reference of ADC/TSENS
High voltage Supply for ADC0 pads and shared pads for
ADC0/1.
VSS_HV_ADRE0
Ground
High voltage Ground for digital portion of ADC pads
Voltage reference Ground of ADC/TSENS
High voltage Ground for ADC0 pads and shared pads for
ADC0/1.
VDD_HV_ADRE1
Supply
High voltage Supply for digital portion of ADC pads
Voltage reference of ADC/TSENS
High voltage Supply for ADC1 pads, shared pads for ADC1/3,
and shared pads for ADC2/3.
VSS_HV_ADRE1
Ground
High voltage Ground for digital portion of ADC pads
Voltage reference Ground of ADC/TSENS
High voltage Ground for ADC1 pads, shared pads for
ADC1/3, and shared pads for ADC2/3.
VDD_LV_LFAST
Supply
LFAST PLL low voltage Supply
—
N16
VSS_LV_LFAST
Ground
LFAST PLL low voltage Ground
—
N17
VDD_LV_NEXUS
Supply
Aurora LVDS Supply
—
J16
VSS_LV_NEXUS
Ground
Aurora LVDS Ground
—
K16
2.2.3 System pins/balls
The following table contains information about system pin functions for the devices.
Table 5. System pins/balls
Symbol
Type
NMI_B
Input
XTAL
Output
Description
144LQFP
257MAPBGA
Non-maskable Interrupt
1
E4
Output of the oscillator amplifier circuit
29
N1
EXTAL
Input
Crystal oscillator input/external clock input
30
R1
RESET_B
Input
Functional Reset
31
P2
EXT_POR_B
Input
External Power On Reset
130
D6
VPP_TEST1
Input
SoC Test Mode
107
D15
JCOMP
Input
JTAGC, JTAG Compliance Enable
123
A6
TCK
Input
JTAGC, Test Clock Input
88
H17
TMS
Input
JTAGC, Test Mode Select
87
H15
TDO
Output
JTAGC, Test Data Out
89
G14
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MPC5744P Data Sheet, Rev. 6.1, 11/2017
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Pinouts
Table 5. System pins/balls (continued)
Symbol
Type
TDI
Input
Description
144LQFP
257MAPBGA
JTAGC, Test Data Input
86
J17
9
G1
4,5,8
E1, F1, E2
MDO[0]
Output
NEXUS, Message data out pins; reflects the state of
the internal power on reset signal until RESET is
negated
MDO[3:1]
Output
NEXUS, Message data out pins
EVTO
Output
NEXUS, Event Out Pin
24
K2
EVTI
NEXUS, Event In Pin
25
L2
MCKO
Output
Input
NEXUS, Message clock out pin
19
J4
MSEO[1:0]
Output
NEXUS, Message Start/End out pin
20, 23
J3, K3
RDY_B
Output
NEXUS, Read/Write Transfer completed
—
J2
16
K1
69
R13
—
L17, K17
BCTRL
Output
J[11], J[10]
--
Base control signal of external npn ballast
FSL Factory
Test2
1. VPP_TEST must be connected to ground.
2. Do not connect on the board.
2.2.4 LVDS pins/balls
The following tables contain information on LVDS pin functions for the devices.
Table 6. SIPI LFAST LVDS pin descriptions
Functional
block
Port pin
SIPI LFAST1, 2
Signal
Signal description
Direction
257MAPBGA
I[5]
LFAST_TX SIPI/ LFAST, LVDS Transmit Negative Terminal
N
O
N15
C[12]3
LFAST_TX SIPI/ LFAST, LVDS Transmit Positive Terminal
P
O
M14
I[6]
LFAST_RX SIPI/ LFAST, LVDS Receive Negative Terminal
N
I
M15
G[7]3
LFAST_RX SIPI/ LFAST, LVDS Receive Positive Terminal
P
I
M16
1. DRCLK and TCK/DRCLK usage for SIPI LFAST are described in the reference manual's SIPI LFAST chapters.
2. For the MSCR SSS value of the port pin, see Table 1.
3. The 144LQFP package has G[7] and C[12] but no SIPI LFAST functionality.
CAUTION
SIPI LFAST pins are muxed with GPIOs. Do not use GPIO and
SIPI LFAST functionality in parallel.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
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13
Pinouts
Table 7. Aurora LVDS pin descriptions
Functional block
Nexus Aurora High
Speed Trace
Direction
257MAPBGA1
Nexus Aurora High Speed Trace Lane 0,
LVDS Positive Terminal
O
H14
TX0N
Nexus Aurora High Speed Trace Lane 0,
LVDS Negative Terminal
O
J14
G[14]
TX1P
Nexus Aurora High Speed Trace Lane 1,
LVDS Positive Terminal
O
L15
G[15]
TX1N
Nexus Aurora High Speed Trace Lane 1,
LVDS Negative Terminal
O
K14
H[0]
CLKP
Nexus Aurora High Speed Trace Clock,
LVDS Positive Terminal
I
K15
H[1]
CLKN
Nexus Aurora High Speed Trace Clock,
LVDS Negative Terminal
I
J15
Pad
Signal
G[12]
TX0P
G[13]
Signal description
1. Nexus Aurora High Speed Trace is available only on the 257MAPBGA.
2.2.5 Generic pins/balls
The I/O signal descriptions for the device are in the following table. It contains the port
definition, multiplexing, direction, pad type, and package pin/ball numbers for each I/O
pin on the device.
MSCR registers are used for alternative (ALT) mode selection and programming of pad
control options.
IMCR registers are used to configure input muxing by peripheral. See Peripheral input
muxing for details.
For the pins which have Nexus functionality muxed with GPIO or other functions, the
Nexus functionality of such pins is automatically set when the Nexus tool is connected to
the device. The value in MSCR register may have value that does not correspond to
Nexus functionality.
A[0]
SIUL2 MSCR/
IMCR
Number
MSCR[0]
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0000
(Default)2
GPIO[0]
SIUL2-GPIO[0] General Purpose IO A[0]
I/O
0001
ETC0
eTimer_0
eTimer_0 Input/Output Data
Channel 0
I/O
0010
SCK
DSPI2
DSPI 2 Input/Output Serial
Clock
I/O
73
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing
P12
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Pinouts
A[1]
A[2]
A[3]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0011-1111
—
Reserved
—
—
IMCR[48]
0001
SCK
DSPI2
DSPI 2 Input Serial Clock
I
IMCR[59]
0010
ETC0
eTimer_0
eTimer_0 Input Data Channel 0 I
IMCR[173]
0001
REQ0
SIUL2
SIUL2 External Interrupt 0
MSCR[1]
0000
(Default)
GPIO[1]
SIUL2-GPIO[1] General Purpose IO A[1]
I/O
0001
ETC1
eTimer_0
eTimer_0 Input/Output Data
Channel 1
I/O
0010
SOUT
DSPI2
DSPI 2 Serial Data Out
O
0011-1111
—
Reserved
—
—
IMCR[60]
0010
ETC1
eTimer_0
eTimer_0 Input Data Channel 1 I
IMCR[174]
0001
REQ1
SIUL2
SIUL2 External Interrupt
Source 1
MSCR[2]
0000
(Default)
GPIO[2]
SIUL2-GPIO[2] General Purpose IO A[2]
I/O
0001
ETC2
eTimer_0
eTimer_0 Input/Output Data
Channel 2
I/O
0010
—
Reserved
—
—
0011
A3
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 3
I/O
0100-1111
—
Reserved
—
—
IMCR[169]
0000
(Default)
ABS0
MC_RGM
RGM external boot mode 1
I
IMCR[47]
0010
SIN
DSPI2
DSPI 2 Serial Data Input
I
IMCR[61]
0010
ETC2
eTimer_0
eTimer_0 Input Data Channel 2 I
IMCR[97]
0001
A3
FlexPWM_0
FlexPWM_0 Channel A Input 3 I
IMCR[175]
0001
REQ2
SIUL2
SIUL2 External Interrupt
Source 2
MSCR[3]
0000
(Default)
GPIO[3]
SIUL2-GPIO[3] General Purpose IO A[3]
I/O
0001
ETC3
eTimer_0
eTimer_0 Input/Output Data
Channel 3
I/O
0010
CS0
DSPI2
DSPI 2 Peripheral Chip Select
0
I/O
0011
B3
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 3
I/O
0100-1111
—
Reserved
—
—
IMCR[171]
0000
(Default)
ABS2
MC_RGM
RGM external boot mode 2
I
IMCR[62]
0010
ETC3
eTimer_0
eTimer_0 Input Data Channel 3 I
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
I
74
T14
84
L14
92
G15
I
I
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MPC5744P Data Sheet, Rev. 6.1, 11/2017
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Pinouts
A[4]
A[5]
A[6]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
IMCR[49]
0001
CS0
DSPI2
DSPI 2 Peripheral Chip Select
0
IMCR[98]
0001
B3
FlexPWM_0
FlexPWM_0 Channel B Input 3 I
IMCR[176]
0001
REQ3
SIUL2
SIUL2 External Interrupt
Source 3
MSCR[4]
0000
(Default)
GPIO[4]
SIUL2-GPIO[4] General Purpose IO A[4]
I/O
0001
ETC0
eTimer_1
eTimer_1 Input/Output Data
Channel 0
I/O
0010
CS1
DSPI2
DSPI 2 Peripheral Chip Select
1
O
0011
ETC4
eTimer_0
eTimer_0 Input/Output Data
Channel 4
I/O
0100
A2
FlexPWM_1
FlexPWM_1 Channel A Input/
Output 2
I/O
0101-1111
—
Reserved
—
—
IMCR[112]
0001
A2
FlexPWM_1
FlexPWM_1 Channel A Input 2 I
IMCR[177]
0001
REQ4
SIUL2
SIUL2 External Interrupt
Source 4
I
IMCR[172]
0000
(Default)
FAB
MC_RGM
RGM Force Alternate Boot
Mode
I
IMCR[65]
0001
ETC0
eTimer_1
eTimer_1 Input Data Channel 0 I
IMCR[63]
0011
ETC4
eTimer_0
eTimer_0 Input Data Channel 4 I
MSCR[5]
0000
(Default)
GPIO[5]
SIUL2-GPIO[5] General Purpose IO A[5]
I/O
0001
CS0
DSPI1
DSPI 1 Peripheral Chip Select
0
I/O
0010
ETC5
eTimer_1
eTimer_1 Input/Output Data
Channel 5
I/O
0011
CS7
DSPI0
DSPI 0 Peripheral Chip Select
7
O
—
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
108
D16
14
H4
2
D1
I
I
0100-1111
—
Reserved
—
IMCR[70]
0001
ETC5
eTimer_1
eTimer_1 Input Data Channel 5 I
IMCR[178]
0001
REQ5
SIUL2
SIUL2 External Interrupt
Source 5
MSCR[6]
0000
(Default)
GPIO[6]
SIUL2-GPIO[6] General Purpose IO A[6]
I/O
0001
SCK
DSPI1
DSPI 1 Input/Output Serial
Clock
I/O
0010
ETC2
eTimer_2
eTimer_2 Input/Output Data
Channel 2
I/O
0011-1111
—
Reserved
—
—
I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
16
NXP Semiconductors
Pinouts
A[7]
A[8]
A[9]
A[10]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
IMCR[73]
0001
ETC2
eTimer_2
eTimer_2 Input Data Channel 2 I
IMCR[179]
0001
REQ6
SIUL2
SIUL2 External Interrupt
Source 6
MSCR[7]
0000
(Default)
GPIO[7]
SIUL2-GPIO[7] General Purpose IO A[7]
I/O
0001
SOUT
DSPI1
DSPI 1 Serial Data Out
O
0010
ETC3
eTimer_2
eTimer_2 Input/Output Data
Channel 3
I/O
0011-1111
—
Reserved
—
—
IMCR[74]
0001
ETC3
eTimer_2
eTimer_2 Input Data Channel 3 I
IMCR[180]
0001
REQ7
SIUL2
SIUL2 External Interrupt
Source 7
MSCR[8]
0000
(Default)
GPIO[8]
SIUL2-GPIO[8] General Purpose IO A[8]
I/O
0001
—
Reserved
—
—
0010
ETC4
eTimer_2
eTimer_2 Input/Output Data
Channel 4
I/O
0011-1111
—
Reserved
—
—
IMCR[44]
0001
SIN
DSPI1
DSPI 1 Serial Data Input
I
IMCR[75]
0001
ETC4
eTimer_2
eTimer_2 Input Data Channel 4 I
IMCR[181]
0001
REQ8
SIUL2
SIUL2 External Interrupt
Source 8
MSCR[9]
0000
(Default)
GPIO[9]
SIUL2-GPIO[9] General Purpose IO A[9]
I/O
0001
CS1
DSPI2
DSPI 2 Peripheral Chip Select
1
O
0010
ETC5
eTimer_2
eTimer_2 Input/Output Data
Channel 5
I/O
0011
B3
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 3
I/O
0100-1111
—
Reserved
—
—
IMCR[76]
0001
ETC5
eTimer_2
eTimer_2 Input Data Channel 5 I
IMCR[98]
0010
B3
FlexPWM_0
FlexPWM_0 Channel B Input 3 I
IMCR[83]
0001
FAULT0
FlexPWM_0
FlexPWM_0 Fault Input 0
I
IMCR[206]
0011
SENT_RX[1]
SENT_0
SENT 0 Receiver channel 1
I
MSCR[10]
0000
(Default)
GPIO[10]
SIUL2GPIO[10]
General Purpose IO A[10]
I/O
0001
CS0
DSPI2
DSPI 2 Peripheral Chip Select
0
O
0010
B0
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 0
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
I
10
G4
12
H1
134
A4
118
B11
I
I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
17
Pinouts
A[11]
A[12]
A[13]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0011
X2
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 2
I/O
0100-1111
—
Reserved
—
—
IMCR[49]
0010
CS0
DSPI2
DSPI 2 Peripheral Chip Select
0
I/O
IMCR[89]
0001
B0
FlexPWM_0
FlexPWM_0 Channel B Input 0 I
IMCR[96]
0001
X2
FlexPWM_0
FlexPWM_0 Auxiliary Input 2
I
IMCR[182]
0001
REQ9
SIUL2
SIUL2 External Interrupt
Source 9
I
IMCR[214]
0011
SENT_RX[1]
SENT_1
SENT 1 Receiver channel 1
I
MSCR[11]
0000
(Default)
GPIO[11]
SIUL2GPIO[11]
General Purpose IO A[11]
I/O
0001
SCK
DSPI2
DSPI 2 Input/Output Serial
Clock
I/O
0010
A0
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 0
I/O
0011
A2
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 2
I/O
0100-1111
—
Reserved
—
—
IMCR[48]
0010
SCK
DSPI2
DSPI 2 Input Serial Clock
I
IMCR[88]
0001
A0
FlexPWM_0
FlexPWM_0 Channel A Input 0 I
IMCR[94]
0001
A2
FlexPWM_0
FlexPWM_0 Channel A Input 2 I
IMCR[183]
0001
REQ10
SIUL2
SIUL2 External Interrupt
Source 10
I
MSCR[12]
0000
(Default)
GPIO[12]
SIUL2GPIO[12]
General Purpose IO A[12]
I/O
0001
SOUT
DSPI2
DSPI 2 Serial Data Out
O
0010
A2
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 2
I/O
0011
B2
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 2
I/O
0100-1111
—
Reserved
—
—
IMCR[94]
0010
A2
FlexPWM_0
FlexPWM_0 Channel A Input 2 I
IMCR[95]
0001
B2
FlexPWM_0
FlexPWM_0 Channel B Input 2 I
IMCR[184]
0001
REQ11
SIUL2
SIUL2 External Interrupt
Source 11
I
MSCR[13]
0000
(Default)
GPIO[13]
SIUL2GPIO[13]
General Purpose IO A[13]
I/O
0001
—
Reserved
—
—
0010
B2
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 2
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
120
D10
122
D7
136
C5
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
18
NXP Semiconductors
Pinouts
A[14]
A[15]
B[0]
B[1]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0011-1111
—
Reserved
—
—
IMCR[83]
0010
FAULT0
FlexPWM_0
FlexPWM_0 Fault Input 0
I
IMCR[95]
0010
B2
FlexPWM_0
FlexPWM_0 Channel B Input 2 I
IMCR[47]
0001
SIN
DSPI2
DSPI 2 Serial Data Input
I
IMCR[185]
0001
REQ12
SIUL2
SIUL2 External Interrupt
Source 12
I
MSCR[14]
0000
(Default)
GPIO[14]
SIUL2GPIO[14]
General Purpose IO A[14]
I/O
0001
TXD
CAN1
CAN 1 Transmit Pin
O
0010
ETC4
eTimer_1
eTimer_1 Input/Output Data
Channel 4
I/O
0011-1111
—
Reserved
—
—
IMCR[69]
0001
ETC4
eTimer_1
eTimer_1 Input Data Channel 4 I
IMCR[186]
0001
REQ13
SIUL2
SIUL2 External Interrupt
Source 13
I
MSCR[15]
0000
(Default)
GPIO[15]
SIUL2GPIO[15]
General Purpose IO A[15]
I/O
0001
—
Reserved
—
—
0010
ETC5
eTimer_1
eTimer_1 Input/Output Data
Channel 5
I/O
0011-1111
—
Reserved
—
—
IMCR[32]
0001
RXD
CAN0
CAN 0 Receive Pin
I
IMCR[33]
0001
RXD
CAN1
CAN 1 Receive Pin
I
IMCR[70]
0010
ETC5
eTimer_1
eTimer_1 Input Data Channel 5 I
IMCR[187]
0001
REQ14
SIUL2
SIUL2 External Interrupt
Source 14
I
MSCR[16]
0000
(Default)
GPIO[16]
SIUL2GPIO[16]
General Purpose IO B[0]
I/O
0001
TXD
CAN0
CAN 0 Transmit Pin
O
0010
ETC2
eTimer_1
eTimer_1 Input/Output Data
Channel 2
I/O
0011
DEBUG0
SSCM
SSCM Debug Output 0
O
0100-1111
—
Reserved
—
—
IMCR[67]
0001
ETC2
eTimer_1
eTimer_1 Input Data Channel 2 I
IMCR[188]
0001
REQ15
SIUL2
SIUL2 External Interrupt
Source 15
I
MSCR[17]
0000
(Default)
GPIO[17]
SIUL2GPIO[17]
General Purpose IO B[1]
I/O
0001
—
Reserved
—
—
0010
ETC3
eTimer_1
eTimer_1 Input/Output Data
Channel 3
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
143
A3
144
D3
109
C16
110
C14
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
19
Pinouts
B[2]
B[3]
B[4]
B[5]
B[6]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0011
DEBUG1
SSCM
SSCM Debug Output 1
O
0100-1111
—
Reserved
—
—
IMCR[32]
0010
RXD
CAN0
CAN 0 Receive Pin
I
IMCR[33]
0010
RXD
CAN1
CAN 1 Receive Pin
I
IMCR[68]
0001
ETC3
eTimer_1
eTimer_1 Input Data Channel 3 I
IMCR[189]
0001
REQ16
SIUL2
SIUL2 External Interrupt
Source 16
I
MSCR[18]
0000
(Default)
GPIO[18]
SIUL2GPIO[18]
General Purpose IO B[2]
I/O
0001
TXD
LIN0
LINFlexD 0 Transmit Pin
O
0010
CS4
DSPI0
DSPI 0 Peripheral Chip Select
4
O
0011
DEBUG2
SSCM
SSCM Debug Output 2
O
0100-1111
—
Reserved
—
—
IMCR[190]
0001
REQ17
SIUL2
SIUL2 External Interrupt
Source 17
I
MSCR[19]
0000
(Default)
GPIO[19]
SIUL2GPIO[19]
General Purpose IO B[3]
I/O
0001
—
Reserved
—
—
0010
CS5
DSPI0
DSPI 0 Peripheral Chip Select
5
O
0011
DEBUG3
SSCM
SSCM Debug Output 3
O
0100-1111
—
Reserved
—
—
IMCR[165]
0001
RXD
LIN0
LIN 0 Receive Pin
I
MSCR[20]
0
GPIO[20]
SIUL2GPIO[20]
General Purpose IO B[4]
I/O
0001
(Default)
TDO
NPC_HNDSHK NPC_HNDSHK Test Data Out
(TDO)
O
0010-1111
—
Reserved
—
—
0000
(Default)
GPIO[21]
SIUL2GPIO[21]
JTAGC Test Data In (TDI)3
I/O
0001
CS7
DSPI0
DSPI 0 Peripheral Chip Select
7
O
0010-1111
—
Reserved
—
—
0000
(Default)
GPIO[22]
SIUL2GPIO[22]
General Purpose IO B[6]
I/O
0001
CLK_OUT
MC_CGM
CGM Clock out for off-chip use O
and observation
0010
CS2
DSPI2
DSPI 2 Peripheral Chip Select
2
O
0011-1111
—
Reserved
—
—
MSCR[21]
MSCR[22]
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
114
C12
116
B12
89
G14
86
J17
138
B5
General Purpose IO B[5]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
20
NXP Semiconductors
Pinouts
B[7]
B[8]
SIUL2 MSCR/
IMCR
Number
B[10]
B[11]
B[12]
B[13]
B[14]
Signal
Module
Short Signal Description
SIUL2 External Interrupt
Source 18
Dir
IMCR[191]
0001
REQ18
SIUL2
MSCR[23]
0000
(Default)
GPI[23]4
SIUL2-GPI[23] General Purpose Input B[7]
I
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0010
RXD
LIN0
LIN 0 Receive Pin
I
MSCR[24]
0
GPI[24]4
ADC0_AN[1]
SIUL2-GPI[24] General Purpose Input B[8]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0001
ETC5
eTimer_0
eTimer_0 Input Data Channel 5 I
0000
(Default)
GPI[25]4
SIUL2-GPI[25] General Purpose Input B[9]
I
MSCR[25]
MSCR[26]
MSCR[27]
MSCR[28]
MSCR[29]
43
R5
47
P7
52
U7
53
R8
54
T8
55
U8
60
R10
64
P11
ADC0_AN[0]
IMCR[165]
IMCR[64]
B[9]
MSCR/
IMCR SSS
Value1
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
ADC0_ADC1_A
N[11]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[26]4
SIUL2-GPI[26] General Purpose Input B[10]
I
ADC0_ADC1_A
N[12]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[27]4
SIUL2-GPI[27] General Purpose Input B[11]
I
ADC0_ADC1_A
N[13]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[28]4
SIUL2-GPI[28] General Purpose Input B[12]
I
ADC0_ADC1_A
N[14]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[29]4
SIUL2-GPI[29] General Purpose Input B[13]
I
ADC1_AN[0]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
IMCR[166]
0001
RXD
LIN1
LIN 1 Receive Pin
I
MSCR[30]
0000
(Default)
GPI[30]4
ADC1_AN[1]
SIUL2-GPI[30] General Purpose Input B[14]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
21
Pinouts
B[15]
C[0]
C[1]
C[2]
C[4]
C[5]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
IMCR[63]
0001
ETC4
eTimer_0
eTimer_0 Input Data Channel 4 I
IMCR[192]
0001
REQ19
SIUL2
SIUL2 External Interrupt
Source 19
MSCR[31]
0000
(Default)
GPI[31]4
ADC1_AN[2]
SIUL2-GPI[31] General Purpose Input B[15]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
IMCR[193]
0001
REQ20
SIUL2
SIUL2 External Interrupt
Source 20
I
MSCR[32]
0000
(Default)
GPI[32]4
ADC1_AN[3]
SIUL2-GPI[32] General Purpose Input C[0]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[33]4
SIUL2-GPI[33] General Purpose Input C[1]
I
ADC0_AN[2]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[34]4
ADC0_AN[3]
SIUL2-GPI[34] General Purpose Input C[2]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPIO[36]
SIUL2GPIO[36]
General Purpose IO C[4]
I/O
0001
CS0
DSPI0
DSPI 0 Peripheral Chip Select
0
I/O
0010
X1
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 1
I/O
0011
DEBUG4
SSCM
SSCM Debug Output 4
O
0100-1111
—
Reserved
—
—
IMCR[93]
0001
X1
FlexPWM_0
FlexPWM_0 Auxiliary Input 1
I
IMCR[195]
0001
REQ22
SIUL2
SIUL2 External Interrupt
Source 22
I
MSCR[37]
0000
(Default)
GPIO[37]
SIUL2GPIO[37]
General Purpose IO C[5]
I/O
0001
SCK
DSPI0
DSPI 0 Input/Output Serial
Clock
I/O
0010
—
Reserved
—
—
0011
DEBUG5
SSCM
SSCM Debug Output 5
O
0100-1111
—
Reserved
—
—
0001
FAULT3
FlexPWM_0
FlexPWM_0 Fault Input 3
I
MSCR[33]
MSCR[34]
MSCR[36]
IMCR[86]
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
I
62
R11
66
R12
41
T4
45
U5
11
H3
13
G3
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
22
NXP Semiconductors
Pinouts
C[6]
C[7]
C[10]
C[11]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
IMCR[196]
0001
REQ23
SIUL2
SIUL2 External Interrupt
Source 23
I
MSCR[38]
0000
(Default)
GPIO[38]
SIUL2GPIO[38]
General Purpose IO C[6]
I/O
0001
SOUT
DSPI0
DSPI 0 Serial Data Out
O
0010
B1
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 1
I/O
0011
DEBUG6
SSCM
SSCM Debug Output 6
O
0100-1111
—
Reserved
—
—
IMCR[92]
0001
B1
FlexPWM_0
FlexPWM_0 Channel B Input 1 I
IMCR[197]
0001
REQ24
SIUL2
SIUL2 External Interrupt
Source 24
I
MSCR[39]
0000
(Default)
GPIO[39]
SIUL2GPIO[39]
General Purpose IO C[7]
I/O
0001
—
Reserved
—
—
0010
A1
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 1
I/O
0011
DEBUG7
SSCM
SSCM Debug Output 7
O
0100-1111
—
Reserved
—
—
IMCR[41]
0001
SIN
DSPI0
DSPI 0 Serial Data Input
I
IMCR[91]
0001
A1
FlexPWM_0
FlexPWM_0 Channel A Input 1 I
MSCR[42]
0000
(Default)
GPIO[42]
SIUL2GPIO[42]
General Purpose IO C[10]
I/O
0001
CS2
DSPI2
DSPI 2 Peripheral Chip Select
2
O
0010
—
Reserved
—
—
0011
A3
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 3
I/O
0100-1111
—
Reserved
—
—
IMCR[84]
0001
FAULT1
FlexPWM_0
FlexPWM_0 Fault Input 1
I
IMCR[97]
0010
A3
FlexPWM_0
FlexPWM_0 Channel A Input 3 I
MSCR[43]
0000
(Default)
GPIO[43]
SIUL2GPIO[43]
General Purpose IO C[11]
I/O
0001
ETC4
eTimer_0
eTimer_0 Input/Output Data
Channel 4
I/O
0010
CS2
DSPI2
DSPI 2 Peripheral Chip Select
2
O
0011
TX_ER
ENET_0
Ethernet transmit Data Error
O
0100
CS0
DSPI3
DSPI 3 Peripheral Chip Select
0
I/O
0101-1111
—
Reserved
—
—
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
142
D4
15
J1
111
B14
80
P16
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
23
Pinouts
C[12]5
C[13]
C[14]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
IMCR[52]
0001
CS0
DSPI3
DSPI 3 Peripheral Chip Select
0"
IMCR[63]
0100
ETC4
eTimer_0
eTimer_0 Input Data Channel 4 I
MSCR[44]
0000
(Default)
GPIO[44]
SIUL2GPIO[44]
General Purpose IO C[12]
I/O
0001
ETC5
eTimer_0
eTimer_0 Input/Output Data
Channel 56
I/O
0010
CS3
DSPI2
DSPI 2 Peripheral Chip Select
3
O
0011
LFAST_TXP
LFAST
SIPI/LFAST LVDS transmit
positive terminal
O
0100
CS1
DSPI3
DSPI 3 Peripheral Chip Select
1
O
0101-1111
—
Reserved
—
—
IMCR[213]
0100
SENT_RX[0]
SENT1
SENT 1 Receiver Channel 0
I
IMCR[64]
0011
ETC5
eTimer_0
eTimer_0 Input Data Channel 5 I
MSCR[45]
0000
(Default)
GPIO[45]
SIUL2GPIO[45]
General Purpose IO C[13]
I/O
0001
ETC1
eTimer_1
eTimer_1 Input/Output Data
Channel 1
I/O
0010-0011
—
Reserved
—
—
0100
A0
FlexPWM_1
FlexPWM_1 Channel A Input/
Output 0
I/O
0101-1111
—
Reserved
—
—
IMCR[38]
0001
EXT_IN
CTU_0
CTU 0 External Trigger Input
I
IMCR[66]
0001
ETC1
eTimer_1
eTimer_1 Input Data Channel 1 I
IMCR[87]
0001
EXT_SYNC
FlexPWM_0
FlexPWM_0 External Trigger
Input
IMCR[105]
0001
A0
FlexPWM_1
FlexPWM_1 Channel A Input 0 I
MSCR[46]
0000
(Default)
GPIO[46]
SIUL2GPIO[46]
General Purpose IO C[14]
I/O
0001
ETC2
eTimer_1
eTimer_1 Input/Output Data
Channel 2
I/O
0010
EXT_TGR
CTU_0
CTU0 External Trigger Output
O
0011
CS7
DSPI1
DSPI 1 Peripheral Chip Select
7
O
0100
B0
FlexPWM_1
FlexPWM_1 Channel B Input/
Output 0
I/O
—
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
I
82
M14
101
E15
103
F14
I
0101-1111
—
Reserved
—
IMCR[67]
0010
ETC2
eTimer_1
eTimer_1 Input Data Channel 2 I
IMCR[106]
0001
B0
FlexPWM_1
FlexPWM_1 Channel B Input 0 I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
24
NXP Semiconductors
Pinouts
C[15]
D[0]
D[1]
D[2]
SIUL2 MSCR/
IMCR
Number
MSCR[47]
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0000
(Default)
GPIO[47]
SIUL2GPIO[47]
General Purpose IO C[15]
I/O
0001
FR_A_TXEN
FLEXRAY
FlexRay Transmit Enable
Channel A
O
0010
ETC0
eTimer_1
eTimer_1 Input/Output Data
Channel 0
I/O
0011
A1
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 1
I/O
0100-1111
—
Reserved
—
—
IMCR[38]
0010
EXT_IN
CTU_0
CTU 0 External Trigger Input
I
IMCR[65]
0010
ETC0
eTimer_1
eTimer_1 Input Data Channel 0 I
IMCR[87]
0010
EXT_SYNC
FlexPWM_0
FlexPWM_0 External Sync
Input
IMCR[91]
0010
A1
FlexPWM_0
FlexPWM_0 Channel A Input 1 I
MSCR[48]
0000
(Default)
GPIO[48]
SIUL2GPIO[48]
General Purpose IO D[0]
I/O
0001
FR_A_TX
FLEXRAY
FlexRay Transmit Data
Channel A
O
0010
ETC1
eTimer_1
eTimer_1 Input/Output Data
Channel 1
I/O
0011
B1
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 1
I/O
0100-1111
—
Reserved
—
—
IMCR[66]
0010
ETC1
eTimer_1
eTimer_1 Input Data Channel 1 I
IMCR[92]
0010
B1
FlexPWM_0
FlexPWM_0 Channel B Input 1 I
MSCR[49]
0000
(Default)
GPIO[49]
SIUL2GPIO[49]
General Purpose IO D[1]
I/O
0001
—
Reserved
—
—
0010
ETC2
eTimer_1
eTimer_1 Input/Output Data
Channel 2
I/O
0011
EXT_TGR
CTU_0
CTU 0 External Trigger Output
O
0100-1111
—
Reserved
—
—
IMCR[67]
0011
ETC2
eTimer_1
eTimer_1 Input Data Channel 2 I
IMCR[136]
0001
FR_A_RX
FLEXRAY
FlexRay Channel A Receive
Pin
I
MSCR[50]
0000
(Default)
GPIO[50]
SIUL2GPIO[50]
General Purpose IO D[2]
I/O
0001
—
Reserved
—
—
0010
ETC3
eTimer_1
eTimer_1 Input/Output Data
Channel 3
I/O
0011
X3
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 3
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
124
A8
125
B8
3
E3
140
B4
I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
25
Pinouts
D[3]
D[4]
D[5]
D[6]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0100-1111
—
Reserved
—
IMCR[68]
0010
ETC3
eTimer_1
eTimer_1 Input Data Channel 3 I
IMCR[99]
0001
X3
FlexPWM_0
FlexPWM_0 Auxiliary Input 3
I
IMCR[137]
0001
FR_B_RX
FLEXRAY
FlexRay Channel B Receive
Pin
I
MSCR[51]
0000
(Default)
GPIO[51]
SIUL2GPIO[51]
General Purpose IO D[3]
I/O
0001
FR_B_TX
FLEXRAY
FlexRay Transmit Data
Channel B
O
0010
ETC4
eTimer_1
eTimer_1 Input/Output Data
Channel 4
I/O
0011
A3
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 3
I/O
0100-1111
—
Reserved
—
—
IMCR[69]
0010
ETC4
eTimer_1
eTimer_1 Input Data Channel 4 I
IMCR[97]
0011
A3
FlexPWM_0
FlexPWM_0 Channel A Input 3 I
MSCR[52]
0000
(Default)
GPIO[52]
SIUL2GPIO[52]
General Purpose IO D[4]
I/O
0001
FR_B_TXEN
FLEXRAY
FlexRay Transmit Enable
Channel B
O
0010
ETC5
eTimer_1
eTimer_1 Input/Output Data
Channel 5
I/O
0011
B3
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 3
I/O
0100-1111
—
Reserved
—
—
IMCR[70]
0011
ETC5
eTimer_1
eTimer_1 Input Data Channel 5 I
IMCR[98]
0011
B3
FlexPWM_0
FlexPWM_0 Channel B Input 3 I
MSCR[53]
0000
(Default)
GPIO[53]
SIUL2GPIO[53]
General Purpose IO D[5]
I/O
0001
CS3
DSPI0
DSPI 0 Peripheral Chip Select
3
O
0010
—
Reserved
—
—
0100
SOUT
DSPI3
DSPI 3 Serial Data Out
O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
—
0101-1111
—
Reserved
—
—
IMCR[85]
0001
FAULT2
FlexPWM_0
FlexPWM_0 Fault Input 2
I
IMCR[205]
0001
SENT_RX[0]
SENT0
SENT 0 Receiver channel 0
I
IMCR[227]
0001
RX_D1
ENET_0
Ethernet MII/RMII receive data
1
I
MSCR[54]
0000
(Default)
GPIO[54]
SIUL2GPIO[54]
General Purpose IO D[6]
I/O
128
A5
129
B7
33
M4
34
P3
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
26
NXP Semiconductors
Pinouts
D[7]
D[8]
D[9]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0001
CS2
DSPI0
DSPI 0 Peripheral Chip Select
2
O
0010
—
Reserved
—
—
0011
X3
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 3
I/O
0100
SCK
DSPI3
DSPI 3 Input/Output Serial
Clock
I/O
0101-1111
—
Reserved
—
—
IMCR[51]
0001
SCK
DSPI3
DSPI 3 Input Serial Clock
I
IMCR[84]
0010
FAULT1
FlexPWM_0
FlexPWM_0 Fault Input 1
I
IMCR[99]
0010
X3
FlexPWM_0
FlexPWM_0 Channel X Input 3 I
IMCR[226]
0001
RX_D0
ENET_0
Ethernet MII/RMII receive data
0
I
MSCR[55]
0000
(Default)
GPIO[55]7
SIUL2GPIO[55]
General Purpose IO D[7]
I/O
0001
CS3
DSPI1
DSPI 1 Peripheral Chip Select
3
O
0010
—
Reserved
—
—
0011
CS4
DSPI0
DSPI 0 Peripheral Chip Select
4
O
0100-1111
—
Reserved
—
—
IMCR[50]
0010
SIN
DSPI3
DSPI 3 Serial Data Input
I
IMCR[213]
0001
SENT_RX[0]
SENT1
SENT 1 Receiver channel 0
I
IMCR[225]
0001
RX_DV
ENET_0
Ethernet Receive data valid
I
MSCR[56]
0000
(Default)
GPIO[56]
SIUL2GPIO[56]
General Purpose IO D[8]
I/O
0001
CS2
DSPI1
DSPI 1 Peripheral Chip Select
2
O
0010
ETC4
eTimer_1
eTimer_1 Input/Output Data
Channel 4
I/O
0011
CS5
DSPI0
DSPI 0 Peripheral Chip Select
5
O
0100-1111
—
Reserved
—
—
IMCR[69]
0011
ETC4
eTimer_1
eTimer_1 Input Data Channel 4 I
IMCR[86]
0010
FAULT3
FlexPWM_0
FlexPWM_0 Fault Input 3
I
IMCR[224]
0001
RX_CLK
ENET_0
Ethernet Receive clock
I
MSCR[57]
0000
(Default)
GPIO[57]
SIUL2GPIO[57]
General Purpose IO D[9]
I/O
0001
X0
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 0
I/O
0010
TXD
LIN1
LINFlexD 1 Transmit Pin
O
SGEN
OUT8
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
37
R4
32
L4
26
N3
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
27
Pinouts
D[10]
D[11]
D[12]
D[14]
SIUL2 MSCR/
IMCR
Number
MSCR[58]
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[58]
SIUL2GPIO[58]
General Purpose IO D[10]
I/O
0001
A0
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 0
I/O
0010
—
Reserved
—
—
0011
TX_D2
ENET_0
Ethernet MII transmit data
O
0100
CS0
DSPI3
DSPI 3 Peripheral Chip Select
0
I/O
—
0110-1111
—
Reserved
—
IMCR[52]
0010
CS0
DSPI3
DSPI 3 Peripheral chip Select 0 I
IMCR[59]
0001
ETC0
eTimer_0
eTimer_0 Input Data Channel 0 I
IMCR[88]
0010
A0
FlexPWM_0
FlexPWM_0 Channel A Input 0 I
MSCR[59]
0000
(Default)
GPIO[59]
SIUL2GPIO[59]
General Purpose IO D[11]
I/O
0001
B0
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 0
I/O
0010
—
Reserved
—
—
0011
CS1
DSPI3
DSPI 3 Peripheral Chip Select
1
O
0100
SCK
DSPI3
DSPI 3 Input/Output Serial
Clock
I/O
0101-1111
—
Reserved
—
—
IMCR[51]
0010
SCK
DSPI3
DSPI 3 Input Serial Clock
I
IMCR[60]
0001
ETC1
eTimer_0
eTimer_0 Input Data Channel 1 I
IMCR[89]
0010
B0
FlexPWM_0
FlexPWM_0 Channel B Input 0 I
MSCR[60]
0000
(Default)
GPIO[60]
SIUL2GPIO[60]
General Purpose IO D[12]
I/O
0001
X1
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 1
I/O
0010
CS6
DSPI1
DSPI 1 Peripheral Chip Select
6
O
0011
CS2
DSPI3
DSPI 3 Peripheral Chip Select
2
O
0100
SOUT
DSPI3
DSPI 3 Serial Data Output
O
0101-1111
—
Reserved
—
—
IMCR[93]
0010
X1
FlexPWM_0
FlexPWM_0 Channel X Input 1 I
IMCR[166]
0010
RXD
LIN1
LIN 1 Receive Pin
I
MSCR[62]
0000
(Default)
GPIO[62]
SIUL2GPIO[62]
General Purpose IO D[14]
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
76
R16
78
P17
99
F15
105
E17
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
28
NXP Semiconductors
Pinouts
E[0]
E[2]
E[4]
E[5]
E[6]
E[7]
E[9]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0001
B1
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 1
I/O
0010
—
Reserved
—
—
0011
CS3
DSPI3
DSPI 3 Peripheral Chip Select
3
O
0100-1111
—
Reserved
—
—
IMCR[50]
0011
SIN
DSPI3
DSPI 3 Serial Data Input
I
IMCR[62]
0001
ETC3
eTimer_0
eTimer_0 Input Data Channel 3 I
IMCR[92]
0011
B1
FlexPWM_0
FlexPWM_0 Channel B Input 1 I
0000
(Default)
GPI[64]4
SIUL2-GPI[64] General Purpose Input E[0]
I
MSCR[64]
MSCR[66]
MSCR[68]
MSCR[69]
MSCR[70]
MSCR[71]
MSCR[73]
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
68
T13
49
U6
42
U4
44
T5
46
R6
48
T6
61
U10
ADC1_AN[5]/
ADC3_AN[4]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[66]4
SIUL2-GPI[66] General Purpose Input E[2]
I
ADC0_AN[5]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[68]4
SIUL2-GPI[68] General Purpose Input E[4]
I
ADC0_AN[7]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[69]4
SIUL2-GPI[69] General Purpose Input E[5]
I
ADC0_AN[8]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[70]4
SIUL2-GPI[70] General Purpose Input E[6]
I
ADC0_ADC2_A
N[4]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[71]4
SIUL2-GPI[71] General Purpose Input E[7]
I
ADC0_AN[6]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
GPI[73]4
ADC1_AN[7]/
ADC3_AN[6]
SIUL2-GPI[73] General Purpose Input E[9]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
29
Pinouts
E[10]
E[11]
E[12]
E[13]
E[14]
SIUL2 MSCR/
IMCR
Number
MSCR[74]
MSCR[75]
MSCR[76]
MSCR[77]
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0000
(Default)
GPI[74]4
ADC1_AN[8]/
ADC3_AN[7]
SIUL2-GPI[74] General Purpose Input E[10]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[75]4
SIUL2-GPI[75] General Purpose Input E[11]
I
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
63
T11
65
U11
67
T12
117
A11
119
B10
ADC1_AN[4]/
ADC3_AN[3]
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPI[76]4
ADC1_AN[6]/
ADC3_AN[5]
SIUL2-GPI[76] General Purpose Input E[12]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0000
(Default)
GPIO[77]
SIUL2GPIO[77]
General Purpose IO E[13]
I/O
0001
ETC5
eTimer_0
eTimer_0 Input/Output Data
Channel 5
I/O
0010
CS3
DSPI2
DSPI 2 Peripheral Chip Select
3
O
0011
CS4
DSPI1
DSPI 1 Peripheral Chip Select
4
O
0100
SCK
DSPI3
DSPI 3 Input/Output Serial
Clock
I/O
0101-1111
—
Reserved
—
—
IMCR[51]
0011
SCK
DSPI3
DSPI 3 Input Serial Clock
I
IMCR[198]
0001
REQ25
SIUL2
SIUL2 External Interrupt
Source 25
I
IMCR[64]
0100
ETC5
eTimer_0
eTimer_0 Input Data Channel
I
MSCR[78]
0000
(Default)
GPIO[78]
SIUL2GPIO[78]
General Purpose IO E[14]
I/O
0001
ETC5
eTimer_1
eTimer_1 Input/Output Data
Channel 5
I/O
0010
SOUT
DSPI3
DSPI 3 Serial Data Out
O
0011
CS5
DSPI1
DSPI 1 Peripheral Chip Select
5
O
0100
B2
FlexPWM_1
FlexPWM_1 Channel B Input/
Output 2
I/O
0101-1111
—
Reserved
—
—
IMCR[70]
0100
ETC5
eTimer_1
eTimer_1 Input Data Channel 5 I
IMCR[113]
0001
B2
FlexPWM_1
FlexPWM_1 Channel B Input 2 I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
30
NXP Semiconductors
Pinouts
E[15]
F[0]
F[3]
F[4]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
IMCR[199]
0001
REQ26
SIUL2
SIUL2 External Interrupt
Source 26
I
MSCR[79]
0000
(Default)
GPIO[79]
SIUL2GPIO[79]
General Purpose IO E[15]
I/O
0001
CS1
DSPI0
DSPI 0 Peripheral Chip Select
1
O
0010
—
Reserved
—
—
0011
TIMER1
ENET_0
Ethernet TIMER Outputs
(Output Compare Events)
O
0100-1111
—
Reserved
—
—
IMCR[50]
0100
SIN
DSPI3
DSPI 3 Serial Data Input
I
IMCR[200]
0001
REQ27
SIUL2
SIUL2 External Interrupt
Source 27
I
MSCR[80]
0000
(Default)
GPIO[80]
SIUL2GPIO[80]
General Purpose IO F[0]
I/O
0001
A1
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 1
I/O
0010
CS3
DSPI3
DSPI 3 Peripheral Chip Select
3
O
0011
MDC
ENET_0
Ethernet MDIO clock output
O
—
0100-1111
—
Reserved
—
IMCR[61]
0001
ETC2
eTimer_0
eTimer_0 Input Data Channel 2 I
IMCR[91]
0011
A1
FlexPWM_0
FlexPWM_0 Channel A Input 1 I
IMCR[201]
0001
REQ28
SIUL2
SIUL2 External Interrupt
Source 28
I
MSCR[83]
0000
(Default)
GPIO[83]
SIUL2GPIO[83]
General Purpose IO F[3]
I/O
0001
CS6
DSPI0
DSPI 0 Peripheral Chip Select
6
O
0010
—
Reserved
—
—
0011
CS2
DSPI3
DSPI 3 Peripheral Chip Select
2
O
0100
TIMER2
ENET_0
Ethernet TIMER Outputs 2
(Output Compare Events)
O
0101-1111
—
Reserved
—
—
0000
(Default)
GPIO[84]
SIUL2GPIO[84]
General Purpose IO F[4]
I/O
0001
—
Reserved
—
O
0010
MDO[3]
NPC_WRAPP
ER
Nexus - Message Data Out Pin O
3
0011
CS1
DSPI3
DSPI 3 Peripheral Chip Select
1
MSCR[84]
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
121
C8
133
B6
139
B3
4
E1
O
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
31
Pinouts
F[5]
F[6]
F[7]
F[8]
F[9]
F[10]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0100-1111
—
Reserved
—
—
0000
(Default)
GPIO[85]
SIUL2GPIO[85]
General Purpose IO F[5]
I/O
0001
—
Reserved
—
O
0010
MDO[2]
NPC_WRAPP
ER
Nexus Message Data Out Pin 2 O
0011
CS0
DSPI3
DSPI 3 Peripheral Chip Select
0
I/O
0100-1111
—
Reserved
—
—
IMCR[52]
0011
CS0
DSPI3
DSPI 3 Peripheral Chip Select
0
I
MSCR[86]
0000
(Default)
GPIO[86]
SIUL2GPIO[86]
General Purpose IO F[6]
I/O
0001
—
Reserved
—
I/O
0010
MDO[1]
NPC_WRAPP
ER
Nexus Message Data Out Pin 1 O
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[87]
SIUL2GPIO[87]
General Purpose IO F[7]
I/O
0001
—
Reserved
—
I/O
0010
MCKO
NPC_WRAPP
ER
Nexus Message Clock Out for
development tools
O
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[88]
SIUL2GPIO[88]
General Purpose IO F[8]
I/O
0001
—
Reserved
—
I/O
0010
MSEO_B[1]
NPC_WRAPP
ER
Nexus Message Start/End Out
Pin 1
O
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[89]
SIUL2GPIO[89]
General Purpose IO F[9]
I/O
0001
—
Reserved
—
I/O
0010
MSEO_B[0]
NPC_WRAPP
ER
Nexus Message Start/End Out
Pin 0
O
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[90]
SIUL2GPIO[90]
General Purpose IO F[10]
I/O
0001
—
Reserved
—
—
0010
EVTO_B
NPC_WRAPP
ER
Nexus Event Out Pin
O
0011-1111
—
Reserved
—
—
MSCR[85]
MSCR[87]
MSCR[88]
MSCR[89]
MSCR[90]
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
5
F1
8
E2
19
J4
20
J3
23
K3
24
K2
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
32
NXP Semiconductors
Pinouts
F[11]
F[12]
F[13]
F[14]
F[15]
SIUL2 MSCR/
IMCR
Number
MSCR[91]
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0000
(Default)
GPIO[91]
SIUL2GPIO[91]
General Purpose IO F[11]
I/O
0001
—
Reserved
—
—
0010
EVTI_IN
NPC_WRAPP
ER
Nexus Event In Pin
I
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[92]
SIUL2GPIO[92]
General Purpose IO F[12]
I/O
0001
ETC3
eTimer_1
eTimer_1 Input/Output Data
Channel 3
I/O
0010-0011
—
Reserved
—
—
0100
A1
FlexPWM_1
FlexPWM_1 Channel A Input/
Output 1
I/O
0101-1111
—
Reserved
—
—
IMCR[68]
0011
ETC3
eTimer_1
eTimer_1 Input Data Channel 3 I
IMCR[109]
0001
A1
FlexPWM_1
FlexPWM_1 Channel A Input 1 I
IMCR[203]
0001
REQ30
SIUL2
SIUL2 External Interrupt
Source 30
I
MSCR[93]
0000
(Default)
GPIO[93]
SIUL2GPIO[93]
General Purpose IO F[13]
I/O
0001
ETC4
eTimer_1
eTimer_1 Input/Output Data
Channel 4
I/O
0010-0011
—
Reserved
—
—
0100
B1
FlexPWM_1
FlexPWM_1 Channel A Input/
Output 1
I/O
0101-1111
—
Reserved
—
—
IMCR[69]
0100
ETC4
eTimer_1
eTimer_1 Input Data Channel 4 I
IMCR[110]
0001
B1
FlexPWM_1
FlexPWM_1 Channel B Input 1 I
IMCR[204]
0001
REQ31
SIUL2
SIUL2 External Interrupt
Source 31
I
MSCR[94]
0000
(Default)
GPIO[94]
SIUL2GPIO[94]
General Purpose IO F[14]
I/O
0001
TXD
LIN1
LINFlexD 1 Transmit Pin
O
0010
TXD
CAN2
CAN 2 Transmit Pin
O
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[95]
SIUL2GPIO[95]
General Purpose IO F[15]
I/O
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
IMCR[166]
0011
RXD
LIN1
LIN1 RXD
I
IMCR[34]
0001
RXD
CAN2
CAN2 RXD
I
MSCR[92]
MSCR[95]
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
25
L2
106
D17
112
A15
115
D12
113
A13
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
33
Pinouts
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]5
SIUL2 MSCR/
IMCR
Number
MSCR[98]
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0000
(Default)
GPIO[98]
SIUL2GPIO[98]
General Purpose IO G[2]
I/O
0001
X2
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 2
I/O
0010
CS1
DSPI1
DSPI 1 Peripheral Chip Select
1
O
0011-1111
—
Reserved
—
—
IMCR[96]
0010
X2
FlexPWM_0
FlexPWM_0 Auxiliary Input 2
I
MSCR[99]
0000
(Default)
GPIO[99]
SIUL2GPIO[99]
General Purpose IO G[3]
I/O
0001
A2
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 2
I/O
0010-1111
—
Reserved
—
—
IMCR[63]
0010
ETC4
eTimer_0
eTimer_0 Input Data Channel 4 I
IMCR[94]
0011
A2
FlexPWM_0
FlexPWM_0 Channel A Input 2 I
MSCR[100]
0000
(Default)
GPIO[100]
SIUL2GPIO[100]
General Purpose IO G[4]
I/O
0001
B2
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 2
I/O
0010-1111
—
Reserved
—
—
IMCR[64]
0010
ETC5
eTimer_0
eTimer_0 Input Data Channel 5 I
IMCR[95]
0011
B2
FlexPWM_0
FlexPWM_0 Channel B Input 2 I
MSCR[101]
0000
(Default)
GPIO[101]
SIUL2GPIO[101]
General Purpose IO G[5]
I/O
0001
X3
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 3
I/O
0010
CS3
DSPI2
DSPI 2 Peripheral Chip Select
3
O
0011
TX_EN
ENET_0
Ethernet Transmit Data Valid
O
0100-1111
—
Reserved
—
—
IMCR[99]
0011
X3
FlexPWM_0
FlexPWM_0 Auxiliary Input 3
I
MSCR[102]
0000
(Default)
GPIO[102]
SIUL2GPIO[102]
General Purpose IO G[6]
I/O
0001
A3
FlexPWM_0
FlexPWM_0 Channel A Input/
Output 3
I/O
0010-1111
—
Reserved
—
—
IMCR[97]
0100
A3
FlexPWM_0
FlexPWM_0 Channel A Input 3 I
MSCR[103]
0000
(Default)
GPIO[103]
SIUL2GPIO[103]
General Purpose IO G[7]9
I/O
0001
B3
FlexPWM_0
FlexPWM_0 Channel B Input/
Output 3
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
102
F17
104
E16
100
F16
85
M17
98
G17
83
M16
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
34
NXP Semiconductors
Pinouts
G[8]
G[9]
G[10]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0010
—
Reserved
—
—
0011
LFAST_RXP
LFAST
SIPI/LFAST LVDS receive
positive terminal
I
—
0100-1111
—
Reserved
—
IMCR[98]
0100
B3
FlexPWM_0
FlexPWM_0 Channel B Input 3 I
MSCR[104]
0000
(Default)
GPIO[104]
SIUL2GPIO[104]
General Purpose IO G[8]
0001
FR_DBG[0]
FLEXRAY
FlexRay Debug Strobe Signal 0 O
0010
CS1
DSPI0
DSPI 0 Peripheral Chip Select
1
O
0011
RMII_CLK
ENET_0
Ethernet RMII Clock (used in
MII to RMII Gaskets)
O
0100-1111
—
Reserved
—
—
IMCR[83]
0011
FAULT0
FlexPWM_0
FlexPWM_0 Fault Input 0
I
IMCR[194]
0001
REQ21
SIUL2
SIUL2 External Interrupt
Source 21
I
IMCR[205]
0011
SENT_RX[0]
SENT_0
SENT 0 Receiver channel 0
I
IMCR[233]
0001
TX_CLK
ENET_0
Ethernet Transmit Clock
I
MSCR[105]
0000
(Default)
GPIO[105]
SIUL2GPIO[105]
General Purpose IO G[9]
I/O
0001
FR_DBG[1]
FLEXRAY
FlexRay Debug Strobe Signal 1 O
0010
CS1
DSPI1
DSPI 1 Peripheral Chip Select
1
0011
TX_D0
ENET_0
Ethernet MII/RMII transmit data O
0
0100-1111
—
Reserved
—
—
IMCR[84]
0011
FAULT1
FlexPWM_0
FlexPWM_0 Fault Input 1
I
IMCR[202]
0001
REQ29
SIUL2
SIUL2 External Interrupt
Source 29
I
IMCR[213]
0011
SENT_RX[0]
SENT_1
SENT 1 Receiver channel 0
I
MSCR[106]
0000
(Default)
GPIO[106]
SIUL2GPIO[106]
General Purpose IO G[10]
I/O
0001
FR_DBG[2]
FLEXRAY
FlexRay Debug Strobe Signal 2 O
0010
CS3
DSPI2
DSPI 2 Peripheral Chip Select
3
0011
TX_D1
ENET_0
Ethernet MII/RMII transmit data O
1
0100-1111
—
Reserved
—
—
IMCR[85]
0010
FAULT2
FlexPWM_0
FlexPWM_0 Fault Input 2
I
IMCR[206]
0100
SENT_RX[1]
SENT_0
SENT 0 Receiver channel 1
I
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
81
N14
79
P14
77
R17
O
O
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
35
Pinouts
G[11]
H[4]
H[5]
H[6]
H[7]
SIUL2 MSCR/
IMCR
Number
MSCR[107]
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0000
(Default)
GPIO[107]
SIUL2GPIO[107]
General Purpose IO G[11]
I/O
0001
FR_DBG[3]
FLEXRAY
FlexRay Debug Strobe Signal 3 O
0010
—
Reserved
—
0011
TX_D3
ENET_0
Ethernet MII/RMII transmit data O
3
0100-1111
—
Reserved
—
—
IMCR[86]
0011
FAULT3
FlexPWM_0
FlexPWM_0 Fault Input 3
I
IMCR[214]
0100
SENT_RX[1]
SENT_1
SENT 1 Receiver channel 1
I
MSCR[116]
0000
(Default)
GPIO[116]
SIUL2GPIO[116]
General Purpose IO H[4]
I/O
0001
X0
FlexPWM_1
FlexPWM_1 Auxiliary Input/
Output 0
I/O
0010
ETC0
eTimer_2
eTimer_2 Input/Output Data
Channel 0
I/O
—
75
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
T15
—
0011-1111
—
Reserved
—
IMCR[71]
0001
ETC0
eTimer_2
eTimer_2 Input Data Channel 0 I
IMCR[231]
0001
CRS
ENET_0
Ethernet MII Carrier Sense
I
MSCR[117]
0000
(Default)
GPIO[117]
SIUL2GPIO[117]
General Purpose IO H[5]
I/O
0001
A0
FlexPWM_1
FlexPWM_1 Channel A Input/
Output 0
I/O
0010
—
Reserved
—
—
0011
CS4
DSPI0
DSPI 0 Peripheral Chip Select
4
O
0100-1111
—
Reserved
—
—
IMCR[105]
0010
A0
FlexPWM_1
FlexPWM_1 Channel A Input 0 I
IMCR[230]
0001
COL
ENET_0
Ethernet MII Collision
I
MSCR[118]
0000
(Default)
GPIO[118]
SIUL2GPIO[118]
General Purpose IO H[6]
I/O
0001
B0
FlexPWM_1
FlexPWM_1 Channel B Input/
Output 0
I/O
0010
—
Reserved
—
—
0011
CS5
DSPI0
DSPI 0 Peripheral Chip Select
5
O
0100-1111
—
Reserved
—
—
IMCR[106]
0010
B0
FlexPWM_1
FlexPWM_1 Channel B Input 0 I
MSCR[119]
0000
(Default)
GPIO[119]
SIUL2GPIO[119]
General Purpose IO H[7]
I/O
0001
X1
FlexPWM_1
FlexPWM_1 Auxiliary Input/
Output 1
I/O
F4
F3
C13
F2
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
36
NXP Semiconductors
Pinouts
H[8]
H[9]
H[10]
H[11]
H[12]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0010
ETC1
eTimer_2
eTimer_2 Input/Output Data
Channel 1
I/O
0011
MDIO
ENET_0
Ethernet MDIO input/output
data
I/O
0100-1111
—
Reserved
—
—
IMCR[72]
0001
ETC1
eTimer_2
eTimer_2 Input Data Channel 1 I
MSCR[120]
0000
(Default)
GPIO[120]
SIUL2GPIO[120]
General Purpose IO H[8]
I/O
0001
A1
FlexPWM_1
FlexPWM_1 Channel A Input/
Output 1
I/O
0010
—
Reserved
—
—
0011
CS6
DSPI0
DSPI 0 Peripheral Chip Select
6
O
0100-1111
—
Reserved
—
—
IMCR[109]
0010
A1
FlexPWM_1
FlexPWM_1 Channel A Input 1 I
IMCR[228]
0001
RX_D2
ENET_0
Ethernet MII Receive Data 2
I
MSCR[121]
0000
(Default)
GPIO[121]
SIUL2GPIO[121]
General Purpose IO H[9]
I/O
0001
B1
FlexPWM_1
FlexPWM_1 Channel B Input/
Output 1
I/O
0010
—
Reserved
—
—
0011
CS7
DSPI0
DSPI 0 Peripheral Chip Select
7
O
0100-1111
—
Reserved
—
—
IMCR[110]
0010
B1
FlexPWM_1
FlexPWM_1 Channel B Input 1 I
MSCR[122]
0000
(Default)
GPIO[122]
SIUL2GPIO[122]
General Purpose IO H[10]
I/O
0001
X2
FlexPWM_1
FlexPWM_1 Auxiliary Input/
Output 2
I/O
0010
ETC2
eTimer_2
eTimer_2 Input/Output Data
Channel 2
I/O
0011-1111
—
Reserved
—
—
IMCR[73]
0010
ETC2
eTimer_2
eTimer_2 Input Data Channel 2 I
MSCR[123]
0000
(Default)
GPIO[123]
SIUL2GPIO[123]
General Purpose IO H[11]
I/O
0001
A2
FlexPWM_1
FlexPWM_1 Channel A Input/
Output 2
I/O
0010-1111
—
Reserved
—
—
IMCR[112]
0010
A2
FlexPWM_1
FlexPWM_1 Channel A Input 2 I
MSCR[124]
0000
(Default)
GPIO[124]
SIUL2GPIO[124]
General Purpose IO H[12]
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
L1
B13
C7
C9
A7
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
37
Pinouts
H[13]
H[14]
H[15]
I[0]
I[1]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0001
B2
FlexPWM_1
FlexPWM_1 Channel B Input/
Output 2
I/O
0010-1111
—
Reserved
—
—
IMCR[113]
0010
B2
FlexPWM_1
FlexPWM_1 Channel B Input 2 I
MSCR[125]
0000
(Default)
GPIO[125]
SIUL2GPIO[125]
General Purpose IO H[13]
I/O
0001
X3
FlexPWM_1
FlexPWM_1 Auxiliary Input/
Output 3
I/O
0010
ETC3
eTimer_2
eTimer_2 Input/Output Data
Channel 3
I/O
0011-1111
—
Reserved
—
—
IMCR[74]
0010
ETC3
eTimer_2
eTimer_2 Input Data Channel 3 I
MSCR[126]
0000
(Default)
GPIO[126]
SIUL2GPIO[126]
General Purpose IO H[14]
I/O
0001
A3
FlexPWM_1
FlexPWM_1 Channel A Input/
Output 3
I/O
0010
ETC4
eTimer_2
eTimer_2 Input/Output Data
Channel 4
I/O
0011-1111
—
Reserved
—
—
IMCR[75]
0010
ETC4
eTimer_2
eTimer_2 Input Data Channel 4 I
MSCR[127]
0000
(Default)
GPIO[127]
SIUL2GPIO[127]
General Purpose IO H[15]
I/O
0001
B3
FlexPWM_1
FlexPWM_1 Channel B Input/
Output 3
I/O
0010
ETC5
eTimer_2
eTimer_2 Input/Output Data
Channel 5
I/O
—
0011-1111
—
Reserved
—
IMCR[76]
0010
ETC5
eTimer_2
eTimer_2 Input Data Channel 5 I
MSCR[128]
0000
(Default)
GPIO[128]
SIUL2GPIO[128]
General Purpose IO I[0]
I/O
0001
ETC0
eTimer_2
eTimer_2 Input/Output Data
Channel 0
I/O
0010
CS4
DSPI0
DSPI 0 Peripheral Chip Select
4
O
0011-1111
—
Reserved
—
—
IMCR[71]
0010
ETC0
eTimer_2
eTimer_2 Input Data Channel 0 I
IMCR[100]
0001
FAULT0
FlexPWM_1
FlexPWM_1 Fault Input 0
I
MSCR[129]
0000
(Default)
GPIO[129]
SIUL2GPIO[129]
General Purpose IO I[1]
I/O
0001
ETC1
eTimer_2
eTimer_2 Input/Output Data
Channel 1
I/O
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
A14
P13
C17
C6
T3
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
38
NXP Semiconductors
Pinouts
I[2]
I[3]
SIUL2 MSCR/
IMCR
Number
Signal
Module
Short Signal Description
Dir
0010
CS5
DSPI0
DSPI 0 Peripheral Chip Select
5
O
0011-1111
—
Reserved
—
—
IMCR[72]
0010
ETC1
eTimer_2
eTimer_2 Input Data Channel 1 I
IMCR[101]
0001
FAULT1
FlexPWM_1
FlexPWM_1 Fault Input 1
I
IMCR[232]
0001
RX_ER
ENET_0
Ethernet Receive Data Error
I
MSCR[130]
0000
(Default)
GPIO[130]
SIUL2GPIO[130]
General Purpose IO I[2]
I/O
0001
ETC2
eTimer_2
eTimer_2 Input/Output Data
Channel 2
I/O
0010
CS6
DSPI0
DSPI 0 Peripheral Chip Select
6
O
0011-1111
—
Reserved
—
—
IMCR[73]
0011
ETC2
eTimer_2
eTimer_2 Input Data Channel 2 I
IMCR[102]
0001
FAULT2
FlexPWM_1
FlexPWM_1 Fault Input 2
I
MSCR[131]
0000
(Default)
GPIO[131]
SIUL2GPIO[131]
General Purpose IO I[3]
I/O
0001
ETC3
eTimer_2
eTimer_2 Input/Output Data
Channel 3
I/O
0010
CS7
DSPI0
DSPI 0 Peripheral Chip Select
7
O
0011
EXT_TGR
CTU_0
CTU0 External Trigger Output
O
0100
TIMER0
ENET_0
Ethernet TIMER Outputs 0
(Output Compare Events)
O
0101-1111
—
Reserved
—
—
IMCR[74]
0011
ETC3
eTimer_2
eTimer_2 Input Data Channel 3 I
IMCR[103]
0001
FAULT3
FlexPWM_1
FlexPWM_1 Fault Input 3
I
0000
(Default)
GPIO[132]
SIUL2GPIO[132]
General Purpose IO I[4]
I/O
0001
—
Reserved
—
—
0010
NEX_RDY_B
NPC_WRAPP
ER
Nexus data ready for transfer
(RDY_B)
O
0011-1111
—
Reserved
—
—
RDY_ MSCR[132]
B/I[4]
I[5]5
MSCR/
IMCR SSS
Value1
MSCR[133]
I[5]10
0000
(Default)
GPIO[133]
SIUL2GPIO[133]
General Purpose IO
I/O
0001
TXD
CAN2
CAN 2 Transmit Pin
O
0010
—
Reserved
—
—
0011
LFAST_TXN
LFAST
SIPI/LFAST LVDS transmit
negative terminal
O
0100-1111
—
Reserved
—
—
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
D11
A10
J2
N15
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
39
Pinouts
I[6]5
I[7]
I[8]
I[9]
I[10]
I[11]
I[12]
SIUL2 MSCR/
IMCR
Number
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0000
(Default)
GPIO[134]
SIUL2GPIO[134]
General Purpose IO I[6]11
I/O
0001
—
Reserved
—
—
0010
—
Reserved
—
—
0011
LFAST_RXN
LFAST
SIPI/LFAST LVDS receive
negative terminal
I
0100-1111
—
Reserved
—
—
IMCR[34]
0010
RXD
CAN2
CAN 2 Receive Pin
I
MSCR[135]
0000
(Default)
GPIO[135]
SIUL2GPIO[135]
General Purpose IO I[7]
I/O
0001
LFAST_REF_C MC_CGM
LK
SIPI/LFAST Input/Output
reference clock
I/O
0010-1111
—
Reserved
—
—
IMCR[205]
0010
SENT_RX[0]
SENT0
SENT 0 Receiver channel 0
I
MSCR[136]
0000
(Default)
GPIO[136]
SIUL2GPIO[136]
General Purpose IO I[8]
I/O
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
IMCR[213]
0010
SENT_RX[0]
SENT1
SENT 1 Receiver channel 0
I
MSCR[137]
0000
(Default)
GPIO[137]
SIUL2GPIO[137]
General Purpose IO I[9]
I/O
0001
ETC4
eTimer_2
eTimer_2 Input/Output Data
Channel 4
I/O
0010-1111
—
Reserved
—
—
IMCR[75]
0011
ETC4
eTimer_2
eTimer_2 Input Data Channel 4 I
MSCR[138]
0000
(Default)
GPIO[138]
SIUL2GPIO[138]
General Purpose IO I[10]
I/O
0001
ETC5
eTimer_2
eTimer_2 Input/Output Data
Channel 5
I/O
0010-1111
—
Reserved
—
—
IMCR[76]
0011
ETC5
eTimer_2
eTimer_2 Input Data Channel 5 I
MSCR[139]
0000
(Default)
GPIO[139]
SIUL2GPIO[139]
General Purpose IO I[11]
I/O
0001
—
Reserved
—
—
MSCR[134]
0010-1111
—
Reserved
—
—
IMCR[206]
0001
SENT_RX[1]
SENT0
SENT 0 Receiver channel 1
I
MSCR[140]
0000
(Default)
GPIO[140]
SIUL2GPIO[140]
General Purpose IO I[12]
I/O
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0001
SENT_RX[1]
SENT1
SENT 1 Receiver channel 1
I
IMCR[214]
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
M15
D2
K4
L3
M3
U3
P5
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
40
NXP Semiconductors
Pinouts
I[13]
I[14]
I[15]
J[0]
J[1]
J[2]
J[3]
J[4]
SIUL2 MSCR/
IMCR
Number
MSCR[141]
MSCR/
IMCR SSS
Value1
Signal
Module
Short Signal Description
Dir
0000
GPIO[141]
SIUL2GPIO[141]
General Purpose IO I[13]
I/O
0001
EXT_TGR
CTU_1
CTU1 External Trigger Output
O
0010-1111
—
Reserved
—
—
0000
(Default)
GPIO[142]
SIUL2GPIO[142]
General Purpose IO I[14]
I/O
0001
CS0
DSPI3
DSPI 3 Peripheral Chip Select
0
I/O
0010-1111
—
Reserved
—
—
IMCR[52]
0100
CS0
DSPI3
DSPI 3 Peripheral Chip Select
0
I
MSCR[143]
0000
(Default)
GPIO[143]
SIUL2GPIO[143]
General Purpose IO I[15]
I/O
0001
SCK
DSPI3
DSPI 3 Input/Output Serial
Clock
I/O
0010-1111
—
Reserved
—
—
IMCR[51]
0100
SCK
DSPI3
DSPI 3 Input Peripheral Serial
Clock
I
MSCR[144]
0000
(Default)
GPIO[144]
SIUL2GPIO[144]
General Purpose IO J[0]
I/O
0001
SOUT
DSPI3
DSPI 3 Serial Data Out
O
0010-1111
—
Reserved
—
—
0000
(Default)
GPIO[145]
SIUL2GPIO[145]
General Purpose IO J[1]
I/O
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
IMCR[50]
0001
SIN
DSPI3
DSPI 3 Serial Data Input
I
MSCR[146]
0000
(Default)
GPIO[146]
SIUL2GPIO[146]
General Purpose IO J[2]
I/O
0001
CS1
DSPI3
DSPI 3 Peripheral Chip Select
1
O
0010-1111
—
Reserved
—
—
0000
(Default)
GPIO[147]
SIUL2GPIO[147]
General Purpose IO J[3]
I/O
0001
CS2
DSPI3
DSPI 3 Peripheral Chip Select
2
O
0010-1111
—
Reserved
—
—
0000
(Default)
GPIO[148]
SIUL2GPIO[148]
General Purpose IO J[4]
I/O
0001
CS3
DSPI3
DSPI 3 Peripheral Chip Select
3
O
0010-1111
—
Reserved
—
—
MSCR[142]
MSCR[145]
MSCR[147]
MSCR[148]
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
P6
C10
C1
C2
A12
C11
B15
D13
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
41
Pinouts
SIUL2 MSCR/
IMCR
Number
IMCR[39]
J[5]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0010
SENT_RX[1]
SENT0
SENT 0 Receiver channel 1
I
0000
(Default)
GPI[150]4
SIUL2ADC2_ADC3_A GPI[150]
N[1]
General Purpose Input J[6]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
0010
SENT_RX[1]
SENT1
SENT 1 Receiver channel 1
I
0000
(Default)
GPI[151]4
SIUL2ADC2_ADC3_A GPI[151]
N[2]
General Purpose Input J[7]
I
0001
—
Reserved
—
—
0010-1111
—
Reserved
—
—
J[8]
0000
(Default)
GPIO[152]
SIUL2GPIO[152]
General Purpose IO J[8]
I/O
0001
ETC4
eTimer_2
eTimer_2 Input/Output Data
Channel 4
I/O
0010
ETC2
eTimer_2
eTimer_2 Input/Output Data
Channel 2
I/O
0011-1111
—
Reserved
—
—
IMCR[34]
0011
RXD
CAN2
CAN 2 Receive Pin
I
IMCR[73]
0100
ETC2
eTimer_2
eTimer_2 Input Data Channel 2 I
IMCR[75]
0100
ETC4
eTimer_2
eTimer_2 Input Data Channel 4 I
J[9]
MSCR[153]
0000
(Default)
GPIO[153]
SIUL2GPIO[153]
General Purpose IO J[9]
I/O
0001
ETC5
eTimer_2
eTimer_2 Input/Output Data
Channel 5
I/O
0010
NEX_RDY_B
NPC
Nexus data ready for transfer
(RDY_B)
O
0011-1111
—
Reserved
—
—
IMCR[39]
0010
EXT_IN
CTU_1
CTU_1 External Trigger Input
I
IMCR[76]
0100
ETC5
eTimer_2
eTimer_2 Input Data Channel 5 I
IMCR[229]
0001
RX_D3
ENET_0
Ethernet MII Receive Data 3
I
0000
(Default)
NMI_B
Core
Non-Maskable Interrupt
I
MSCR[151]
MSCR[152]
NMI_B MSCR[154]
0000
(Default)
GPI[149]4
CTU_1
Dir
General Purpose Input J[5]
MSCR[150]
EXT_IN
Short Signal Description
SIUL2ADC2_ADC3_A GPI[149]
N[0]
MSCR[149]
0001
Module
I
IMCR[214]
J[7]
Signal
CTU 1 External Trigger Input
IMCR[206]
J[6]
MSCR/
IMCR SSS
Value1
BGA257
Port
Pin
LQFP144
Table 8. Pin muxing (continued)
P8
P9
P10
95
G16
16
K1
1
E4
1. Selecting an alternative function with a "Reserved" source function causes the pin to enter a null state (input buffer and
output buffer enables are both 0).
MPC5744P Data Sheet, Rev. 6.1, 11/2017
42
NXP Semiconductors
Pinouts
(Default) = ALT mode configuration after reset.
Changing the B[5] configuration during debug might affect the availability of TDI.
ADC analog input: Program corresponding MSCR APC bit and enable ADC to switch on the analog input path.
When the LFAST interface is selected the other functionality of the MSCR register is not available.
Shared with SIPI LFAST transmit pad SIPI_TXP. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is
used for SIPI LFAST.
7. To operate D[7] as GPIO, disable the Sine Wave Generator (SGEN) and the peripheral bus clock of the SGEN: Program
the MC_ME_PCTL239 register to select an MC_ME_RUN_PCn (or MC_ME_LP_PCn) configuration where the field for the
desired mode is 0.
8. SGEN output if SGEN is enabled.
9. Shared with SIPI LFAST receive pad SIPI_RXP. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is
used for SIPI LFAST.
10. Shared with SIPI LFAST receive pad SIPI_TXN. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is
used for SIPI LFAST.
11. Shared with SIPI LFAST receive pad SIPI_RXN. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is
used for SIPI LFAST.
2.
3.
4.
5.
6.
The following table list ports that are not implemented. The corresponding control and
data registers are not implemented.
Table 9. Ports - Not Implemented
Port Name
Port Index
C
3,8,9
D
13,15
E
1,3,8
F
1,2
G
0,1,[12:15]
H
[0:3]
J
[10:15]
Any attempt to access unimplemented MSCRs generates a bus error. The read value from
unimplemented ports must be masked in case of parallel port accesses.
2.2.6 Peripheral input muxing
The following table describes the peripheral muxing capabilities of the device.
Table 10. Peripheral muxing
Destination
peripheral
FlexCAN_0
FlexCAN_1
Destination
functions
RXD
RXD
IMCR number
IMCR[32]
IMCR[33]
IMCR[SSS] field value
Source
peripherals
Source functions
0000 (Default)1
—
Disable
0001
I/O-Pad
A[15]
0010
I/O-Pad
B[1]
0011-1111
—
Reserved2
0000 (Default)
—
Disable
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
43
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
FlexCAN_2
CTU_0
CTU_1
DSPI_0
DSPI_1
DSPI_2
DSPI_2
DSPI_2
DSPI_3
Destination
functions
RXD
EXT_IN
EXT_IN
SIN
SIN
SIN
SCK
SC0
SIN
IMCR number
IMCR[34]
IMCR[38]
IMCR[39]
IMCR[41]
IMCR[44]
IMCR[47]
IMCR[48]
IMCR[49]
IMCR[50]
IMCR[SSS] field value
Source
peripherals
Source functions
0001
I/O-Pad
A[15]
0010
I/O-Pad
B[1]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
F[15]
0010
I/O-Pad
I[6]
0011
I/O-Pad
J[8]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[13]
0010
I/O-Pad
C[15]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
J[4]
0010
I/O-Pad
J[9]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[7]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[8]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[13]
0010
I/O-Pad
A[2]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[0]
0010
I/O-Pad
A[11]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[3]
0010
I/O-Pad
A[10]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
J[1]
0010
I/O-Pad
D[7]
0011
I/O-Pad
D[14]
0100
I/O-Pad
E[15]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
44
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
DSPI_3
DSPI_3
eTimer_0
eTimer_0
eTimer_0
eTimer_0
eTimer_0
eTimer_0
Destination
functions
SCK
CS0
ETC0
ETC1
ETC2
ETC3
ETC4
ETC5
IMCR number
IMCR[51]
IMCR[52]
IMCR[59]
IMCR[60]
IMCR[61]
IMCR[62]
IMCR[63]
IMCR[64]
IMCR[SSS] field value
Source
peripherals
Source functions
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[6]
0010
I/O-Pad
D[11]
0011
I/O-Pad
E[13]
0100
I/O-Pad
I[15]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[11]
0010
I/O-Pad
D[10]
0011
I/O-Pad
F[5]
0100
I/O-Pad
I[14]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[10]
0010
I/O-Pad
A[0]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[11]
0010
I/O-Pad
A[1]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
F[0]
0010
I/O-Pad
A[2]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[14]
0010
I/O-Pad
A[3]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[14]
0010
I/O-Pad
G[3]
0011
I/O-Pad
A[4]
0100
I/O-Pad
C[11]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[8]
0010
I/O-Pad
G[4]
0011
I/O-Pad
C[12]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
45
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
eTimer_1
eTimer_1
eTimer_1
eTimer_1
eTimer_1
eTimer_1
eTimer_2
eTimer_2
Destination
functions
ETC0
ETC1
ETC2
ETC3
ETC4
ETC5
ETC0
ETC1
IMCR number
IMCR[65]
IMCR[66]
IMCR[67]
IMCR[68]
IMCR[69]
IMCR[70]
IMCR[71]
IMCR[72]
IMCR[SSS] field value
Source
peripherals
Source functions
0100
I/O-Pad
E[13]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[4]
0010
I/O-Pad
C[15]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[13]
0010
I/O-Pad
D[0]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[0]
0010
I/O-Pad
C[14]
0011
I/O-Pad
D[1]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[1]
0010
I/O-Pad
D[2]
0011
I/O-Pad
F[12]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[14]
0010
I/O-Pad
D[3]
0011
I/O-Pad
D[8]
0100
I/O-Pad
F[13]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[5]
0010
I/O-Pad
A[15]
0011
I/O-Pad
D[4]
0100
I/O-Pad
E[14]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
H[4]
0010
I/O-Pad
I[0]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
H[7]
0010
I/O-Pad
I[1]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
46
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
eTimer_2
eTimer_2
eTimer_2
eTimer_2
FlexPWM_0
FlexPWM_0
FlexPWM_0
FlexPWM_0
Destination
functions
ETC2
ETC3
ETC4
ETC5
FAULT0
FAULT1
FAULT2
FAULT3
IMCR number
IMCR[73]
IMCR[74]
IMCR[75]
IMCR[76]
IMCR[83]
IMCR[84]
IMCR[85]
IMCR[86]
IMCR[SSS] field value
Source
peripherals
Source functions
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[6]
0010
I/O-Pad
H[10]
0011
I/O-Pad
I[2]
0100
I/O-Pad
J[8]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[7]
0010
I/O-Pad
H[13]
0011
I/O-Pad
I[3]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[8]
0010
I/O-Pad
H[14]
0011
I/O-Pad
I[9]
0100
I/O-Pad
J[8]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[9]
0010
I/O-Pad
H[15]
0011
I/O-Pad
I[10]
0100
I/O-Pad
J[9]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[9]
0010
I/O-Pad
A[13]
0011
I/O-Pad
G[8]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[10]
0010
I/O-Pad
D[6]
0011
I/O-Pad
G[9]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[5]
0010
I/O-Pad
G[10]
0011-1111
—
Reserved
0000 (Default)
—
Disable
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
47
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
FlexPWM_0
FlexPWM_0
FlexPWM_0
FlexPWM_0
FlexPWM_0
FlexPWM_0
FlexPWM_0
FlexPWM_0
Destination
functions
EXT_SYNC
A0
B0
A1
B1
X1
A2
B2
IMCR number
IMCR[87]
IMCR[88]
IMCR[89]
IMCR[91]
IMCR[92]
IMCR[93]
IMCR[94]
IMCR[95]
IMCR[SSS] field value
Source
peripherals
Source functions
0001
I/O-Pad
C[5]
0010
I/O-Pad
D[8]
0011
I/O-Pad
G[11]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[13]
0010
I/O-Pad
C[15]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[11]
0010
I/O-Pad
D[10]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[10]
0010
I/O-Pad
D[11]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[7]
0010
I/O-Pad
C[15]
0011
I/O-Pad
F[0]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[6]
0010
I/O-Pad
D[0]
0011
I/O-Pad
D[14]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[4]
0010
I/O-Pad
D[12]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[11]
0010
I/O-Pad
A[12]
0011
I/O-Pad
G[3]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[12]
0010
I/O-Pad
A[13]
0011
I/O-Pad
G[4]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
48
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
FlexPWM_0
FlexPWM_0
FlexPWM_0
FlexPWM_0
FlexPWM_1
FlexPWM_1
FlexPWM_1
FlexPWM_1
FlexPWM_1
FlexPWM_1
Destination
functions
X2
A3
B3
X3
FAULT0
FAULT1
FAULT2
FAULT3
A0
B0
IMCR number
IMCR[96]
IMCR[97]
IMCR[98]
IMCR[99]
IMCR[100]
IMCR[101]
IMCR[102]
IMCR[103]
IMCR[105]
IMCR[106]
IMCR[SSS] field value
Source
peripherals
Source functions
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[10]
0010
I/O-Pad
G[2]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[2]
0010
I/O-Pad
C[10]
0011
I/O-Pad
D[3]
0100
I/O-Pad
G[6]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[3]
0010
I/O-Pad
A[9]
0011
I/O-Pad
D[4]
0100
I/O-Pad
G[7]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[2]
0010
I/O-Pad
D[6]
0011
I/O-Pad
G[5]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
I[0]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
I[1]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
I[2]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
I[3]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[13]
0010
I/O-Pad
H[5]
0011-1111
—
Reserved
0000 (Default)
—
Disable
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
49
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
FlexPWM_1
FlexPWM_1
FlexPWM_1
FlexPWM_1
FlexRay
FlexRay
LIN_0
LIN_1
MC_RGM
MC_RGM
Destination
functions
A1
B1
A2
B2
FR_A_RX
FR_B_RX
RXD
RXD
ABS0
ABS2
IMCR number
IMCR[109]
IMCR[110]
IMCR[112]
IMCR[113]
IMCR[136]
IMCR[137]
IMCR[165]
IMCR[166]
IMCR[169]
IMCR[171]
IMCR[SSS] field value
Source
peripherals
Source functions
0001
I/O-Pad
C[14]
0010
I/O-Pad
H[6]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
F[12]
0010
I/O-Pad
H[8]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
F[13]
0010
I/O-Pad
H[9]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[4]
0010
I/O-Pad
H[11]
0011-1111
—
Reserved
0000
—
Disable
0001
I/O-Pad
E[14]
0010
I/O-Pad
H[12]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[1]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[2]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[3]
0010
I/O-Pad
B[7]
0011-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[13]
0010
I/O-Pad
D[12]
0011
I/O-Pad
F[15]
0100-1111
—
Reserved
0000 (Default)
I/O-Pad
A[2]
0001
—
Disable
0010-1111
—
Reserved
0000 (Default)
I/O-Pad
A[3]
0001
—
Disable
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
50
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
MC_RGM
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
Destination
functions
FAB
REQ0
REQ1
REQ2
REQ3
REQ4
REQ5
REQ6
REQ7
REQ8
REQ9
REQ10
REQ11
IMCR number
IMCR[172]
IMCR[173]
IMCR[174]
IMCR[175]
IMCR[176]
IMCR[177]
IMCR[178]
IMCR[179]
IMCR[180]
IMCR[181]
IMCR[182]
IMCR[183]
IMCR[184]
IMCR[SSS] field value
Source
peripherals
Source functions
0010-1111
—
Reserved
0000 (Default)
I/O-Pad
A[4]
0001
—
Disable
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[0]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[1]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[2]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[3]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[4]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[5]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[6]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[7]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[8]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[10]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[11]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[12]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
51
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
Destination
functions
REQ12
REQ13
REQ14
REQ15
REQ16
REQ17
REQ18
REQ19
REQ20
REQ21
REQ22
REQ23
REQ24
IMCR number
IMCR[185]
IMCR[186]
IMCR[187]
IMCR[188]
IMCR[189]
IMCR[190]
IMCR[191]
IMCR[192]
IMCR[193]
IMCR[194]
IMCR[195]
IMCR[196]
IMCR[197]
IMCR[SSS] field value
Source
peripherals
Source functions
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[13]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[14]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
A[15]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[0]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[1]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[2]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[6]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[14]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
B[15]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
G[8]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[4]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[5]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
C[6]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
52
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SENT_0
SENT_0
SENT_1
Destination
functions
REQ25
REQ26
REQ27
REQ28
REQ29
REQ30
REQ31
SENT_RX[0]
SENT_RX[1]
SENT_RX[0]
IMCR number
IMCR[198]
IMCR[199]
IMCR[200]
IMCR[201]
IMCR[202]
IMCR[203]
IMCR[204]
IMCR[205]
IMCR[206]
IMCR[213]
IMCR[SSS] field value
Source
peripherals
Source functions
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
E[13]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
E[14]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
E[15]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
F[0]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
G[9]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
F[12]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
F[13]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[5]
0010
I/O-Pad
I[7]
0011
I/O-Pad
G[8]
0100-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
I[11]
0010
I/O-Pad
J[5]
0011
I/O-Pad
A[9]
0100
I/O-Pad
G[10]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[7]
0010
I/O-Pad
I[8]
0011
I/O-Pad
G[9]
0100
I/O-Pad
C[12]
0101-1111
—
Reserved
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
53
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
SENT_1
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
Destination
functions
SENT_RX[1]
RX_CLK
RX_DV
RX_D0
RX_D1
RX_D2
RX_D3
COL
CRS
RX_ER
TX_CLK
IMCR number
IMCR[214]
IMCR[224]
IMCR[225]
IMCR[226]
IMCR[227]
IMCR[228]
IMCR[229]
IMCR[230]
IMCR[231]
IMCR[232]
IMCR[233]
IMCR[SSS] field value
Source
peripherals
Source functions
0000 (Default)
—
Disable
0001
I/O-Pad
I[12]
0010
I/O-Pad
J[6]
0011
I/O-Pad
A[10]
0100
I/O-Pad
G[11]
0101-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[8]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[7]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[6]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
D[5]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
H[8]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
J[9]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
H[5]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
H[4]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
I[1]
0010-1111
—
Reserved
0000 (Default)
—
Disable
0001
I/O-Pad
G[8]
0010-1111
—
Reserved
1. (Default) = configuration after reset
2. Selecting an alternate function with a 'Reserved' source function causes the pin to enter a null state (Input buffer and
Output buffer enables both at 0).
MPC5744P Data Sheet, Rev. 6.1, 11/2017
54
NXP Semiconductors
Electrical characteristics
Table 11. Peripheral muxing example
SSS field value in IMCR[214]
Result
0001
I/O-Pad I[12] is connected to SENT_1 Receive input SENT_RX[1]
0010
I/O-Pad J[6] is connected to SENT_1 Receive input SENT_RX[1]
See Table 9 concerning the availability of port pins on the packages.
3 Electrical characteristics
3.1 Introduction
This section contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for this device.
This device is designed to operate at 200 MHz.
3.2 165°C junction temperature option
For orderable parts whose device marking shows they support this extended temperature
option:
• Operation at 150°C < TJ < 165°C is allowed for a maximum cumulative time of 200
hours over the device lifetime.
• Production parameters at 165°C reflect testing over an ambient temperature range of
–40°C to 150°C with appropriate guardbanding to guarantee operation at 165°C.
3.3 Absolute maximum ratings
NOTE
Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maximum values is not
guaranteed.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
55
Electrical characteristics
CAUTION
Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
Table 12. Absolute maximum ratings
Symbol
VDD_LV
VDD_LV_PLL
VDD_LV_LFAST
VDD_LV_NEXUS
VDD_HV_PMU
Parameter
Conditions
voltage1, 2, 3
—
1.25 V PLL supply voltage1, 2, 3
—
1.25 V LFAST PLL supply voltage1, 2, 3
—
—
1.25 V core supply
1.25 V Aurora LVDS supply
voltage1, 2, 3
3.3 V voltage regulator supply voltage
—
Min
Max
Unit
–0.3
1.5
V
–0.3
1.5
V
–0.3
1.5
V
–0.3
1.5
V
–0.3
4.04, 5
V
V
VDD_HV_IO
3.3 V input/output supply voltage
—
–0.3
3.634, 5
VSS_HV_IO
Input/output ground voltage
—
–0.1
0.1
V
3.634, 5
V
VDD_HV_FLA
3.3 V flash supply voltage
—
–0.3
VSS_HV_FLA
Flash memory ground
—
–0.1
0.1
V
VDD_HV_OSC
3.3 V crystal oscillator amplifier supply voltage
—
–0.3
4.04, 5
V
VSS_HV_OSC
3.3 V crystal oscillator amplifier ground
—
–0.1
0.1
V
VDD_HV_ADRE06
3.3 V / 5.0 V ADC_0 high reference voltage
—
–0.3
6
V
VDD_HV_ADRE1
3.3 V / 5.0 V ADC_1 high reference voltage
VSS_HV_ADRE0
ADC_0 ground and low reference voltage
—
–0.1
0.1
V
VSS_HV_ADRE1
ADC_1 ground and low reference voltage
VDD_HV_ADV
3.3 V ADC supply voltage
—
–0.3
4.04, 5
V
VSS_HV_ADV
3.3 V ADC supply ground
—
–0.1
0.1
V
TVDD
Supply ramp rate
—
0.9 V/s
0.06 V/µs
VINA
Voltage on analog pin with respect to ground
(VSS_HV_IO)
—
–0.3
6
V
VIN
Voltage on any digital pin with respect to ground
(VSS_HV_IO)
Relative to
VDD_HV_IO
–0.3
VDD_HV_IO +
0.3, 7
V
IINJ
Maximum DC injection current per pin, 5 V ADC pads
Note 8
–5
5
mA
IINJPAD
Injected input current on any pin during overload
condition
—
–10
10
mA
IINJSUM
Absolute sum of all injected input currents during
overload condition
—
–50
50
mA
Storage temperature
—
–55
165
°C
TSTG
1. 1.45 V to 1.5 V allowed for 60 seconds cumulative time at maximum TJ=165°C; remaining time as defined in note -1 and
note -1.
2. 1.375 V to 1.45 V allowed for 10 hours cumulative time at maximum TJ=165°C; remaining time as defined in note -1.
3. 1.32 V to 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at
maximum TJ=165°C.
4. 5.3 V for 10 hours cumulative over lifetime of device; 3.3 V +10% for time remaining.
5. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
6. VDD_HV_ADRE0 and VDD_HV_ADRE1 cannot be operated at different voltages and must be supplied by the same voltage
source.
7. Only when VDD_HV_IO < 3.63 V.
8. The following conditions apply:
• Absolute maximum supply: VDD_HV_ADREx = 6.0 V (60 seconds lifetime, no restrictions—part can switch)
MPC5744P Data Sheet, Rev. 6.1, 11/2017
56
NXP Semiconductors
Electrical characteristics
•
•
•
•
Absolute maximum supply: VDD_HV_ADREx = 6.0 V (10 hours, device in reset—no switching)
Absolute maximum supply: VDD_HV_ADREx = 5.5 V (always)
Absolute maximum ADC input pin voltage = 7.0 V (60 seconds lifetime), when VDD_HV is connected to the 5 V
Absolute maximum ADC input pin voltage = 6.5 V (always while respecting 5 mA maximum injection), when VDD_HV
is connected to the 5 V
3.4 Recommended operating conditions
NOTE
Full functionality cannot be guaranteed when voltage drops
below 3.0 V. In particular, ADC electrical characteristics and
DC electrical specifications for I/Os might not be guaranteed.
Table 13. Recommended operating conditions (VDD_HV_xx = 3.3 V)
Symbol
Parameter
Conditions
Min
Max
Unit
3.3 V voltage regulator supply voltage
—
3.15
3.6
V
VDD_HV_IO
3.3 V input/output supply voltage
—
3.15
3.6
V
VSS_HV_IO
VDD_HV_PMU
1
2
Input/output ground voltage
—
0
0
V
VDD_HV_FLA3
3.3 V flash supply voltage
—
3.15
3.6
V
VSS_HV_FLA
Flash memory ground
—
0
0
V
VDD_HV_OSC
3.3 V crystal oscillator amplifier supply voltage
—
3.15
3.6
V
VSS_HV_OSC
3.3 V crystal oscillator amplifier ground
—
0
0
V
4
VDD_HV_ADRE0
3.3 V / 5.0 V ADC_0 high reference voltage
VDD_HV_ADRE1
3.3 V / 5.0 V ADC_1 high reference voltage
VDD_HV_ADRE05
3.3 V / 5.0 V ADC_0 high reference voltage
VDD_HV_ADRE1
3.3 V / 5.0 V ADC_1 high reference voltage
VSS_HV_ADRE05
ADC_0 ground and low reference voltage
VSS_HV_ADRE1
ADC_1 ground and low reference voltage
VDD_HV_ADV6
VSS_HV_ADV
TJ ≤ 150°C
3.15 to 5.5
V
150°C < TJ < 165°C
(only for
corresponding
marked parts)
3.15 to 5.25
V
—
0
0
V
3.3 V ADC supply voltage
—
3.15
3.6
V
3.3 V ADC supply ground
—
0
0
V
Core supply, 1.25 V +/-5%
—
1.19
1.32
V
VDD_LV_CORx
Internal supply voltage
—
—
—
V
VSS_LV_CORx
VDD_LV_COR
7
Internal reference voltage
—
0
0
V
VDD_LV_PLL
Internal PLL supply voltage
—
1.19
1.32
V
VSS_LV_PLL
Internal PLL reference voltage
—
0
0
V
VDD_LV_NEXUS
Aurora LVDS supply voltage
—
1.19
1.32
V
VSS_LV_NEXUS
Aurora LVDS supply ground
—
0
0
V
VDD_LV_LFAST
LFAST PLL supply voltage
—
1.19
1.32
V
VSS_LV_LFAST
LFAST PLL supply ground
—
0
0
V
Digital pins
–3.0
3.0
mA
Analog pins
–3.0
3.0
IIC
DC injection current per
pin8, 9, 10
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
57
Electrical characteristics
Table 13. Recommended operating conditions (VDD_HV_xx = 3.3 V) (continued)
Symbol
Parameter
Conditions
Min
Max
Shared analog pins
–3.6
3.6
Unit
TA
Ambient temperature under bias
fCPU≤ 200MHz
–40
13511
°C
TJ
Junction temperature under bias
—
–40
16512, 13
°C
1. The chip functions down to the point where LVD_PMC resets the chip. When the voltage drops below LVD_PMC, the chip
resets.
2. The chip functions down to the point where LVD_IO resets the chip. When the voltage drops below LVD_IO, the chip
resets.
3. The chip functions down to the point where LVD_FLASH resets the chip. When the voltage drops below LVD_FLASH, the
chip resets.
4. The chip functions down to the point where LVD_OSC resets the chip. When the voltage drops below LVD_OSC, the chip
resets.
5. VDD_HV_ADRE0 and VDD_HV_ADRE1 cannot be operated at different voltages and need to be supplied by the same voltage
source.
6. The chip functions down to the point where LVD_ADC resets the chip. When the voltage drops below LVD_ADC, the chip
resets.
7. The chip functions down to the point where LVD_CORE or up to the point where HVD_CORE resets the chip by default.
8. I/O and analog input specifications are valid only if the injection current on adjacent pins is within these limits. See the
absolute maximum ratings table for maximum input current for reliability requirements.
9. Full device lifetime without performance degradation.
10. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is
above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network
calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
11. For a maximum TJ of 150°C, the corresponding maximum TA is 125°C.
12. Some orderable parts have a maximum TJ value of 150°C. See the device marking for the applicable temperature range.
13. For devices supporting the 165°C junction temperature option: Operation at 150°C < TJ < 165°C is allowed for a maximum
cumulative time of 200 hours over the device lifetime.
3.5 Thermal characteristics
Table 14. Thermal characteristics for 144LQFP and 257MAPBGA packages
Symbol
RθJA
RθJMA
Parameter
Thermal resistance, junction-to-ambient
natural convection2
Thermal resistance, junction-to-ambient
forced convection at 200 ft/min1
Conditions
144LQFP
257MAPBGA
Unit
Single layer board - 1s
39
45
°C/W
Four layer board - 2s2p
31
25
1s3
31
36
2s2p4
25
21
Single layer board Four layer board -
°C/W
Thermal resistance
junction-to-board5
—
18
13
°C/W
RθJC
Thermal resistance
junction-to-case6
—
8
8
°C/W
ΨJT
Junction-to-package-top natural
convection7
—
2
2
°C/W
RθJB
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
4. Per JEDEC JESD51-6 with the board horizontal.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
58
NXP Semiconductors
Electrical characteristics
5. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package. Board temperature is measured on the top surface of the board near the package.
6. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
7. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
3.5.1 General notes for specifications at maximum junction
temperature
An estimation of the chip junction temperature, TJ, can be obtained from this equation:
TJ = TA + (RθJA × PD)
where:
• TA = ambient temperature for the package (°C)
• RθJA = junction to ambient thermal resistance (°C/W)
• PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which value is closer to the application depends on the power dissipated
by other components on the board. The value obtained on a single layer board is
appropriate for the tightly packed printed circuit board. The value obtained on the board
with the internal planes is usually appropriate if the board has low power dissipation and
the components are well separated.
When a heat sink is used, the thermal resistance is expressed in the following equation as
the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
• RθJA = junction to ambient thermal resistance (°C/W)
• RθJC = junction to case thermal resistance (°C/W)
• RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RθCA. For instance, the
user can change the size of the heat sink, the air flow around the device, the interface
material, the mounting arrangement on printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
59
Electrical characteristics
To determine the junction temperature of the device in the application when heat sinks
are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using this equation:
TJ = TT + (ΨJT × PD)
where:
• TT = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a
40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
3.5.1.1
References
Semiconductor Equipment and Materials International; 3081 Zanker Road; San Jose, CA
95134 USA; (408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global
Engineering Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the Web at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA
Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San
Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for AirCooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board
Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of
SemiTherm, San Diego, 1999, pp. 212–220.
3.6 Electromagnetic compatibility (EMC)
Tests were carried out in accordance with the International Electrotechnical Commission
specifications:
MPC5744P Data Sheet, Rev. 6.1, 11/2017
60
NXP Semiconductors
Electrical characteristics
• IEC 61967: Integrated Circuits, Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz
• IEC 61967-2: Measurement of radiated emissions – TEM-cell and wideband TEMcell method
Parameter
Test #
Comm.
modules3
GPIO
Classification
level2
Unit
1
On
Off, input pull-up
L
dBμV
2
On
Off, input pull-up
L
dBμV
3
On
Off, input pull-up
L
dBμV
4
On
Off, input pull-up
—4
dBμV
5
On
Off, input pull-up
L
dBμV
6
PG15
input, pull-up
L
dBμV
Off
PG15
output high, half drive
L
dBμV
Off
PG15
output high, full drive
L
dBμV
Off
PG15
output low, half drive
L
dBμV
10
Off
PG15
output low, full drive
L
dBμV
11
Off
All I/O tri-stated
I
dBμV
12
Off
PG26 toggle @ 5 kHz, half drive, SR off
L
dBμV
13
Off
PG26 toggle @ 5 kHz, half drive, SR on
L
dBμV
Off
PG26
toggle @ 5 kHz, full drive, SR off
L
dBμV
Off
PG26
toggle @ 5 kHz, full drive, SR on
I
dBμV
7
VEME
Conditions1
8
9
14
15
On
1. All tests ran with core and bus frequency at 200 MHz. Test #2 had "weak" FM modulation and Test #3 had "strong" FM
modulation.
2. I = Class 1 (36 dBµV), L = Class 2 (24 dBµV), N = Class 3 (12 dBµV)
3. LINFlex0/1 running at 19.2 kbd, SPI0 running at 2.5 MHz, SPI1 running at 7.5 MHz, SPI2 running at 4.5 MHz, CAN0/1
running at 500 kbd
4. Test #4 values were slightly above class I level.
5. PG1 = port group 1: pins F[3:15]
6. PG2 = port group 2: pins A[2:4], C[11:14], D14, F12, G6, J8
Each of the tests ran once across each of the following frequency bands.
Frequency band
RBW (kHz)
VBW (kHz)
150 kHz to 30 MHz
9
30
30 MHz to 1000 MHz
120
300
Sweep time
(ms/MHz)
Pre-amplifier
Detector
5
ON (–20 dB)
Peak-Average
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61
Electrical characteristics
3.7 Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
NOTE
A device will be defined as a failure if after exposure to ESD
pulses the device no longer meets the device specification
requirements.
Table 15. ESD ratings
No.
Symbol
1
VESD(HBM)
2
VESD(CDM)
Parameter
Conditions1
Electrostatic discharge
TA = 25 °C
(Human Body Model)
conforming to AEC-Q100-002
Electrostatic discharge
TA = 25 °C
(Charged Device Model)
conforming to AEC-Q100-011
Class
Max value
Unit
H1C
2000
V
C3A
500
V
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
3.8 Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
• High power regulator (external NPN to support core current)
• Low voltage detector (LVD_IO) for 3.3 V supply to IO (VDD_HV_IO)
• Low voltage detector (LVD_PMC) for 3.3 V supply (VDD_HV_PMU)
• Low voltage detector (LVD_FLASH) for 3.3 V flash memory supply (VDD_HV_FLA)
• Low voltage detector (LVD_ADC) for 3.3 V ADC supply (VDD_HV_ADV)
• Low voltage detector (LVD_OSC) for 3.3 V OSC supply (VDD_HV_OSC)
• Low voltage detector (LVD_CORE) for 1.25 V digital core supply (VDD_LV)
• Low voltage detector (LVD_CORE_BK) for the self-test of LVD_CORE
• High voltage detector (HVD_CORE) for 1.25 V digital core supply (VDD_LV)
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NXP Semiconductors
Electrical characteristics
• High voltage detector (HVD_CORE_BK) for the self-test of HVD_CORE
• Power on Reset (POR)
NOTE
When the external regulator mode is used either the
EXT_POR_B signal needs to be driven by external circuitry
until all power supplies are in recommended ranges or the
internal LVDs keep the device in POR until all power supply
are in recommended range. There needs to be used the external
over voltage detectors for all power supplies in both regulator
modes for safety operation.
The following bipolar transistor is supported:
• ON Semiconductor™ NJD2873 (requires a heat sink to operate up to 165 °C): See
Table 16.
Table 16. Recommended operating characteristics: NJD2873
Symbol
Parameter
Value
Unit
60-550
—
hFE
DC current gain (Beta)
PD
Absolute minimum power dissipation
1.60
W
ICMaxDC
Minimum peak collector current
2.0
A
VCESAT
Collector to emitter saturation voltage
300
mV
Base to emitter voltage
0.95
V
Minimum voltage at transistor collector
2.5
V
VBE
Vc
Table 17. Voltage regulator electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4
—
18.8
µF
0.03
—
0.15
Ω
Cld
External decoupling / stability capacitor
Min value granted with
respect to tolerance, voltage,
temperature, and aging
variations. 4 capacitors are
recommended – one for each
side of the chip.
—
Combined ESR of external capacitor
—
tSU
Start-up time after main supply
stabilization
Cld = 4 µF
—
—
2.5
ms
Lbw
Bonding inductance
—
—
—
13
nH
Rbw
Bonding wire and pad resistance
—
—
—
0.5
Ω
Rsd
Series resistance of on-chip power grid
—
—
—
0.1
Ω
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NXP Semiconductors
63
Electrical characteristics
Table 17. Voltage regulator electrical specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Cpd
Parallel decoupling capacitor
Per pin; must use at least 6
capacitors, but total of all
capacitors must be no more
than 300 nF
47
—
300
nF
—
Power supply rejection
@DC no load
—
—
–23
dB
(Cld = 4 µF)
@200 kHz no load
–23
@DC 400 mA
–23
@200 kHz 400 mA
–23
—
Load current transient time
Iload from 20% to 80%
1.0
—
—
µs
—
0.01
V/ms
—
0.125
V/µs
—
0.9 V/s
—
0.06 V/
μs
0.98
1.02
1.08
V
Cld = 4 µF
—
Supply ramp rate
VDD_LV_COR
—
Supply ramp rate
VDD_HV_PMU
—
POR_COR
—
—
POR_PMU
—
2.4
2.59
2.76
V
—
LVD_CORE, LVD_CORE_BK
calibrated (trimmed)
1.12
1.15
1.18
V
—
HVD_CORE, HVD_CORE_BK
calibrated (trimmed)
1.32
1.36
1.40
V
—
LVD_PMC
calibrated (trimmed)
2.93
3.02
3.13
V
—
LVD_IO
calibrated (trimmed)
2.93
3.02
3.13
V
—
LVD_FLASH
calibrated (trimmed)
2.93
3.02
3.13
V
—
LVD_ADC
calibrated (trimmed)
2.93
3.02
3.13
V
—
LVD_OSC
calibrated (trimmed)
2.93
3.02
3.13
V
—
Hysteresis LVD_CORE
—
—
10
—
mV
—
Hysteresis HVD_CORE
—
—
—
—
mV
—
Hysteresis LVD_PMC, LVD_IO,
LVD_FLASH, LVD_ADC, LVD_OSC
—
—
20
—
mV
—
LVD/HVD trimming
16 steps
—
5
—
mV
TJ
Junction Temperature
—
–40
—
165
°C
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Electrical characteristics
VDD_HV_PMU
BCTRL
Cld 4μ
Cpd
47n
Lbw
Package
Rbw
Cpd
47n
Rbw
Cpd
47n
Lbw
Rbw
Rsd
Lbw
Die
Rbw
Lbw
Cpd
47n
Figure 4. Core supply decoupling and parasitics
3.9 DC electrical characteristics
The following tables provide DC characteristics for bidirectional pads:
• Table 18 provides output driver characteristics FlexRay I/Os (SYM).
• Table 19 provides output driver characteristics for LFAST I/Os.
NOTE
See the FlexRay section for parameters dedicated to this
interface.
Table 18. FlexRay (SYM) configuration output buffer electrical characteristics
Symbol
ROH_Y
ROL_Y
Parameter
Conditions1
PMOS output impedance
Push Pull, IOH = 2 mA,
SYM configuration
VOH = VDD_HV_IO–(0.28...0.52V)
PMOS output impedance
Push Pull, IOL = 2 mA,
SYM configuration
VOL = 0.28...0.52 V
Value
Unit
Min
Typ
Max
35
50
65
Ω
35
50
65
Ω
Table continues on the next page...
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65
Electrical characteristics
Table 18. FlexRay (SYM) configuration output buffer electrical characteristics
(continued)
Symbol
Fmax_Y
Ttr_Y
|Tskew_Y|
Conditions1
Parameter
Output frequency
CL = 20 pF, VDD_HV_IO=3.3 V
SYM configuration
–5%, +10%
Transition time output pin
CL = 20 pF, VDD_HV_IO=3.3 V
SYM configuration
–5%, +10%
Difference between rise
and fall time
—
Value
Unit
Min
Typ
Max
—
—
50
MHz
1
—
6
ns
0
—
1
ns
1. VDD_HV_IO = 3.3 V (–5%, +10%), TJ = –40 to 165 °C, unless otherwise specified.
NOTE
See the LFAST section for parameters dedicated to this
interface.
Table 19. LFAST output buffer electrical characteristics
Symbol
Conditions1
Parameter
Value
Unit
Min
Typ
Max
|ΔVO_L|
Absolute value for differential output voltage
swing (terminated)
—
100
200
285
mV
VICOM_L
Common mode voltage
—
1.08
1.2
1.32
V
Transition time output pin LVDS configuration
—
0.2
—
1.5
ns
Ttr_L
1. VDD_HV_IO = 3.3 V (–5%, +10%), TJ = –40 to 165 °C, unless otherwise specified.
NOTE
Fast IOs must be specified only as fast (and not as high
current). See Table 20.
Table 20. DC electrical specifications
Symbol
VDD_LV
Parameter
Conditions
Value
Unit
Min
Typ
Max
LV (core) Supply Voltage
—
1.19
—
1.32
V
I/O Supply Voltage
—
3.15
—
3.6
V
VIH
CMOS Input Buffer High Voltage (with hysteresis
disabled)
—
0.55 *
VDD_HV_IO
—
VDD_HV_IO
+ 0.3
V
VIL
CMOS Input Buffer Low Voltage (with hysteresis
disabled)
—
Vss - 0.3
—
0.40 *
VDD_HV_IO
V
CMOS Input Buffer Hysteresis
—
0.1 *
VDD_HV_IO
—
—
V
Weak Pullup Current2
—
10
—
80
µA
—
10
—
80
µA
VDD_HV_IO1
VHYS
Pull_IOH
Pull_IOL
Weak Pulldown
Current3
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Electrical characteristics
Table 20. DC electrical specifications (continued)
Symbol
Parameter
Conditions
Value
Unit
Min
Typ
Max
Digital Pad Input Leakage Current (weak pull inactive)4
—
-2.5
—
2.5
µA
VOH
Output High Voltage5
—
0.8 *
VDD_HV_IO
—
—
V
VOL
Output Low Voltage6
—
—
—
0.2 *
VDD_HV_IO
V
IOH_F
Full drive IOH (SIUL2_MSCRn's SRC[1:0] field is 11b)
—
10
—
180
mA
IINACT_D
IOL_F
Full drive IOL (SIUL2_MSCRn's SRC[1:0] field is 11b)
—
21
—
230
mA
IOH_H
Half drive IOH (SIUL2_MSCRn's SRC[1:0] field is 10b)
—
9
—
90
mA
IOL_H
Half drive IOL (SIUL2_MSCRn's SRC[1:0] field is 10b)
—
10.5
—
115
mA
1.
2.
3.
4.
Max power supply ramp rate is 100 V / ms
Measured when pad = 0 V
Measured when pad = VDD_HV_IO
The specified values apply to all pads except D[7] (SGEN output pad). For D[7], leakage current specifications are -15μA
Min and 15μA Max.
5. Measured when pad is sourcing 2 mA
6. Measured when pad is sinking 2 mA
3.10 Supply current characteristics
Current consumption data is given in the following table.
Table 21. Current consumption characteristics
Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
IDD_LV
Operating current
TA = 25 °C
—
350
400
mA
—
440
570
—
470
610
—
340
—
—
410
—
—
430
—
—
25
35
+ IDD_LV_PLL2
VDD_LV_COR = 1.32 V
TJ = 150 °C
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
IDD_LV_BIST
Operating current
+ IDD_LV_PLL
Normal startup self-test
mA
TA = 25 °C
VDD_LV_COR = 1.32 V
TJ = 150 °C
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
IDD_LV_STOP
Operating current in
VDD STOP mode
TA = 25 °C
mA
VDD_LV_COR = 1.32 V
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
67
Electrical characteristics
Table 21. Current consumption characteristics (continued)
Symbol
Parameter
Conditions1
Min
Typ
Max
TJ = 150 °C
—
90
230
—
120
310
—
25
40
—
110
300
—
140
400
—
—
6.6
—
—
6.8
—
—
12.1
—
—
12.5
—
3.4
4.2
—
3.5
4.5
—
0.20
0.28
—
0.32
0.50
—
0.24
0.40
—
0.40
0.70
—
—
1.6
Unit
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
IDD_LV_HALT
Operating current in
VDD HALT mode
TA = 25 °C
mA
VDD_LV_COR = 1.32 V
TJ = 150 °C
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
IDD_LV_LFAST
Operating current
TJ = 150 °C
mA
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
IDD_LV_NEXUS
Operating current
TJ = 150 °C
mA
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
3
IDD_HV_ADV
Operating current
TJ = 150 °C
mA
4 ADCs operating at 80 MHz
VDD_HV_ADV = 3.6 V
TJ = 165 °C
4 ADCs operating at 80 MHz
VDD_HV_ADV = 3.6 V
IDD_HV_ADRE, 4
Operating current
TJ = 150 °C
mA
ADC operating at 80 MHz
VDD_HV_ADRE = 3.6 V
TJ = 150 °C
ADC operating at 80 MHz
VDD_HV_ADRE = 5.5 V
TJ = 165 °C
ADC operating at 80 MHz
VDD_HV_ADRE = 3.6 V
TJ = 165 °C
ADC operating at 80 MHz
VDD_HV_ADRE = 5.5 V
IDD_HV_OSC
Operating current
TJ = 150 °C
mA
3.3 V supplies
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Electrical characteristics
Table 21. Current consumption characteristics (continued)
Symbol
Conditions1
Parameter
Min
Typ
Max
—
—
1.8
—
—
5.5
—
—
7.0
Unit
Frequency: 200MHz
TJ = 165 °C
3.3 V supplies
Frequency: 200MHz
IDD_HV_FLA
Operating current
TJ = 150 °C
mA
3.3 V supplies
Frequency: 200MHz
TJ = 165 °C
3.3 V supplies
Frequency: 200MHz
1. The content of the Conditions column identifies the components that draw the specific current.
2. Enabled modules: ADC0/1, FlexPWM0, eTimer0, two SPIs, two FlexCANs, FlexRay, one LINFlexD, DMA. At maximum
frequency. I/O supply current excluded.
3. Internal structures hold the input voltage less than VDD_HV_ADV + 1.0 V on all pads powered by VDDA supplies, if the
maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.
4. This value is the total current for two ADCs.
3.11 Temperature sensor
The following table describes the temperature sensor electrical characteristics.
Table 22. Temperature sensor electrical characteristics
Symbol
—
Parameter
Conditions
Min
Typ
Max
Unit
Temperature monitoring range
—
–40
—
165
°C
TSENS
Sensitivity
—
—
5.18
—
mV/°C
TACC
Accuracy for linear temperature sensor
TJ = –40 to 150 °C
–3
—
+3
°C
TJ = 150 to 165 °C
–5
—
+5
—
Accuracy for temperature-threshold digital flags
TJ = –40 to 150 °C
–5
—
+5
°C
—
Temperature variation for each customer-adjustable
trim step
TJ = –40 to 150 °C
0.4
0.7
1.0
°C
—
Operating current
TJ = –40 to 165 °C
—
—
675
µA
3.12 Main oscillator electrical characteristics
This device provides a driver for the oscillator in pierce configuration with amplitude
control. Controlling the amplitude allows a more sinusoidal oscillation, reducing EMI
and power consumption. This Loop Controlled Pierce (LCP mode) requires good
practices to reduce the stray capacitance of traces between the crystal and the MCU.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
69
Electrical characteristics
An operation in Full Swing Pierce (FSP mode), implemented by an inverter, is also
available in cases of parasitic capacitances that cannot be reduced or of using a crystal
with high equivalent series resistance. This mode requires special care regarding the
serial resistance used to avoid the crystal overdrive.
Two other provided modes are External (EXT Wave) and disable (OFF mode). For EXT
Wave, the drive is disabled and an external clock source within the CMOS level based in
the analog oscillator supply can be used. When OFF, the EXTAL is pulled down by a
240-kohm resistor and the feedback resistor remains active, connecting XTAL through
EXTAL by a 1M resistor.
The following figure describes a simple model of the internal oscillator driver and
provides an example of connections for an oscillator.
NOTE
When selecting C1 and C2 in your oscillator circuit, contact the
crystal manufacturer for their recommended values. Capacitor
loading of the oscillator must be fully characterized at the
system level to ensure proper operation.
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Electrical characteristics
Figure 5. Oscillator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external
circuits.
Table 23. Main oscillator electrical characteristics
Symbol
Parameter
Mode
Conditions1
Min
Typ
Max
—
42
Unit
fXOSCHS
Oscillator frequency
FSP/LCP
—
40
MHz
gmXOSCHS
Driver transconductance
LCP
VDD_HV_OSC = 3.3V
—
20
—
mA/V
FSP
–5%, +10%
—
30
—
Oscillation amplitude
LCP
fOSC = 4, 8, 16 MHz
1.1
1.3
2.6
V
fOSC = 40 MHz
1.2
1.5
1.7
V
Oscillator startup time
FSP/LCP3
fOSC = 4 MHz
1.75
2.5
2.9
ms
fOSC = 8, 16, 40 MHz
0.25
0.5
1.1
ms
VXOSCHS
TXOSCHSSU
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71
Electrical characteristics
Table 23. Main oscillator electrical characteristics (continued)
Symbol
Parameter
VIH
Input high level CMOS Schmitt
Trigger
VIL
VHYS
Conditions1
Mode
Min
Typ
Max
Unit
EXT Wave Oscillator bypass mode
—
1.48
—
V
Input low level CMOS Schmitt
Trigger
EXT Wave Oscillator bypass mode
—
1.85
—
V
Input low level CMOS Schmitt
hysteresis
EXT Wave Oscillator bypass mode
—
0.37
—
V
1. VDD_HV_OSC = 3.3 V –5%, +10%, TJ = 27 °C, unless otherwise specified
2. When using XOSC as the source for PLL0IN, the minimum frequency requirement of the PLL must be fulfilled as stated in
the PLL0 electrical characteristics.
3. Values are very dependent on crystal or resonator used and parasitic capacitance observed in the board.
3.13 PLLDIG electrical characteristics
PLL0_PHI0
IRCOSC
PLL0
PLL0_PHI1
XOSC
PLL1
PLL1_PHI0
Figure 6. PLL integration
Table 24. PLL0 electrical characteristics
Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
fPLL0IN
PLL0 input clock
—
8
—
40
MHz
PLL0IN
PLL0 input clock duty cycle2
—
40
—
60
%
fPLL0VCO
PLL0 VCO frequency
—
600
—
1250
MHz
fPLL0PHI0
PLL0 output clock PHI0
—
4.76
—
200
MHz
fPLL0PHI1
PLL0 output clock PHI1
—
20
—
156
MHz
tPLL0LOCK
PLL0 lock time
—
—
—
100
µs
|PLL0PHISPJ|
PLL0_PHI single period jitter
fPLL0PHI = 400 MHz, 6-sigma
—
—
200
ps
fPLL0PHI1 = 40 MHz, 6-sigma
—
—
300
ps
10 periods accumulated jitter (80 MHz
equivalent frequency), 6-sigma pk-pk
—
—
±250
ps
fPLL0IN = 20 MHz (resonator)
|PLL0PHI1SPJ|
PLL0_PHI1 single period jitter
fPLL0IN = 20 MHz (resonator)
PLL0LTJ
PLL0 output long term jitter3
fPLL0IN = 20 MHz (resonator),
VCO frequency = 800 MHz
72
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
Electrical characteristics
Table 24. PLL0 electrical characteristics (continued)
Symbol
Conditions1
Min
Typ
Max
Unit
16 periods accumulated jitter (50 MHz
equivalent frequency), 6-sigma pk-pk
—
—
±300
ps
long term jitter (< 1 MHz equivalent
frequency), 6-sigma pk-pk)
—
—
±500
ps
FINE LOCK state
—
—
5
mA
Parameter
IPLL0
PLL0 consumption
1. VDD_LV =1.25 V ± 5%, TJ = -40 to 165 °C unless otherwise specified.
2. PLL0IN clock retrieved directly from either IRCOSC or external XOSC clock. Input characteristics are granted when using
IRCOSC or when external oscillator is used in functional mode.
3. VDD_LV noise due to application in the range VDD_LV = 1.25 V±5%, with frequency below PLL bandwidth (40 kHz) will be
filtered.
Table 25. FMPLL1 electrical characteristics
Symbol
Parameter
fPLL1IN
PLL1 input clock
PLL0 input clock duty
PLL1IN
Conditions1
Min
Typ
Max
Unit
—
38
—
78
MHz
—
35
—
65
%
cycle2
fPLL1VCO
PLL1 VCO frequency
—
600
—
1250
MHz
fPLL1PHI0
PLL1 output clock PHI0
—
4.76
—
200
MHz
tPLL1LOCK
PLL1 lock time
—
—
—
100
µs
fPLL1MOD
PLL1 modulation frequency
—
—
—
250
kHz
|δPLL1MOD|
PLL1 modulation depth (when enabled)
Center spread
0.25
—
2
%
Down spread
0.5
—
4
%
FINE LOCK state
—
—
6
mA
IPLL1
PLL1 consumption
1. VDD_LV = 1.25 V ± 5%, TJ = -40 to 165 °C unless otherwise specified.
2. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when
using internal PLL0 or when external oscillator is used in functional mode.
3.14 16 MHz Internal RC Oscillator (IRCOSC) electrical
specifications
NOTE
Unless stated otherwise, specifications in Table 26 assume the
following: VDD_HV_PMU=3.15V to 3.6V, VSS=0V,
VDD_LV=1.18V to 1.32V, VSS=0V, TJ=–40 to 165°C.
Table 26. Internal RC Oscillator electrical specifications
Symbol
fTarget
fUntrimmed
Parameter
Conditions
Min
Typ
Max
Unit
IRCOSC target frequency
—
—
16
—
MHz
IRCOSC frequency (untrimmed)
—
11
—
17
MHz
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
73
Electrical characteristics
Table 26. Internal RC Oscillator electrical specifications (continued)
Symbol
δfvar
δfvar_noT1
Tstartup
Parameter
Conditions
Min
Typ
Max
Unit
IRC frequency variation with temperature and
voltage compensation
TJ < 150 °C
-3
—
3
%
—
4
IRC frequency variation without temperature
compensation (only voltage compensation)
TJ < 150 °C
–8
—
8
TJ < 165 °C
–10
—
10
—
—
—
5
µs
TJ < 165 °C
Startup time without temperature compensation
-4
%
IVDD3
Current consumption on 3.3 V power supply
After Tstartup
—
—
55
µA
IVDD12
Current consumption on 1.2 V power supply
After Tstartup
—
—
270
µA
1. The typical user trim step size (dfTRIM) is +48kHz for frequencies trimmed above nominal and -40kHz for frequencies
trimmed below nominal based on characterization results.
3.15 ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter.
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
( 2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out
7
( 1)
6
5
(5)
4
(4)
3
(3)
2
1
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
1 LSB (ideal)
0
1
2
3
Offset Error OSE
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Figure 7. ADC characteristics and error definitions
MPC5744P Data Sheet, Rev. 6.1, 11/2017
74
NXP Semiconductors
Electrical characteristics
3.15.1 Input equivalent circuit and ADC conversion characteristics
EXTERNAL CIRCUIT
Source
Filter
RS
RF
INTERNAL CIRCUIT SCHEME
Current Limiter
RL
Sampling
RSW1
CF
VA
VDD_HV_ADREn
Channel
Selection
CP1
RAD
CS
CP2
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL
Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 8. Input equivalent circuit
NOTE
Unless noted otherwise, the specifications in Table 27 assume
the use of 12-bit resolution (high accuracy, recommended): In
ADC_CALBISTREG, set OPMODE to 110b.
Table 27. ADC conversion characteristics
Symbol
fCK
fs
tsample
tconv
CS
CP15
Conditions1
Parameter
Min
Typ
Max
Unit
ADC Clock frequency (depends on ADC —
configuration) (The duty cycle depends
on AD_CK2 frequency.)
20
—
80
MHz
Sampling frequency
—
—
1.00
MHz
80 MHz, 12-bit resolution
250
—
—
ns
80 MHz, 12-bit resolution
(high accuracy,
recommended)
250
—
—
80 MHz, 12-bit resolution
650
—
—
80 MHz, 12-bit resolution
(high accuracy,
recommended)
700
—
—
Sample
—
time3
Conversion time4
ns
ADC input sampling capacitance
—
—
3
5
pF
ADC input pin capacitance 1
—
—
—
56
pF
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
75
Electrical characteristics
Table 27. ADC conversion characteristics (continued)
Symbol
CP25
Conditions1
Parameter
Min
Typ
Max
Unit
ADC input pin capacitance 2
—
—
—
0.8
pF
Internal resistance of analog source
VREF range = 4.5 to 5.5 V
—
—
0.3
kΩ
VREF range = 3.15 to 3.6 V
—
—
875
Ω
Internal resistance of analog source
—
—
—
825
Ω
INL
Integral non-linearity
—
–2
—
2
LSB
DNL
Differential non-linearity
—
–1
—
1
LSB
OFS
Offset error
—
–4
—
4
LSB
GNE
Gain error
—
–4
—
4
LSB
150 °C
—
—
250
nA
—
–3
—
3
mA
Max leakage
150 °C
—
—
300
nA
Max positive/negative injection
|VREF_AD0 - VREF_AD1| <
150mV
–3.6
—
3.6
mA
SNR
Signal-to-noise ratio
VREF = 3.3 V, Fin < 125kHz
67
—
—
dB
SNR7
Signal-to-noise ratio
VREF = 5.0 V, Fin < 125kHz
69
—
—
dB
RSW15
5
RAD
Input (single ADC Max leakage
channel)
Max positive/negative injection
Input (double
ADC channel)
THD
Total harmonic distortion
Fin ≤ 125 kHz
65
70
—
dB
ENOB
Effective number of bits
Fin < 125 kHz
10.5
—
—
bits
SINAD
Signal-to-noise and distortion
See ENOB
(6.02 * ENOB) + 1.76
dB
TUEIS1WINJ
Total unadjusted error for IS1WINJ
(single ADC channels)
Without current injection
–6
—
6
LSB
TUEIS1WINJ
Total unadjusted error for IS1WINJ
(single ADC channels)
Current injection: ±3 mA for
each channel, max 3
channels
–8
—
8
LSB
1. VDD_HV_IO = 3.3 V -5%,+10%, TJ = –40 to +165 °C, unless otherwise specified, and analog input voltage from VAGND to
VAREF
2. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the
sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tsample depend on programming.
4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
5. See Figure 2.
6. For the 144-pin package.
7. Test conditions have an influence on the achieved performance. Please contact FSL personnel to share the conditions for
these results.
NOTE
The ADC performance specifications are not guaranteed if two
ADCs simultaneously sample the same shared channel.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
76
NXP Semiconductors
Flash memory specifications
3.16 Flash memory specifications
3.16.1 Maximum junction temperature 150°C
3.16.1.1
Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this
section are defined for a single embedded flash memory within
an SoC, and represent average currents for given supplies and
operations.
Table 28 shows the estimated Program/Erase times.
Table 28. Flash memory program and erase specifications
Characteristic1
Symbol
Typ2
Factory
Programming3, 4
Field Update
Initial
Max
Initial
Max, Full
Temp
Typical
End of
Life5
20°C ≤TA
≤30°C
-40°C ≤TJ
≤150°C
-40°C ≤TJ
≤150°C
Unit
Lifetime Max6
≤ 1,000
cycles
≤ 250,000
cycles
tdwpgm
Doubleword (64 bits) program time 43
100
150
55
500
μs
tppgm
Page (256 bits) program time
73
200
300
108
500
μs
tqppgm
Quad-page (1024 bits) program
time
268
800
1,200
396
2,000
μs
t16kers
16 KB Block erase time
168
290
320
250
1,000
ms
t16kpgm
16 KB Block program time
34
45
50
40
1,000
ms
t32kers
32 KB Block erase time
217
360
390
310
1,200
ms
t32kpgm
32 KB Block program time
69
100
110
90
1,200
ms
t64kers
64 KB Block erase time
315
490
590
420
1,600
ms
t64kpgm
64 KB Block program time
138
180
210
170
1,600
ms
t256kers
256 KB Block erase time
884
1,520
2,030
1,080
4,000
—
ms
t256kpgm
256 KB Block program time
552
720
880
650
4,000
—
ms
1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: -40°C ≤ TJ ≤ 150°C, full spec voltage.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
77
Maximum junction temperature 150°C
3.16.1.2
Flash memory Array Integrity and Margin Read specifications
Table 29. Flash memory Array Integrity and Margin Read specifications
Symbol
Characteristic
Min
Typical
Max1
Units
tai16kseq
Array Integrity time for sequential sequence on 16 KB block.
—
—
512 x
Tperiod x
Nread
—
tai32kseq
Array Integrity time for sequential sequence on 32 KB block.
—
—
1024 x
Tperiod x
Nread
—
tai64kseq
Array Integrity time for sequential sequence on 64 KB block.
—
—
2048 x
Tperiod x
Nread
—
tai256kseq
Array Integrity time for sequential sequence on 256 KB block.
—
—
8192 x
Tperiod x
Nread
—
tmr16kseq
Margin Read time for sequential sequence on 16 KB block.
73.81
—
110.7
μs
tmr32kseq
Margin Read time for sequential sequence on 32 KB block.
128.43
—
192.6
μs
tmr64kseq
Margin Read time for sequential sequence on 64 KB block.
237.65
—
356.5
μs
tmr256kseq
Margin Read time for sequential sequence on 256 KB block.
893.01
—
1,339.5
μs
2
1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
3.16.1.3
Symbol
Array P/E
cycles
Data
retention
Flash memory module life specifications
Table 30. Flash memory module life specifications
Characteristic
Conditions
Min
Typical
Units
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.1
—
250,000
—
P/E
cycles
Number of program/erase cycles per block
for 256 KB blocks.2
—
1,000
250,000
P/E
cycles
Minimum data retention.
Blocks with 0 - 1,000 P/E
cycles.
50
—
Years
Blocks with 100,000 P/E
cycles.
20
—
Years
Blocks with 250,000 P/E
cycles.
10
—
Years
1. Program and erase supported across standard temperature specs.
2. Program and erase supported across standard temperature specs.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
78
NXP Semiconductors
Maximum junction temperature 150°C
3.16.1.4
Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the
following figure. The spec window represents qualified limits. The extrapolated dotted
line demonstrates technology capability, however is beyond the qualification limits.
3.16.1.5
Symbol
tpsus
tesus
tres
tdone
Flash memory AC timing specifications
Table 31. Flash memory AC timing specifications
Characteristic
Min
Typical
Max
Units
Time from setting the MCR-PSUS bit until MCR-DONE bit is set
to a 1.
—
9.4
11.5
μs
plus four
system
clock
periods
plus four
system
clock
periods
Time from setting the MCR-ESUS bit until MCR-DONE bit is set
to a 1.
—
16
20.8
plus four
system
clock
periods
plus four
system
clock
periods
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low.
—
—
100
ns
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—
—
5
ns
μs
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
79
Maximum junction temperature 165°C
Table 31. Flash memory AC timing specifications (continued)
Symbol
tdones
tdrcv
Characteristic
Min
Typical
Max
Units
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
—
16
20.8
μs
plus four
system
clock
periods
plus four
system
clock
periods
Time to recover once exiting low power mode.
16
—
45
plus seven
system
clock
periods.
μs
plus seven
system
clock
periods
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin Read
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP
—
—
5
ns
taistop
Time from 1 to 0 transition of UT0-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request.
—
—
80
ns
Time from 1 to 0 transition of UT0-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request.
10.36
tmrstop
plus fifteen
system
clock
periods
—
20.42
plus four
system
clock
periods
μs
plus four
system
clock
periods
3.16.2 Maximum junction temperature 165°C
3.16.2.1
Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this
section are defined for a single embedded flash memory within
an SoC, and represent average currents for given supplies and
operations.
Table 32 shows the estimated Program/Erase times.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
80
NXP Semiconductors
Maximum junction temperature 165°C
Table 32. Flash memory program and erase specifications
Characteristic1
Symbol
Typ2
Factory Programming3, 4
Initial Max
Initial Max
Full Temp
20°C≤ TA ≤
30°C4
–40°C≤ TJ ≤
150°C4
Field Update
Units
Typical End of
Life5
Lifetime Max6
–40°C≤ TJ ≤
165 °C
≤
≤
1,000 250,000
cycles cycles
tdwpgm
Doubleword (64 bits)
program time
43
100
150
65
650
μs
tppgm
Page (256 bits)
program time
73
200
300
145
650
μs
tqppgm
Quad-page (1024 bits)
program time
268
800
1,200
540
2,700
μs
t16kers
16 KB Block erase time 168
290
320
500
9,000
ms
t16kpgm
16 KB Block program
time
45
50
70
1,400
ms
t32kers
32 KB Block erase time 217
360
390
610
9,000
ms
t32kpgm
32 KB Block program
time
100
110
140
2,800
ms
t64kers
64 KB Block erase time 315
490
590
820
9,000
ms
t64kpgm
64 KB Block program
time
138
180
210
280
5,500
ms
t256kers
256 KB Code erase
time7
884
1,520
2,030
1,080
4,000
—
ms
t256kpgm
256 KB Code program
time7
552
720
880
650
4,000
—
ms
34
69
1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: –40°C ≤ TJ ≤ 165°C; full spec voltage. 16 KB, 32 KB and 64 KB blocks are allowed to be programmed or
erased up to TJ = 165°C with restrictions.
7. 256 KB blocks may be programmed or erased at TJ = 150°C maximum. Times listed on this row are TJ = 150°C times.
3.16.2.2
Flash memory Array Integrity and Margin Read specifications
Table 33. Flash memory Array Integrity and Margin Read specifications
Symbol
Characteristic
Min
Typical
Max1
Units
tai16kseq
Array Integrity time for sequential sequence on 16KB block.
—
—
512 x
Tperiod x
Nread
—
2
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
81
Maximum junction temperature 165°C
Table 33. Flash memory Array Integrity and Margin Read specifications (continued)
Symbol
Characteristic
Min
Typical
Max1
Units
tai32kseq
Array Integrity time for sequential sequence on 32KB block.
—
—
1024 x
Tperiod x
Nread
—
tai64kseq
Array Integrity time for sequential sequence on 64KB block.
—
—
2048 x
Tperiod x
Nread
—
tai256kseq
Array Integrity time for sequential sequence on 256KB block.
—
—
8192 x
Tperiod x
Nread
—
tmr16kseq
Margin Read time for sequential sequence on 16KB block.
73.81
—
110.7
μs
tmr32kseq
Margin Read time for sequential sequence on 32KB block.
128.43
—
192.6
μs
tmr64kseq
Margin Read time for sequential sequence on 64KB block.
237.65
—
356.5
μs
tmr256kseq
Margin Read time for sequential sequence on 256KB block.
893.01
—
1,339.5
μs
2
1. Array Integrity times need to be calculated and is dependant on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
3.16.2.3
Symbol
Array P/E
cycles
Data
retention
Flash memory module life specifications
Table 34. Flash memory module life specifications
Characteristic
Conditions
Min
Typical
Units
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.1
-
250,000
-
P/E
cycles
Number of program/erase cycles per block
for 256 KB blocks.2
-
1,000
250,000
P/E
cycles
Minimum data retention.
Blocks with 0 - 1,000 P/E
cycles.
50
-
Years
Blocks with 100,000 P/E
cycles.
20
-
Years
Blocks with 250,000 P/E
cycles.
10
-
Years
1. Program and erase supported across standard temperature specs. Up to 10,000 program and erase cycles may be done
between 150 °C and 165 °C out of the total specified number of cycles.
2. Program and erase supported across standard temperature specs.
3.16.2.4
Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the
following figure. The spec window represents qualified limits. The extrapolated dotted
line demonstrates technology capability, however is beyond the qualification limits.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
82
NXP Semiconductors
Maximum junction temperature 165°C
3.16.2.5
Symbol
Flash memory AC timing specifications
Table 35. Flash memory AC timing specifications
Characteristic
Min
Typical
Max
Units
tpsus
Time from setting the MCR-PSUS bit until MCR-DONE bit is set
to a 1.
—
9.4 plus
four
system
clock
periods
11.5 plus
four
system
clock
periods
μs
tesus
Time from setting the MCR-ESUS bit until MCR-DONE bit is set
to a 1.
—
16 plus
four
system
clock
periods
20.8 plus
four
system
clock
periods
μs
tres
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low.
—
—
100
ns
tdone
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—
—
5
ns
tdones
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
—
16 plus
four
system
clock
periods
20.8 plus
four
system
clock
periods
μs
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
83
Maximum junction temperature 165°C
Table 35. Flash memory AC timing specifications (continued)
Symbol
tdrcv
Characteristic
Time to recover once exiting low power mode.
Min
Typical
Max
Units
16 plus
seven
system
clock
periods.
—
45 plus
seven
system
clock
periods
μs
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin Read
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP
—
—
5
ns
taistop
Time from 1 to 0 transition of UTO-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request.
—
—
80
ns
Time from 1 to 0 transition of UTO-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request.
10.36
tmrstop
plus fifteen
system
clock
periods
—
plus four
system
clock
periods
20.42
μs
plus four
system
clock
periods
3.16.3 Flash memory read wait-state and address-pipeline control
settings
The following table describes the recommended settings of the Flash Memory
Controller's PFCR1[RWSC] and PFCR1[APC] fields at various operating frequencies,
based on specified intrinsic flash memory access times of the C55FMC array at 150°C.
NOTE
If the user does not follow these recommended settings, the user
must run the flash memory's array integrity (AI) check with
breakpoints disabled: Set the Array Integrity Break Point
Enable bit in the C55FMC's UTest 0 register
(C55FMC_UT0[AIBPE]) to 0.
Table 36. Flash memory read wait-state and address-pipeline control combinations
Operating frequency (fCPU = SYS_CLK)
RWSC
APC
Flash read latency
on mini-cache miss
(# of fCPU clock
periods)
0 MHz < fCPU ≤ 30 MHz
0
0
3
1
33 MHz < fCPU ≤ 100 MHz
30 MHz < fCPU ≤ 90 MHz
2
1
5
1
100 MHz < fCPU ≤ 133 MHz
90 MHz < fCPU ≤ 120 MHz
3
1
6
1
–40°C to 150°C
Max 165°C option
0 MHz < fCPU ≤ 33 MHz
Flash read latency
on mini-cache hit
(# of fCPU clock
periods)
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
84
NXP Semiconductors
Maximum junction temperature 165°C
Table 36. Flash memory read wait-state and address-pipeline control combinations
(continued)
Operating frequency (fCPU = SYS_CLK)
RWSC
APC
Flash read latency
on mini-cache miss
(# of fCPU clock
periods)
120 MHz < fCPU ≤ 150 MHz
4
1
7
1
150 MHz < fCPU ≤ 180 MHz
5
2
8
1
–40°C to 150°C
Max 165°C option
133 MHz < fCPU ≤ 167 MHz
167 MHz < fCPU ≤ 200 MHz
Flash read latency
on mini-cache hit
(# of fCPU clock
periods)
3.17 SGEN electrical characteristics
Table 37. SGEN electrical characteristics
Symbol
Parameter
SGEN_CL Input clock
K
APP
Sine wave amplitude (peak to peak)1, 2
MaxAPP Maximum Amplitude (peak MinAPP
AV
CV
CVV
Minimum Amplitude (peak-peak)1
Amplitude variation3
Common
Typ
Max
Unit
12
16
20
MHz
0.438
—
2.093
V
1.884
2.093
2.302
V
0.394
0.438
0.482
V
-10
—
10
%
voltage4
1.3
Common voltage variation
distortion5
V
-6
—
6
%
45
60.5
—
dB
SINAD
Signal-to-noise ratio plus
FREQ
Frequency range of the sine wave
1
—
50
kHz
FRP
Frequency precision of the sine wave (peak to peak variation)
–5
—
5
%
CLoad
Load capacitance
25
—
100
pF
RESD
ESD Pad Resistance6
149
213
277
Ω
IOUT
Output current
0
—
100
µA
–40
—
165
°C
TJ
1.
2.
3.
4.
5.
6.
peak)1
Min
Junction temperature
Peak to Peak value is measured with no R or I load.
It is range of the typical values for room temperature.
Peak to Peak excludes noise, SINAD must be considered.
Common mode value is measured with no R or I load.
SINAD is measured at Max Peak-to-Peak voltage.
Internal device routing resistance. ESD pad resistance is in series and must be considered for max Peak-to-Peak voltages,
depending on application Iload and/or Rload.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
85
Maximum junction temperature 165°C
3.18 RESET sequence duration
This following table shows the duration of different reset sequences. See the chip's
Reference Manual for details about the reset sequences.
Table 38. RESET sequences
Symbol
Parameter
Conditions
TReset
Unit
Min
Typ
Max1
TDRB
'Destructive' reset sequence, BIST enabled
Self test clock in STCU is
the PLL generated clock.
Self test configuration as
per DCF record
programming. For four
LBIST partitions in design,
two LBIST partitions are
run in parallel.
—
—
18.0
ms
TDR
'Destructive' reset sequence, BIST disabled
—
—
440
480
μs
TERLB
External reset sequence—long, BIST enabled
Self test clock in STCU is
the PLL generated clock.
Self test configuration as
per DCF record
programming. For four
LBIST partitions in design,
two LBIST partitions are
run in parallel.
—
—
17.5
ms
TERL
External reset sequence—long, BIST disabled
—
—
120
150
μs
TFRL
Functional reset sequence—long
—
—
165
180
μs
TFRS
Functional reset sequence—short
—
—
10.0
12.0
μs
1. The maximum value applies only if the reset sequence duration is not prolonged by an extended assertion of RESET_B by
an external reset generator.
3.19 AC specifications
AC Parameters are specified over the full operating junction temperature range of -40°C
to +165°C and for the full operating range of the VDD_IO supply defined in DC electrical
characteristics.
Table 39. Functional Pad AC Specifications
Symbol
Prop. Delay (ns)1
Rise/Fall Edge (ns)
L>H/H>L
I/O (output)
Drive Load
(pF)
Min
Max
Min
Max
2.5/2.5
7.5/7.5
0.9/0.9
3/3
50
—
—
—
12/12
200
SIUL2_MSCRn's
SRC[1:0] field
MSB,LSB
11
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
86
NXP Semiconductors
Maximum junction temperature 165°C
Table 39. Functional Pad AC Specifications
(continued)
Prop. Delay (ns)1
Symbol
Rise/Fall Edge (ns)
L>H/H>L
I/O (input)
Drive Load
(pF)
Min
Max
Min
Max
—
8/8
—
3.5/3.5
25
—
11.5/11.5
—
6.5/6.5
50
—
—
—
30/30
200
—
45/45
—
25/25
50
—
65/65
—
30/30
200
—
75/75
—
40/40
50
—
110/110
—
50/50
200
—
1.5/1.5
—
0.5/0.5
0.5
SIUL2_MSCRn's
SRC[1:0] field
MSB,LSB
10
01
002
NA
1. As measured from 50% of core side input to Voh/Vol of the output
2. Slew rate control modes
3.19.1 Reset pad (EXT_POR, RESET) electrical characteristics
The device implements a dedicated bidirectional RESET pin.
AA
A
VDD_HV_IOx
IO
VDDMIN
PORST
VIH
VIL
device reset forced by PORST
device start-up phase
Figure 9. Start-up reset requirements
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
87
Maximum junction temperature 165°C
VPORST
hw_rst
VDD_HV_IO
IO
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
filtered by
lowpass filter
WFRST
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 10. Noise filtering on reset signal
Table 40. Reset (RESET) electrical characteristics
Symbol
VIH
Parameter
Conditions
Input high level TTL (Schmitt Trigger)
—
Value
Min
Typ
Max
2.0
—
VDD_HV_IO
Unit
V
+ 0.4
VIL
Input low level TTL (Schmitt Trigger)
—
–0.4 —
0.8
V
VHYS
Input hysteresis TTL (Schmitt Trigger)
—
300
—
—
mV
IOL_R
Strong pull-down current
Device under power-on reset
0.2
—
—
mA
15
—
—
VDD_HV_A=1.0 V
VOL = 0.35*VDD_HV_IO
Device under power-on reset
mA
VDD_HV_IO=3.0 V
VOL = 0.35*VDD_HV_IO
WFRST
(RESET)-input filtered pulse
—
—
—
500
ns
WNFRST
(RESET)-input not filtered pulse
—
2
—
—
µs
Weak pull-down current absolute value
RESET pin
30
—
80
µA
|IWPD|
VIN = VDD
MPC5744P Data Sheet, Rev. 6.1, 11/2017
88
NXP Semiconductors
Maximum junction temperature 165°C
Table 41. Reset (EXT_POR) electrical characteristics
Symbol
Parameter
WFPORST
Conditions
PORST input filtered pulse
WNFPORST PORST input not filtered pulse
WIH
Input high level
Value
Unit
Min
Typ
Max
—
—
—
500
ns
—
2000 —
—
ns
—
2
VDD_HV_IO
V
—
+0.4
WIL
Input low level
—
-0.4
—
0.8
V
3.19.2 WKUP/NMI timing
Table 42. WKUP/NMI glitch filter
Symbol
Parameter
Min
Typ
Max
Unit
WFNMI
NMI pulse width that is rejected
—
—
20
ns
WNFNMI
NMI pulse width that is passed
400
—
—
ns
3.19.3 Debug/JTAG/Nexus/Aurora timing
3.19.3.1
JTAG interface timing
Table 43. JTAG pin AC electrical characteristics 1
#
Symbol
Characteristic
Min
Max
Unit
1
tJCYC
TCK Cycle Time
36
—
ns
2
tJDC
TCK Clock Pulse Width
40
60
%
3
tTCKRISE
TCK Rise and Fall Times (40% - 70%)
—
3
ns
4
tTMSS, tTDIS
TMS, TDI Data Setup Time
5
—
ns
5
tTMSH, tTDIH
TMS, TDI Data Hold Time
5
—
ns
6
tTDOV
TCK Low to TDO Data Valid
—
15
ns
7
tTDOI
TCK Low to TDO Data Invalid
0
—
ns
8
tTDOHZ
TCK Low to TDO High Impedance
—
15
ns
9
tJCMPPW
JCOMP Assertion Time
100
—
ns
10
tJCMPS
JCOMP Setup Time to TCK Low
40
—
ns
11
tBSDV
TCK Falling Edge to Output Valid
—
600
ns
12
tBSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
—
600
ns
13
tBSDHZ
TCK Falling Edge to Output High Impedance
—
600
ns
14
tBSDST
Boundary Scan Input Valid to TCK Rising Edge
15
—
ns
15
tBSDHT
TCK Rising Edge to Boundary Scan Input Invalid
15
—
ns
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
89
Maximum junction temperature 165°C
1. These specifications apply to JTAG boundary scan only.
TCK
2
3
2
3
1
Figure 11. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
7
8
TDO
Figure 12. JTAG test access port timing
MPC5744P Data Sheet, Rev. 6.1, 11/2017
90
NXP Semiconductors
Maximum junction temperature 165°C
TCK
10
JCOMP
9
Figure 13. JTAG JCOMP timing
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 14. JTAG boundary scan timing
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
91
Maximum junction temperature 165°C
3.19.3.2
Nexus timing
Table 44. Nexus debug port timing 1
No.
Symbol
1
tMCYC
2
Parameter
Conditions
Min
Max
Unit
MCKO Cycle Time
—
15.6
—
ns
tMDC
MCKO Duty Cycle
—
40
60
%
3
tMDOV
MCKO Low to MDO, MSEO, EVTO Data
Valid2
—
–0.1
0.25
tMCYC
4
tEVTIPW
EVTI Pulse Width
—
4
—
tTCYC
5
tEVTOPW
EVTO Pulse Width
—
1
—
tMCYC
—
62.5
—
ns
Time3
6
tTCYC
TCK Cycle
7
tTDC
TCK Duty Cycle
—
40
60
%
8
tNTDIS, tNTMSS
TDI, TMS Data Setup Time
—
8
—
ns
9
tNTDIH, tNTMSH
TDI, TMS Data Hold Time
—
5
—
ns
10
tJOV
TCK Low to TDO/RDY Data Valid
—
0
25
ns
1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured
from 50% of MCKO and 50% of the respective signal.
2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3. The system clock frequency needs to be four times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
Figure 15. Nexus output timing
EVTI
4
Figure 16. Nexus EVTI Input Pulse Width
MPC5744P Data Sheet, Rev. 6.1, 11/2017
92
NXP Semiconductors
Maximum junction temperature 165°C
6
7
TCK
8
9
TMS, TDI
10
TDO/RDY
Figure 17. Nexus TDI, TMS, TDO timing
3.19.3.3
Aurora LVDS driver electrical characteristics
Symbol
Table 45. Aurora LVDS driver electrical characteristics
Parameter1
Value
Unit
Min
Typ
Max
—
1250
Typ+0.1%
Mbps
Data Rate
DATARATE
Data rate
TSTRT_BIAS
Bias startup time2
—
—
5
µs
TSTRT_TX
Transmitter startup time3
—
—
5
µs
—
—
4
µs
STARTUP
TSTRT_RX
Receiver startup
time4
1. Conditions for these values are VDD_HV_IO = 3.3 V (–5%, +10%), TJ = –40 to 150 °C
2. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
93
Maximum junction temperature 165°C
3. Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is
guaranteed only after the startup time.
4. Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is
guaranteed only after the startup time.
3.19.3.4
Nexus Aurora debug port timing
Table 46. Nexus Aurora debug port timing
#
Symbol
Characteristic
Min
Max
Unit
1
tREFCLK
Reference clock frequency
625
1250
MHz
2
tRCDC
Reference Clock Duty Cycle
45
55
%
3
JRC
Reference Clock jitter
—
40
ps
4
tSTABILITY
Reference Clock Stability
50
—
PPM
5
BER
Bit Error Rate
—
10-12
—
6
JD
Transmit lane Deterministic Jitter
—
0.17
OUI
7
JT
Transmit lane Total Jitter
—
0.35
OUI
8
SO
Differential output skew
—
20
ps
9
SMO
Lane to lane output skew
—
1000
ps
10
UI
Aurora lane Unit Interval
800
1600
ps
MPC5744P Data Sheet, Rev. 6.1, 11/2017
94
NXP Semiconductors
Maximum junction temperature 165°C
1
2
2
CLOCKREF Zero Crossover
CLOCKREF +
8
8
8
Tx Data Ideal Zero Crossover
Tx Data +
Tx Data [n]
Zero Crossover
Tx Data [n+1]
Zero Crossover
Tx Data [m]
Zero Crossover
9
9
Figure 18. Nexus Aurora timings
Rise/fall timing for the Nexus Aurora debug port reference clock must conform to the
area between the minimum and maximum value ranges shown in the following receiver
"eye" diagram.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
95
Maximum junction temperature 165°C
Figure 19. Nexus Aurora receiver "eye" diagram
3.19.4 External interrupt timing (IRQ pin)
Table 47. External interrupt timing
#
Symbol
Parameter
Conditions
Min
Max
Unit
1
tIPWL
IRQ pulse width low
—
3
—
tCYC
2
tIPWH
IRQ pulse width high
—
3
—
tCYC
—
6
—
tCYC
3
tICYC
IRQ edge to edge
time1
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both
MPC5744P Data Sheet, Rev. 6.1, 11/2017
96
NXP Semiconductors
Maximum junction temperature 165°C
IRQ
1
2
3
Figure 20. External interrupt timing
3.19.5 SPI timing
Table 48. SPI timing
#
Symbol
Parameter
Conditions
Min
Max
Unit
1
tSCK
SPI cycle time
Master (MTFE = 0)
40
—
ns
Slave (MTFE = 0)
40
—
16
—
Slave Receive Only
Mode1
2
tCSC
PCS to SCK delay
—
16
—
ns
3
tASC
After SCK delay
—
16
—
ns
4
tSDC
SCK duty cycle
—
tSCK/2 – 4
tSCK/2 + 4
ns
5
tA
Slave access time
SS active to SOUT valid
—
40
ns
6
tDIS
Slave SOUT disable
time
SS inactive to SOUT High-Z or invalid
—
25
ns
7
tPCSC
PCSx to PCSS time
—
13
—
ns
8
tPASC
PCSS to PCSx time
—
13
—
ns
9
tSUI
Data setup time for
inputs
Master (MTFE = 0)
16
—
ns
Slave
2
—
(P2
10
11
12
tHI
tSUO
Data hold time for
inputs
Data valid (after SCK
edge) time for outputs
tHO
Data hold time for
outputs
Master (MTFE = 1, CPHA = 0)
16 –
x
tSYS, 3)
—
Master (MTFE = 1, CPHA = 1)
16
—
Master (MTFE = 0)
–3
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
–3 + (P2 x
tSYS, 3)
—
Master (MTFE = 1, CPHA = 1)
–3
—
Master (MTFE = 0)
—
4
Slave
—
17
Master (MTFE = 1, CPHA = 0)
—
4 + tSYS3
Master (MTFE = 1, CPHA = 1)
—
4
Master (MTFE = 0)
–4
—
Slave
3.6
—
ns
ns
ns
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
97
Maximum junction temperature 165°C
Table 48. SPI timing (continued)
#
Symbol
Parameter
Conditions
Min
Max
Master (MTFE = 1, CPHA = 0)
–4
—
Master (MTFE = 1, CPHA = 1)
–4
—
Unit
1. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the SPI can receive data on SIN,
but no valid data is transmitted on SOUT.
2. P is the number of clock cycles added to delay the SPI input sample point and is software programmable.
3. tSYS is the period of the DSPI_CLKn clock, the input clock to the SPI module. Maximum frequency is 50 MHz (min tSYS =
20 ns).
NOTE
For numbers shown in the following figures, see Table 48.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Figure 21. DSPI classic SPI timing — master, CPHA = 0
MPC5744P Data Sheet, Rev. 6.1, 11/2017
98
NXP Semiconductors
Maximum junction temperature 165°C
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
First Data
SIN
Last Data
12
SOUT
First Data
11
Data
Last Data
Figure 22. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Figure 23. DSPI classic SPI timing — slave, CPHA = 0
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
99
Maximum junction temperature 165°C
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Figure 24. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
First Data
10
12
SOUT
First Data
Last Data
Data
11
Data
Last Data
Figure 25. DSPI modified transfer format timing — master, CPHA = 0
MPC5744P Data Sheet, Rev. 6.1, 11/2017
100
NXP Semiconductors
Maximum junction temperature 165°C
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Figure 26. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Figure 27. DSPI modified transfer format timing – slave, CPHA = 0
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
101
Maximum junction temperature 165°C
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Figure 28. DSPI modified transfer format timing — slave, CPHA = 1
7
8
PCSS
PCSx
Figure 29. DSPI PCS strobe (PCSS) timing
3.19.6 LFAST
MPC5744P Data Sheet, Rev. 6.1, 11/2017
102
NXP Semiconductors
Maximum junction temperature 165°C
3.19.6.1
LFAST interface timing diagrams
Figure 30. LFAST timing definition
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
103
Maximum junction temperature 165°C
H
lfast_pwr_down
L
Tsu
Differential TX
Data Lines
pad_p/pad_n
Data Valid
Figure 31. Power-down exit time
VIH
Differential TX
Data Lines
90%
10%
pad_p/pad_n
VIL
Tfall
Trise
Figure 32. Rise/fall time
3.19.6.2
Symbol
VDD_HV_IO
LFAST interface electrical characteristics
Table 49. LFAST electrical characteristics
Conditions1
Parameter
Value
Unit
Min
Typ
Max
3.15
—
3.6
V
—
312/320
Typ+0.1%
Mbps
—
—
0.5
3
µs
Operating supply conditions
Data Rate
DATARATE
Data rate
—
STARTUP
TSTRT_BIAS
Bias startup
time2
TPD2NM_TX
Transmitter startup time (power
down to normal mode)3
—
—
0.2
2
µs
TSM2NM_TX
Transmitter startup time (sleep
mode to normal mode)
—
—
0.2
0.5
µs
TPD2NM_RX
Receiver startup time5 (Power down
to Normal mode)
—
—
20
40
ns
TPD2SM_RX
Receiver startup time4 (Power down
to Sleep mode)
—
—
20
50
ns
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
104
NXP Semiconductors
Maximum junction temperature 165°C
Table 49. LFAST electrical characteristics
(continued)
Symbol
Conditions1
Parameter
Value
Unit
Min
Typ
Max
TRANSMITTER
VOS_DRF
Common mode voltage
—
1.18
—
1.32
V
|ΔVOD_DRF|
Differential output voltage swing
(terminated)
—
100
200
285
mV
TTR_DRF
Rise/Fall time (10% - 90% of swing)
—
0.26
—
1.5
ns
ROUT_DRF
Terminating resistance
—
67
—
198
Ω
COUT_DRF
Capacitance6
—
—
—
5
pF
RECEIVER
VICOM_DRF
Common mode voltage
—
0.157
—
1.68
V
|DVI_DRF|
Differential input voltage
—
100
—
—
mV
RIN_DRF
Terminating resistance
—
80
115
150
Ω
CIN_DRF
Capacitance9
—
—
3.5
6
pF
LIN_DRF
Parasitic Inductance10
—
—
5
10
nH
1. VDD_VH_IO = 3.3 V -5%,+10%, TJ = –40 to 165 °C, unless otherwise specified
2. Startup time is defined as the time taken by LFAST current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LFAST functionality is guaranteed only after the startup time.
3. Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the
startup time.
4. Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the
startup time.
5. Startup time is defined as the time taken by LFAST receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the
startup time.
6. Total lumped capacitance including silicon, package pin and bond wire. Application board simulation is needed to verify
LFAST template compliancy.
7. Absolute min = 0.15 V – (285 mV / 2) = 0 V
8. Absolute max = 1.6 V + (285 mV / 2) = 1.743 V
9. Total capacitance including silicon, package pin and bond wire
10. Total inductance including silicon, package pin and bond wire
Table 50. LFAST electrical characteristics1
Symbol
Parameter
Conditions
Value
Unit
Min
Nominal
Max
FRF_REF
SysClk Frequency
—
10
—
26
MHz
ERRREF
SysClk Frequency Error
—
-1
—
1
%
DCREF
SysClk Duty Cycle
—
45
—
55
%
CLOAD
Output Buffer Load Capacitance
—
—
—
10
pF
RLOAD
Output Buffer Load Resistance
—
10
—
—
kΩ
20 MHz
—
—
-58
dBc
10 MHz
—
—
-64
dBc
PN
Integrated Phase Noise (single side band)
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
105
Maximum junction temperature 165°C
Table 50. LFAST electrical characteristics1 (continued)
Symbol
Parameter
Conditions
Value
Unit
Min
Nominal
Max
FVCO
PLL VCO Frequency
—
—
320
—
MHz
TLOCK
PLL Phase Lock
—
—
—
40
µs
ΔPER
PLL Long Term Jitter (peak to peak)
—
—
—
600
ps
1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.
3.19.7 FlexRay
3.19.7.1
FlexRay timing parameters
This section provides the FlexRay interface timing characteristics for the input and output
signals. These numbers are recommended per the FlexRay Electrical Physical Layer
Specification, Version 3.0.1, and subject to change per the final timing analysis of the
device.
3.19.7.2
TxEN
TxEN
80 %
20 %
dCCTxENFALL
dCCTxENRISE
Figure 33. FlexRay TxEN signal
MPC5744P Data Sheet, Rev. 6.1, 11/2017
106
NXP Semiconductors
Maximum junction temperature 165°C
Table 51. TxEN output characteristics1
Name
Description
Min
Max
Unit
dCCTxENRISE25
Rise time of TxEN signal at CC
—
9
ns
dCCTxENFALL25
Fall time of TxEN signal at CC
—
9
ns
dCCTxEN01
Sum of delay between Clk to Q of the last FF and the final
output buffer, rising edge
—
25
ns
dCCTxEN10
Sum of delay between Clk to Q of the last FF and the final
output buffer, falling edge
—
25
ns
1. All parameters specified for VDD_HV_IO = 3.3 V -5%, +10%, TJ = –40 °C / 165 °C, TxEN pin load maximum 25 pF
PE_Clk
TxEN
dCCTxEN10
dCCTxEN01
Figure 34. FlexRay TxEN signal propagation delays
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
107
Maximum junction temperature 165°C
3.19.7.3
TxD
TxD
dCCTxD50%
80 %
50 %
20 %
dCCTxDRISE
dCCTxDFALL
Figure 35. FlexRay TxD signal
Table 52. TxD output characteristics
Description1
Name
dCCTxAsym
Min
Max
Unit
–2.45
2.45
ns
—
9
ns
Asymmetry of sending CC @ 25 pF load
(=dCCTxD50% - 100 ns)
dCCTxDRISE25+dCCTx Sum of Rise and Fall time of TxD signal at the output
DFALL25
dCCTxD01
Sum of delay between Clk to Q of the last FF and the final
output buffer, rising edge
—
25
ns
dCCTxD10
Sum of delay between Clk to Q of the last FF and the final
output buffer, falling edge
—
25
ns
1. All parameters specified for VDD_HV_IO = 3.3 V -5%, +10%, TJ = –40 °C / 165 °C, TxD pin load maximum 25 pF
MPC5744P Data Sheet, Rev. 6.1, 11/2017
108
NXP Semiconductors
Maximum junction temperature 165°C
PE_Clk*
TxD
dCCTxD10
dCCTxD01
*FlexRay Protocol Engine Clock
Figure 36. FlexRay TxD signal propagation delays
3.19.7.4
RxD
Table 53. RxD input characteristic
Name
Description1
Min
Max
Unit
C_CCRxD
Input capacitance on RxD pin
—
7
pF
uCCLogic_1
Threshold for detecting logic high
35
70
%
uCCLogic_0
Threshold for detecting logic low
30
65
%
dCCRxD01
Sum of delay from actual input to the D
input of the first FF, rising edge
—
10
ns
dCCRxD10
Sum of delay from actual input to the D
input of the first FF, falling edge
—
10
ns
1. All parameters specified for VDD_HV_IO = 3.3 V -5%, +10%, TJ = –40 / 165 °C
3.19.7.5
Receiver asymmetry
Table 54. Receiver asymmetry
Name
Description
Min
Max
Unit
dCCRxAsymAccept15
Acceptance of asymmetry at receiving CC with 15 pF load (*)
–31.5
+44.0
ns
dCCRxAsymAccept25
Acceptance of asymmetry at receiving CC with 25 pF load (*)
–30.5
+43.0
ns
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
109
Maximum junction temperature 165°C
3.19.8 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
3.19.8.1
MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 55. MII signal switching specifications
Symbol
—
Description
RXCLK frequency
Min.
Max.
Unit
—
25
MHz
MII1
RXCLK pulse width high
35%
65%
RXCLK
MII2
RXCLK pulse width low
35%
65%
RXCLK
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
5
—
ns
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
TXCLK frequency
—
25
MHz
35%
65%
TXCLK
period
period
—
MII5
TXCLK pulse width high
period
MII6
TXCLK pulse width low
35%
65%
TXCLK
period
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
2
—
ns
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
MII6
MII5
TXCLK (input)
MII8
MII7
TXD[n:0]
Valid data
TXEN
Valid data
TXER
Valid data
Figure 37. RMII/MII transmit signal timing diagram
MPC5744P Data Sheet, Rev. 6.1, 11/2017
110
NXP Semiconductors
Obtaining package dimensions
MII2
MII1
MII3
MII4
RXCLK (input)
RXD[n:0]
Valid data
RXDV
Valid data
RXER
Valid data
Figure 38. RMII/MII receive signal timing diagram
3.19.8.2
RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 56. RMII signal switching specifications
Num
—
Description
EXTAL frequency (RMII input clock RMII_CLK)
Min.
Max.
Unit
—
50
MHz
RMII1
RMII_CLK pulse width high
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
4
—
ns
RMII4
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
2
—
ns
RMII7
RMII_CLK to TXD[1:0], TXEN invalid
4
—
ns
RMII8
RMII_CLK to TXD[1:0], TXEN valid
—
15
ns
4 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
Then use this document number
144-pin LQFP
98ASS23177W
257-ball MAPBGA
98ASA00081D
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
111
Ordering information
5 Ordering information
M PC 5744P G K0 K LQ 9
R
Qualification status
Core code (Power Architecture)
Device number
E = Ethernet
F = FlexRay
G = both
(blank) = neither
Fab and mask identifier
Temperature range
Package identifier
Operating frequency
Tape and reel status
Temperature range
Package identifier
Operating frequency Qualification status
9 = 200 MHz
M = –40°C to +125°C LQ = 144 LQFP
K = –40°C to +135°C MM = 257 MAPBGA 8 = 180 MHz
for extended temp
5 = 150 MHz
(+165°C TJ)
Tape and reel status
R = Tape and reel
P = Pre-qualification
M = Fully spec. qualified, general market flow (blank) = Trays
S = Fully spec. qualified, automotive flow
Note: Not all options are available on all devices.
Table 57. Orderable part number examples
Part number1
Flash/SRAM
Package
Other features
SPC5744PFK1MLQ9
2.5 MB/384 KB
144 LQFP (Pb free)
-40 to +125 °C
SPC5744PGK1MMM9
2.5 MB/384 KB
257 MAPBGA (Pb free)
Ethernet interface
LFAST interface
Nexus Aurora
-40 to +125 °C
SPC5743PFK1MLQ9
2 MB/256 KB
144 LQFP (Pb free)
-40 to +125 °C
SPC5743PGK1MMM9
2 MB/256 KB
257 MAPBGA (Pb free)
Ethernet interface
LFAST interface
Nexus Aurora
-40 to +125 °C
SPC5742PFK1MLQ9
1.5 MB/192 KB
144 LQFP (Pb free)
-40 to +125 °C
SPC5742PGK1MMM9
1.5 MB/192 KB
257 MAPBGA (Pb free)
Ethernet interface
LFAST interface
Nexus Aurora
-40 to +125 °C
SPC5741PFK1MLQ9
1 MB/128 KB
144 LQFP (Pb free)
-40 to +125 °C
SPC5741PGK1MMM9
1 MB/128 KB
257 MAPBGA (Pb free)
Ethernet interface
LFAST interface
Nexus Aurora
-40 to +125 °C
MPC5744P Data Sheet, Rev. 6.1, 11/2017
112
NXP Semiconductors
Document revision history
1. All packaged devices are PPC, rather than MPC or SPC, until product qualifications are complete. Not all configurations
are available in the PPC parts.
6 Document revision history
The following table summarizes revisions to this document since the previous release.
Table 58. Revision history
Revision
Date
6
05/2017
Description of changes
Changed Freescale to NXP throughout the document.
Extensively updated Generic pins/balls.
Absolute maximum ratings
• In Table 12
• for row set IINJ changed "Maximum DC injection current per pin, 5 V pads" to "Maximum
DC injection current per pin, 5V ADC pads".
• For row set IINJ updated the footnote.
Voltage regulator electrical characteristics
• In Table 17
• Added the note, "The device has to..........which drives the EXT_POR".
• In existing row Cld added Maximum value 18.8.
• In existing row Cpd added Maximum value 300.
• Renamed parameter from "Load Current transient" to "Load current transient time" and
updated the Min and Max value.
• Renamed the following parameters:
• Supply ramp rate VDD12_CORE to Supply ramp rate VDD_LV_COR
• Supply ramp rate VDD33_REG to Supply ramp rate VDD_HV_PMU
• POR VDD12_CORE to POR_COR
• POR VDD33_REG to POR_PMU
• In Figure 4 changed VDD33_REG to VDD_HV_PMU.
16 MHz Internal RC Oscillator (IRCOSC) electrical specifications
• In Table 26
• Changed the Min and Max values for IRCOSC frequency (untrimmed) parameter.
• Added IRC frequency variation with temperature and voltage compensation parameter
row.
ADC electrical characteristics
• Changed the Note from "Unless noted otherwise, the specifications in Table 27 assume the
use of 13-bit resolution: In ADC_CALBISTREG, set OPMODE to 110b" to "Unless noted
otherwise, the specifications in Table 27 assume the use of 12-bit resolution (high accuracy,
recommended): In ADC_CALBISTREG, set OPMODE to 110b".
• In Table 27 for existing rows tsample and tconv changed the "13 bit resolution" to "12-bit
resolution (high accuracy, recommended)".
• In Flash memory program and erase specifications changed symbols for specifications:
• Quad-page (1024 bits) program time: Changed symbol from tqppgn to tqppgm
• 16 KB Block program time: Changed symbol from t16kpgn to t16kpgm
• In Flash memory Array Integrity and Margin Read specifications incorporated minor editorial
changes
• In Flash memory AC timing specifications for tpsus:
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
113
Document revision history
Table 58. Revision history (continued)
Revision
Date
Description of changes
• Changed Typical from 7 µs plus four system clock periods to 9.4 µs plus four system
clock periods
• Changed Max from 9.1 µs plus four system clock periods to 11.5 µs plus four system
clock periods
SGEN electrical characteristics
• Extensively updated the Table 37
LFAST interface electrical characteristics
• In Table 49 for row set |ΔVOD_DRF| deleted the ± from the Max, Typ, and Min values.
• In Table 49, removed the row set VHYS_DRF
6.1
10/2017
• In Voltage regulator electrical characteristics changed the note, from "The device has
to..........which drives the EXT_POR" to "When the external regulator........regulator modes for
safety operation".
MPC5744P Data Sheet, Rev. 6.1, 11/2017
114
NXP Semiconductors
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Revision 6.1, 11/2017
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