SPC5745BFK1AVKU2

NXP Semiconductors Data Sheet: Technical Data Document Number MPC5746C Rev. 6, 11/2018 MPC5746C MPC5746C Microcontroller Datasheet Features • 1 × 160 MHz Power Architecture® e200z4 Dual issue, 32-bit CPU – Single precision floating point operations – 8 KB instruction cache and 4 KB data cache – Variable length encoding (VLE) for significant code density improvements • 1 x 80 MHz Power Architecture® e200z2 Single issue, 32-bit CPU – Using variable length encoding (VLE) for significant code size footprint reduction • End to end ECC – All bus masters, for example, cores, generate a single error correction, double error detection (SECDED) code for every bus transaction – SECDED covers 64-bit data and 29-bit address • Memory interfaces – 3 MB on-chip flash memory supported with the flash memory controller – 3 x flash memory page buffers (3-port flash memory controller) – 384 KB on-chip SRAM across three RAM ports • Clock interfaces – 8-40 MHz external crystal (FXOSC) – 16 MHz IRC (FIRC) – 128 KHz IRC (SIRC) – 32 KHz external crystal (SXOSC) – Clock Monitor Unit (CMU) – Frequency modulated phase-locked loop (FMPLL) – Real Time Counter (RTC) • System Memory Protection Unit (SMPU) with up to 32 region descriptors and 16-byte region granularity • 16 Semaphores to manage access to shared resources • Interrupt controller (INTC) capable of routing interrupts to any CPU • 32-channel eDMA controller with multiple transfer request sources using DMAMUX • Boot Assist Flash (BAF) supports internal flash programming via a serial link (SCI) • Analog – Two analog-to-digital converters (ADC), one 10-bit and one 12-bit – Three analog comparators – Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or from the PIT • Communication – Four Deserial Serial Peripheral Interface (DSPI) – Four Serial Peripheral interface (SPI) – 16 serial communication interface (LIN) modules – Eight enhanced FlexCAN3 with FD support – Four inter-IC communication interface (I2C) – ENET complex (10/100 Ethernet) that supports Multi queue with AVB support, 1588, and MII/ RMII – Dual-channel FlexRay controller • Audio – Synchronous Audio Interface (SAI) – Fractional clock dividers (FCD) operating in conjunction with the SAI • Configurable I/O domains supporting FlexCAN, LINFlexD, Ethernet, and general I/O • Supports wake-up from low power modes via the WKPU controller • On-chip voltage regulator (VREG) • Debug functionality – e200z2 core:NDI per IEEE-ISTO 5001-2008 Class3+ – e200z4 core: NDI per IEEE-ISTO 5001-2008 Class 3+ • Crossbar switch architecture for concurrent access to peripherals, flash memory, and RAM from multiple bus masters NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. • Timer – 16 Periodic Interrupt Timers (PITs) – Two System Timer Modules (STM) – Three Software Watchdog Timers (SWT) – 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels • Device/board boundary Scan testing supported with Joint Test Action Group (JTAG) of IEEE 1149.1 and IEEE 1149.7 (CJTAG) • Security – Hardware Security Module (HSMv2) – Password and Device Security (PASS) supporting advanced censorship and life-cycle management – One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts • Functional Safety – ISO26262 ASIL-B compliance • Multiple operating modes – Includes enhanced low power operation MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 2 NXP Semiconductors Table of Contents 1 Block diagram.................................................................................... 4 2 Family comparison.............................................................................4 3 Ordering parts.....................................................................................8 6.3.3 Flash memory module life specifications............... 40 3.1 Determining valid orderable parts ..........................................8 6.3.4 Data retention vs program/erase cycles.................. 40 3.2 Ordering Information ............................................................. 9 6.3.5 Flash memory AC timing specifications................ 41 General............................................................................................... 9 6.3.6 Flash read wait state and address pipeline control 4 5 6 6.3.2 Flash memory Array Integrity and Margin Read specifications.......................................................... 39 4.1 Absolute maximum ratings..................................................... 9 settings ................................................................... 42 4.2 Recommended operating conditions....................................... 11 4.3 Voltage regulator electrical characteristics............................. 13 6.4.1 DSPI timing............................................................ 43 4.4 Voltage monitor electrical characteristics............................... 17 6.4.2 FlexRay electrical specifications............................ 49 4.5 Supply current characteristics................................................. 18 6.4.2.1 FlexRay timing....................................49 4.6 Electrostatic discharge (ESD) characteristics......................... 22 6.4.2.2 TxEN................................................... 49 4.7 Electromagnetic Compatibility (EMC) specifications............ 22 6.4.2.3 TxD..................................................... 50 I/O parameters....................................................................................23 6.4.2.4 RxD..................................................... 51 6.4 Communication interfaces.......................................................43 5.1 AC specifications @ 3.3 V Range...........................................23 6.4.3 Ethernet switching specifications........................... 52 5.2 DC electrical specifications @ 3.3V Range............................24 6.4.4 SAI electrical specifications .................................. 53 5.3 AC specifications @ 5 V Range..............................................25 5.4 DC electrical specifications @ 5 V Range..............................25 6.5.1 JTAG interface timing ........................................... 55 5.5 Reset pad electrical characteristics..........................................26 6.5.2 Nexus timing...........................................................58 5.6 PORST electrical specifications..............................................28 6.5.3 WKPU/NMI timing................................................ 60 Peripheral operating requirements and behaviours............................ 28 6.5.4 External interrupt timing (IRQ pin)........................ 61 6.1 Analog..................................................................................... 28 6.1.1 ADC electrical specifications................................. 28 6.1.2 Analog Comparator (CMP) electrical 6.5 7 specifications.......................................................... 33 6.2 Clocks and PLL interfaces modules........................................34 Dimensions.........................................................................................65 8.1 9 Thermal attributes................................................................... 61 Obtaining package dimensions ...............................................65 Pinouts................................................................................................66 6.2.1 Main oscillator electrical characteristics.................34 6.2.2 32 kHz Oscillator electrical specifications ............ 36 10 Reset sequence................................................................................... 66 6.2.3 16 MHz RC Oscillator electrical specifications......36 10.1 Reset sequence........................................................................ 66 6.2.4 128 KHz Internal RC oscillator Electrical 10.1.1 Reset sequence duration..........................................66 specifications ......................................................... 37 10.1.2 BAF execution duration..........................................66 PLL electrical specifications ..................................37 10.1.3 Reset sequence description..................................... 67 6.2.5 6.3 Thermal attributes.............................................................................. 61 7.1 8 Debug specifications............................................................... 55 Memory interfaces...................................................................38 6.3.1 Flash memory program and erase specifications.... 38 9.1 Package pinouts and signal descriptions................................. 66 11 Revision History.................................................................................69 11.1 Revision History......................................................................69 MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 3 Block diagram 1 Block diagram 80 MHz e200z2 160 MHz e200z4 System bus masters 64-bit AHB 8 KB i-cache 4 KB d-cache SPFP-APU Nexus 3+ E2 E-ECC 64-bit AHB System E2 E-ECC Nexus 3+ 64-bit data E2 E-ECC Flash Memory 2xRAM E2 E-ECC E2 E-ECC 3 x SA-PF buffers 64-bit wide RAM Triple ported 256 KB array 3 MB array (inc EEE) 256 KB array Ethernet (ENET) HSMv2 eDMA Flexray SMPU Peripheral bridge E2 E-ECC WKPU 2 x STM BAF PMC FMPLL 16 MHz FIRC RTC/API DEBUG/ JTAG 2 x SWTs FCCU 16 x SEMA42 PASS 16 x PIT-RTI SSCM 32 KHz SXOSC MC_CGM, MC_PCU, MC_ME, MC_RGM 128 KHz SIRC SIUL 8–40 MHz FXOSC STCU (MBIST) MEMU CMU Padkeeper support TDM Low power unit interface (LPU) Peripheral clusters 68 ch 10-bit ADC0 31 ch 12-bit ADC1 1 x FlexCAN(PN)* (mix int and ext) 7 x FlexCAN* 16 x LINFlexD 4 x I2C 3 x analog comparator (CMP) 4 x DSPI 4 x SPI 3 x SAI 3 x FCD 2 x eMIOS + BCTU 2-core INTC DMA and 2 x channel mux 1 x CRC Register protection * All FlexCANs optionally support CAN FD Figure 1. MPC5746C block diagram 2 Family comparison The following table provides a summary of the different members of the MPC5746C family and their proposed features. This information is intended to provide an understanding of the range of functionality offered by this family. For full details of all of the family derivatives please contact your marketing representative. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 4 NXP Semiconductors Family comparison NOTE All optional features (Flash memory, RAM, Peripherals) start with lowest number or address (e.g., FlexCAN0) and end at highest available number or address (e.g., MPC574xB/C have 6 CAN, ending with FlexCAN5). Table 1. MPC5746C Family Comparison1 Feature MPC5745B MPC5744B MPC5746B MPC5744C MPC5745C MPC5746C CPUs e200z4 e200z4 e200z4 e200z4 e200z4 e200z4 e200z2 e200z2 e200z2 FPU e200z4 e200z4 e200z4 e200z4 e200z4 e200z4 Maximum Operating Frequency2 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 80MHz (Z2) 80MHz (Z2) 80MHz (Z2) Flash memory 2 MB 1.5 MB 2 MB 3 MB EEPROM support RAM 1.5 MB 3 MB Emulated up to 64K 256 KB 192 KB Emulated up to 128K 384 KB (Optional 512KB)3 192 KB ECC End to End SMPU 16 entry DMA 32 channels 10-bit ADC 36 Standard channels 256 KB 384 KB (Optional 512KB)3 32 External channels 12-bit ADC 15 Precision channels 16 Standard channels Analog Comparator 3 BCTU 1 SWT 1, SWT[0] STM 1, STM[0] PIT-RTI 24 2 16 channels PIT 1 channels RTI RTC/API Total Timer 1 I/O5 64 channels 16-bits LINFlexD FlexCAN DSPI/SPI 1 1 Master and Slave (LINFlexD[0], 11 Master (LINFlexD[1:11]) Master and Slave (LINFlexD[0], 15 Master (LINFlexD[1:15]) 6 with optional CAN FD support (FlexCAN[0:5]) 8 with optional CAN FD support (FlexCAN[0:7]) 4 x DSPI 4 x SPI Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 5 Family comparison Table 1. MPC5746C Family Comparison1 (continued) Feature MPC5745B MPC5744B MPC5746B MPC5744C I2C 4 4 4 4 SAI/I2S 3 3 3 3 FXOSC 8 - 40 MHz SXOSC 32 KHz FIRC 16 MHz SIRC 128 KHz FMPLL 1 Low Power Unit (LPU) Yes MPC5745C FlexRay 2.1 (dual channel) Yes, 128 MB Yes, 128 MB Yes, 128 MB Yes, 128 MB Ethernet (RMII, MII + 1588, Muti queue AVB support) 1 1 1 1 CRC 1 MEMU 2 STCU2 1 HSM-v2 (security) Optional Censorship Yes FCCU 1 Safety level Specific functions ASIL-B certifiable User MBIST Yes I/O Retention in Standby Yes GPI 1 (100 BGA), 17 (176 LQFP-EP), 18 (256 BGA), 18 (324 BGA) GPIO 65 (100 BGA), 129 (176 LQFP-EP), 178 (256 BGA), 246 (324 BGA) Debug JTAGC, MPC5746C cJTAG Nexus Z4 N3+ (Only available on 324BGA (development only) ) Z2 N3+ (Only available on 324BGA (development only) ) Packages 176 LQFP-EP 176 LQFP-EP 176 LQFP-EP 176 LQFP-EP 176 LQFP-EP 176 LQFP-EP 256 BGA 256 BGA 256 BGA 256 BGA 256 BGA 256 BGA, 100 BGA 100 BGA 100 BGA 100 BGA 100 BGA 324 BGA (development only) 100 BGA 1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is package dependent. 2. Based on 125°C ambient operating temperature and subject to full device characterization. 3. Contact NXP representative for part number 4. Additional SWT included when HSM option selected MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 6 NXP Semiconductors Family comparison 5. See device datasheet and reference manual for information on to timer channel configuration and functions. Table 2. MPC5746C Family Comparison - NVM Memory Map 1 Start Address End Address Flash block RWW partition MPC5744 MPC5745 MPC5746 0x01000000 0x0103FFFF 256 KB code Flash block 0 6 available available available 0x01040000 0x0107FFFF 256 KB code Flash block 1 6 available available available 0x01080000 0x010BFFFF 256 KB code Flash block 2 6 available available available 0x010C0000 0x010FFFFF 256 KB code Flash block3 6 available available available 0x01100000 0x0113FFFF 256 KB code Flash block 4 6 not available available available 0x01140000 0x0117FFFF 256 KB code Flash block 5 7 not available available available 0x01180000 0x011BFFFF 256 KB code Flash block 6 7 not available not available available 0x011C0000 0x011FFFFF 256 KB code Flash block 7 7 not available not available available 0x01200000 0x0123FFFF 256 KB code Flash block 8 7 not available not available available 0x01240000 0x0127FFFF 256 KB code Flash block 9 7 not available not available available Table 3. MPC5746C Family Comparison - NVM Memory Map 2 Start Address End Address Flash block RWW partition MPC5744B MPC5745B MPC5746B MPC5744C MPC5745C MPC5746C 0x00F900001 0x00F93FFF 16 KB data Flash 2 available available1 0x00F94000 0x00F97FFF 16 KB data Flash 2 available available1 0x00F98000 0x00F9BFFF 16 KB data Flash 2 available available1 0x00F9C000 0x00F9FFFF 16 KB data Flash 2 available available1 0x00FA0000 0x00FA3FFF 16 KB data Flash 3 not available available1 0x00FA4000 0x00FA7FFF 16 KB data Flash 3 not available available1 0x00FA8000 0x00FABFFF 16 KB data Flash 3 not available available1 0x00FAC000 0x00FAFFFF 16 KB data Flash 3 not available available1 0x00FB0000 0x00FB7FFF 32 KB data Flash Reserved 0x00FB8000 0x00FBFFFF 32 KB data Flash Reserved 0x00FC0000 0x00FC7FFF 32 KB data Flash 0 available available 0x00FC8000 0x00FCFFFF 32 KB data Flash 1 available available 0x00FD0000 0x00FD7FFF 32 KB data Flash 1 available available 0x00FD8000 0x00FDFFFF 32 KB data Flash 1 available available 0x00FE0000 0x00FEFFFF 64 KB data Flash 0 available available 0x00FF0000 0x00FFFFFF 64 KB data Flash 1 available available MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 7 Ordering parts 1. Flexible patitions for boot and EEPROM Table 4. MPC5748G Family Comparison - NVM Memory Map 3 Start Address End Address Flash block RWW MPC5744B MPC5745B MPC5746B MPC5744C MPC5745C MPC5746C 0x00610000 0x0061FFFF 64 KB HSM Code block 2 0 available available 0x00620000 0x0062FFFF 64 KB HSM Code block 3 1 available available HSM Data 0x00630000 0x00F7FFFF 9536 KB Reserved HSM Data 0x00F80000 0x00F83FFF 16 KB HSM data block 0 4 available available 0x00F84000 0x00F87FFF 16 KB HSM data block 1 5 available available 0x00F88000 0x00F8BFFF 16 KB Reserved Small HSM Code Block 0x00F8C000 0x00F8FFFF 16 KB Code Flash block 0 available available Table 5. MPC5746C Family Comparison - RAM Memory Map Start Address End Address Allocated size Description MPC5744 MPC5745 MPC5746 0x40000000 0x40001FFF 8 KB SRAM0 available available available 0x40002000 0x4000FFFF 56 KB SRAM1 available available available 0x40010000 0x4001FFFF 64 KB SRAM2 available available available 0x40020000 0x4002FFFF 64 KB SRAM3 available available available 0x40030000 0x4003FFFF 64 KB SRAM4 not available available available 0x40040000 0x4004FFFF 64 KB SRAM5 not available not available available 0x40050000 0x4005FFFF 64 KB SRAM6 not available not available available 0x40060000 0x4006FFFF 64 KB SRAM7 not available not available optional 0x40070000 0x4007FFFF 64 KB SRAM8 not available not available optional 3 Ordering parts 3.1 Determining valid orderable parts To determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search for the following device number: MPC5746C. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 8 NXP Semiconductors General 3.2 Ordering Information P Example Code PC 57 4 6 C S K0 M MJ 6 R Qualification Status Power Architecture Automotive Platform Core Version Flash Size (core dependent) Product Optional fields Fab and mask indicator Temperature spec. Package Code CPU Frequency R = Tape & Reel (blank if Tray) Product Version B = Single core C = Dual core Qualification Status P = Engineering samples S = Automotive qualified PC = Power Architecture Automotive Platform 57 = Power Architecture in 55nm Core Version 4 = e200z4 Core Version (highest core version in the case of multiple cores) Flash Memory Size 4 = 1.5 MB 5 = 2 MB 6 = 3 MB Optional fields Blank = No optional feature S = HSM (Security Module) Fab and mask version indicator K = TSMC Fab #(0,1,etc.) = Version of the maskset, like rev. 0=0N65H Package Code KU = 176 LQFP EP MJ = 256 MAPBGA MN M = 324 MAPBGA MH = 100MAPBGA Temperature spec. C = -40.C to +85.C Ta V = -40.C to +105.C Ta M = -40.C to +125.C Ta CPU Frequency F = CAN FD B = HSM + CAN FD R = 512K RAM T = HSM + 512K RAM G* = CAN FD + 512K RAM H* = HSM + CAN FD + 512K RAM * G and H for 5746 B/C only 2 = Z4 operates upto 120 MHz 6 = Z4 operates upto 160 MHz Shipping Method R = Tape and reel Blank = Tray Note: Not all part number combinations are available as production product 4 General 4.1 Absolute maximum ratings NOTE Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in Table 6 for specific conditions MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 9 General Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. Table 6. Absolute maximum ratings Symbol Conditions1 Min Max Unit 3.3 V - 5. 5V input/output supply voltage — –0.3 6.0 V 3.3 V flash supply voltage (when supplying from an external source in bypass mode) — –0.3 3.63 V Decoupling pin for low power regulators7 — –0.3 1.32 V 3.3 V / 5.0 V ADC1 high reference voltage — –0.3 6 V 3.3 V to 5.5V ADC supply voltage — –0.3 6.0 V 3.3V to 5.5V ADC supply ground — –0.1 0.1 V Parameter VDD_HV_A, VDD_HV_B, VDD_HV_C2, 3 VDD_HV_FLA4, 5 VDD_LP_DEC6 8 VDD_HV_ADC1_REF VDD_HV_ADC0 VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV9, 10, 11, 12 Core logic supply voltage — –0.3 1.32 V VINA Voltage on analog pin with respect to ground (VSS_HV) — –0.3 Min (VDD_HV_x, VDD_HV_ADCx, VDD_ADCx_REF) +0.3 V VIN Voltage on any digital pin with respect to ground (VSS_HV) Relative to VDD_HV_A, VDD_HV_B, VDD_HV_C –0.3 VDD_HV_x + 0.3 V Always –5 5 mA IINJPAD Injected input current on any pin during overload condition IINJSUM Absolute sum of all injected input currents during overload condition — –50 50 mA Tramp Supply ramp rate — 0.5 V / min 100V/ms — TA13 Ambient temperature — -40 125 °C TSTG Storage temperature — –55 165 °C 1. All voltages are referred to VSS_HV unless otherwise specified 2. VDD_HV_B and VDD_HV_C are common together on the 176 LQFP-EP package. 3. Allowed VDD_HV_x = 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ= 150 °C, remaining time at or below 5.5 V. 4. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V 5. VDD_HV_FLA must be disconnected from ANY power sources when VDD_HV_A = 5V 6. This pin should be decoupled with low ESR 1 µF capacitor. 7. Not available for input voltage, only for decoupling internal regulators 8. 10-bit ADC does not have dedicated reference and its reference is bonded to 10-bit ADC supply(VDD_HV_ADC0) inside the package. 9. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ = 150 °C, remaining time as defined in footnotes 10 and 11. 10. Allowed 1.38 – 1.45 V– for 10 hours cumulative time at maximum TJ = 150 °C, remaining time as defined in footnote 11. 11. 1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at maximum TJ = 150 °C. 12. If HVD on core supply (VHVD_LV_x) is enabled, it will generate a reset when supply goes above threshold. 13. TJ=150°C. Assumes TA=125°C • Assumes maximum θJA for 2s2p board. See Thermal attributes MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 10 NXP Semiconductors General 4.2 Recommended operating conditions The following table describes the operating conditions for the device, and for which all specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded in order to guarantee proper operation and reliability. The ranges in this table are design targets and actual data may vary in the given range. NOTE • For normal device operations, all supplies must be within operating range corresponding to the range mentioned in following tables. This is required even if some of the features are not used. • If VDD_HV_A is in 5.0V range, VDD_HV_FLA should be externally supplied using a 3.3V source. If VDD_HV_A is in 3.3V range, VDD_HV_FLA should be shorted to VDD_HV_A. • VDD_HV_A, VDD_HV_B and VDD_HV_C are all independent supplies and can each be set to 3.3V or 5V. The following tables: 'Recommended operating conditions (VDD_HV_x = 3.3 V)' and table 'Recommended operating conditions (VDD_HV_x = 5 V)' specify their ranges when configured in 3.3V or 5V respectively. Table 7. Recommended operating conditions (VDD_HV_x = 3.3 V) Symbol VDD_HV_A Conditions1 Min2 Max Unit HV IO supply voltage — 3.15 3.6 V HV flash supply voltage — 3.15 3.6 V HV ADC1 high reference voltage — 3.0 5.5 V HV ADC supply voltage — max(VDD_H V_A,VDD_H V_B,VDD_H V_C) - 0.05 3.6 V HV ADC supply ground — -0.1 0.1 V Core supply voltage — 1.2 1.32 V Analog Comparator DAC reference voltage — 3.15 3.6 V Injected input current on any pin during overload condition — -3.0 3.0 mA Parameter VDD_HV_B VDD_HV_C VDD_HV_FLA3 VDD_HV_ADC1_REF VDD_HV_ADC0 VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV4, 5 VIN1_CMP_REF6, 7 IINJPAD Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 11 General Table 7. Recommended operating conditions (VDD_HV_x = 3.3 V) (continued) Symbol Parameter Conditions1 Min2 Max Unit TA8 Ambient temperature under bias fCPU ≤ 160 MHz –40 125 °C TJ Junction temperature under bias — –40 150 °C 1. All voltages are referred to VSS_HV unless otherwise specified 2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset. 3. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V 4. Only applicable when supplying from external source. 5. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be left floating. 6. VIN1_CMP_REF ≤ VDD_HV_A 7. This supply is shorted VDD_HV_A on lower packages. 8. TJ=150°C. Assumes TA=125°C • Assumes maximum θJA of 2s2p board. See Thermal attributes NOTE If VDD_HV_A is in 5V range, it is necessary to use internal Flash supply 3.3V regulator. VDD_HV_FLA should not be supplied externally and should only have decoupling capacitor. Table 8. Recommended operating conditions (VDD_HV_x = 5 V) Symbol Conditions 1 Min2 Max Unit HV IO supply voltage — 4.5 5.5 V HV flash supply voltage — 3.15 3.6 V HV ADC1 high reference voltage — 3.15 5.5 V HV ADC supply voltage — max(VDD_H V_A,VDD_H V_B,VDD_H V_C) - 0.05 5.5 V HV ADC supply ground — -0.1 0.1 V Core supply voltage — 1.2 1.32 V V Parameter VDD_HV_A VDD_HV_B VDD_HV_C VDD_HV_FLA3 VDD_HV_ADC1_REF VDD_HV_ADC0 VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV4 6 VIN1_CMP_REF IINJPAD Analog Comparator DAC reference voltage — 3.15 5.55 Injected input current on any pin during overload condition — -3.0 3.0 mA TA7 Ambient temperature under bias fCPU ≤ 160 MHz –40 125 °C TJ Junction temperature under bias — –40 150 °C 1. All voltages are referred to VSS_HV unless otherwise specified 2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset. 3. When VDD_HV is in 5 V range, VDD_HV_FLA cannot be supplied externally.This pin is decoupled with Cflash_reg. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 12 NXP Semiconductors General 4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be left floating 5. VIN1_CMP_REF ≤ VDD_HV_A 6. This supply is shorted VDD_HV_A on lower packages. 7. TJ=150°C. Assumes TA=125°C • Assumes maximum θJA of 2s2p board. See Thermal attributes 4.3 Voltage regulator electrical characteristics The voltage regulator is composed of the following blocks: • Choice of generating supply voltage for the core area. • Control of external NPN ballast transistor • Generating core supply using internal ballast transistor • Connecting an external 1.25 V (nominal) supply directly without the NPN ballast • Internal generation of the 3.3 V flash supply when device connected in 5V applications • External bypass of the 3.3 V flash regulator when device connected in 3.3V applications • Low voltage detector - low threshold (LVD_IO_A_LO) for VDD_HV_IO_A supply • Low voltage detector - high threshold (LVD_IO_A_Hi) for VDD_HV_IO_A supply • Low voltage detector (LVD_FLASH) for 3.3 V flash supply (VDD_HV_FLA) • Various low voltage detectors (LVD_LV_x) • High voltage detector (HVD_LV_cold) for 1.2 V digital core supply (VDD_LV) • Power on Reset (POR_LV) for 1.25 V digital core supply (VDD_LV) • Power on Reset (POR_HV) for 3.3 V to 5 V supply (VDD_HV_A) The following bipolar transistors1 are supported, depending on the device performance requirements. As a minimum the following must be considered when determining the most appropriate solution to maintain the device under its maximum power dissipation capability: current, ambient temperature, mounting pad area, duty cycle and frequency for Idd, collector voltage, etc 1. BCP56, MCP68 and MJD31are guaranteed ballasts. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 13 General LPPREG VDD_LP_DEC VDD_HV_BALLAST ULPPREG CLP/ULPREG VRC_CTRL V SS_HV FPREG CBE_FPREG Flash voltage regulator V DD_LV VDD_HV_FLA CFLASH_REG CFP_REG VSS_HV VSS_HV DEVICE Figure 2. Voltage regulator capacitance connection NOTE On BGA, VSS_LV and VSS_HV have been joined on substrate and renamed as VSS. Table 9. Voltage regulator electrical specifications Symbol Cfp_reg 1 Clp/ulp_reg Cbe_fpreg3 Parameter Conditions Min Typ Max Unit 1.32 2.22 3 µF — 0.03 Ohm 1 1.4 µF — 0.1 Ohm External decoupling / stability capacitor Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. Combined ESR of external capacitor — External decoupling / stability capacitor for internal low power regulators Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. Combined ESR of external capacitor — Capacitor in parallel to baseemitter BCP68 and BCP56 3.3 MJD31 4.7 0.001 0.8 0.001 nF Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 14 NXP Semiconductors General Table 9. Voltage regulator electrical specifications (continued) Symbol Conditions Min Typ Max Unit External decoupling / stability capacitor for internal Flash regulators Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1.32 2.2 3 µF Combined ESR of external capacitor — 0.001 — 0.03 Ohm CHV_VDD_A VDD_HV_A supply capacitor 5 Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 — — µF CHV_VDD_B VDD_HV_B supply capacitor5 Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 — — µF CHV_VDD_C VDD_HV_C supply capacitor5 Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 — — µF CHV_ADC0 HV ADC supply decoupling capacitances Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 — — µF HV ADC SAR reference supply decoupling capacitances Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 0.47 — — µF VDD_HV_BALL FPREG Ballast collector supply 7 voltage AST When collector of NPN ballast is directly supplied by an on board supply source (not shared with VDD_HV_A supply pin) without any series resistance, that is, RC_BALLAST less than 0.01 Ohm. 2.25 — 5.5 V RC_BALLAST Series resistor on collector of FPREG ballast When VDD_HV_BALLAST is shorted to VDD_HV_A on the board — — 0.1 Ohm Start-up time with external ballastafter main supply (VDD_HV_A) stabilization Cfp_reg = 3 μF — 74 — μs tSU_int Start-up time with internal ballast after main supply (VDD_HV_A) stabilization Cfp_reg = 3 μF — 103 — μs tramp Load current transient Iload from 15% to 55% Cflash_reg4 CHV_ADC1 CHV_ADR6 tSU Parameter 1.0 µs Cfp_reg = 3 µF 1. Split capacitance on each pair VDD_LV pin should sum up to a total value of Cfp_reg 2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and maximum values. 3. Ceramic X7R or X5R type with capacitance-temperature characteristics +/-15% of -55 degC to +125degC is recommended. The tolerance +/-20% is acceptable. 4. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD_HV_FLA pin and the routing inductance should be less than 1nH. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 15 General 5. 1. For VDD_HV_x, 1µf on each side of the chip a. 0.1 µf close to each VDD/VSS pin pair. b. 10 µf near for each power supply source c. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as specified by CFP_REG parameter. 2. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as specified by CFP_REG parameter 6. Only applicable to ADC1 7. In external ballast configuration the following must be ensured during power-up and power-down (Note: If VDD_HV_BALLAST is supplied from the same source as VDD_HV_A this condition is implicitly met): • During power-up, VDD_HV_BALLAST must have met the min spec of 2.25V before VDD_HV_A reaches the POR_HV_RISE min of 2.75V. • During power-down, VDD_HV_BALLAST must not drop below the min spec of 2.25V until VDD_HV_A is below POR_HV_FALL min of 2.7V. NOTE For a typical configuration using an external ballast transistor with separate supply for VDD_HV_A and the ballast collector, a bulk storage capacitor (as defined in Table 9) is required on VDD_HV_A close to the device pins to ensure a stable supply voltage. Extra care must be taken if the VDD_HV_A supply is also being used to power the external ballast transistor or the device is running in internal regulation mode. In these modes, the inrush current on device Power Up or on exit from Low Power Modes is significant and may cause the VDD_HV_A voltage to drop resulting in an LVD reset event. To avoid this, the board layout should be optimized to reduce common trace resistance or additional capacitance at the ballast transistor collector (or VDD_HV_A pins in the case of internal regulation mode) is required. NXP recommends that customers simulate the external voltage supply circuitry. In all circumstances, the voltage on VDD_HV_A must be maintained within the specified operating range (see Recommended operating conditions) to prevent LVD events. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 16 NXP Semiconductors General 4.4 Voltage monitor electrical characteristics Table 10. Voltage monitor electrical characteristics Symbol Parameter State Conditions Configuration Power Up 1 VPOR_LV LV supply power on reset detector Fall Rise VHVD_LV_col LV supply high voltage d monitoring, detecting at device pin Fall VLVD_LV_PD LV supply low voltage 2_hot monitoring, detecting on the PD2 core (hot) area Fall VLVD_LV_PD LV supply low voltage 1_hot (BGFP) monitoring, detecting on the PD1 core (hot) area Fall VLVD_LV_PD LV supply low voltage 0_hot (BGFP) monitoring, detecting on the PD0 core (hot) area Fall VPOR_HV Fall HV supply power on reset detector Rise Rise Rise Rise VLVD_IO_A_H HV IO_A supply 3 low voltage I monitoring - high range Fall Rise Fall Rise Typ Max V 1.028 V Trimmed - - - V Untrimmed 0.980 1.029 1.078 V Trimmed - - - V 1.375 V Yes POR Min 0.979 No No Reset Type Unit 0.930 Untrimmed Yes Trimmed Rise VLVD_IO_A_L HV IO_A supply ,3 low voltage O monitoring - low range Untrimmed Mask Opt2 Threshold Function Disabled at Start al 1.325 1.345 Untrimmed Disabled at Start Trimmed 1.345 1.365 1.395 V 1.0800 1.1200 1.1600 V Trimmed 1.1250 1.1425 1.1600 V Untrimmed 1.1000 1.1400 1.1800 V Trimmed 1.1450 1.1625 1.1800 V 1.0800 1.1200 1.1600 V Trimmed 1.1140 1.1370 1.1600 V Untrimmed 1.1000 1.140 1.1800 V Trimmed 1.1340 1.1570 1.1800 V Untrimmed Untrimmed Untrimmed Yes Yes No POR 1.0800 1.1200 1.1600 V 1.1140 1.1370 1.1600 V Untrimmed 1.1000 1.1400 1.1800 V Trimmed 1.1340 1.1570 1.1800 V 2.7000 2.8500 3.0000 V Trimmed - - - V Untrimmed 2.7500 2.9000 3.0500 V Trimmed - - - V 2.7500 2.9230 3.0950 V Trimmed 2.9780 3.0390 3.1000 V Untrimmed 2.7800 2.9530 3.1250 V Trimmed 3.0080 3.0690 3.1300 V Function Disabled at Start al 4.0600 4.151 4.2400 V 4.3000 V Untrimmed Trimmed Yes Yes No No POR Trimmed Untrimmed Yes No No No Yes POR POR POR Trimmed Disabled at Start 4.1150 4.2010 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 17 General Table 10. Voltage monitor electrical characteristics (continued) Symbol Parameter State Conditions Configuration Power Up 1 VLVD_LV_PD LV supply low voltage 2_cold monitoring, detecting at the device pin Fall Untrimmed No Mask Opt2 Yes Trimmed Rise Threshold Reset Type Min Unit Typ Max Function Disabled at Start al 1.1400 1.1550 1.1750 V 1.1950 V Untrimmed Disabled at Start Trimmed 1.1600 1.1750 V 1. All monitors that are active at power-up will gate the power up recovery and prevent exit from POWERUP phase until the minimum level is crossed. These monitors can in some cases be masked during normal device operation, but when active will always generate a POR reset. 2. Voltage monitors marked as non maskable are essential for device operation and hence cannot be masked. 3. There is no voltage monitoring on the VDD_HV_ADC0, VDD_HV_ADC1, VDD_HV_B and VDD_HV_C I/O segments. For applications requiring monitoring of these segments, either connect these to VDD_HV_A at the PCB level or monitor externally. 4.5 Supply current characteristics Current consumption data is given in the following table. These specifications are design targets and are subject to change per device characterization. NOTE The ballast must be chosen in accordance with the ballast transistor supplier operating conditions and recommendations. Table 11. Current consumption characteristics Symbol IDD_BODY_1 2, 3 Parameter RUN Body Mode Profile Operating current Conditions1 LV supply + HV supply + HV Flash supply + Min Typ Max Unit — — 147 mA 2 x HV ADC supplies4 Ta = 125°C , 5 VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 80MHz IDD_BODY_2 6 RUN Body Mode Profile Operating current Ta = 105°C — — 142 mA Ta = 85 °C — — 137 mA 246 mA LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies4 — — Ta = 125°C5 VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 160MHz Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 18 NXP Semiconductors General Table 11. Current consumption characteristics (continued) Symbol Conditions1 Parameter IDD_BODY_3 7 RUN Body Mode Profile Operating current Min Typ Max Unit Ta = 105°C — — 235 mA Ta = 85°C — — 210 mA 181 mA LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies4 — — Ta = 125 °C 5 VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 120MHz IDD_BODY_4 8 RUN Body Mode Profile Operating current Ta = 105 °C — — 176 mA Ta = 85°C — — 171 mA 264 mA LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies4 — — Ta = 125 °C 5 VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 120MHz IDD_STOP STOP mode Operating current Ta = 105 °C — — 176 mA Ta = 85 °C — — 171 mA — 49 mA — 10.6 — — 8.1 — — 4.6 — Ta = 125 °C9 — VDD_LV = 1.25 V Ta = 105 °C VDD_LV = 1.25 V Ta = 85 °C VDD_LV = 1.25 V Ta = 25 °C VDD_LV = 1.25 V IDD_HV_ADC_REF 10, 11 ADC REF Operating current Ta = 125 °C5 — 200 400 µA 2 ADCs operating at 80 MHz VDD_HV_ADC_REF = 5.5 V Ta = 105 °C — 200 — — 200 — — 200 — 2 ADCs operating at 80 MHz VDD_HV_ADC_REF = 5.5 V Ta = 85 °C 2 ADCs operating at 80 MHz VDD_HV_ADC_REF = 5.5 V Ta = 25 °C 2 ADCs operating at 80 MHz Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 19 General Table 11. Current consumption characteristics (continued) Symbol Parameter Conditions1 Min Typ Max Unit — 1.2 2 mA VDD_HV_ADC_REF = 3.6 V 11 IDD_HV_ADCx ADC HV Operating current Ta = 125 °C5 ADC operating at 80 MHz VDD_HV_ADC = 5.5 V Ta = 25 °C — 1 2 ADC operating at 80 MHz VDD_HV_ADC = 3.6 V IDD_HV_FLASH12 Flash Operating current during read access Ta = 125 °C5 — 40 45 mA 3.3 V supplies 160 MHz frequency Ta = 105 °C — 40 45 — 40 45 3.3 V supplies 160 MHz frequency Ta = 85 °C 3.3 V supplies 160 MHz frequency 1. The content of the Conditions column identifies the components that draw the specific current. 2. Single e200Z4 core cache disabled @80 MHz, no FlexRay, no ENET, 2 x CAN, 8 LINFlexD, 2 SPI, ADC0 and 1 used constantly, no HSM, Memory: 2M flash, 128K RAM RUN mode, Clocks: FIRC on, XOSC, PLL on, SIRC on for TOD, no 32KHz crystal (TOD runs off SIRC). 3. Recommended Transistors:MJD31 @ 85°C, 105°C and 125°C. In case of internal ballast mode, it is expected that the external ballast is not mounted and BAL_SELECT_INT pin is tied to VDD_HV_A supply on board. Internal ballast can be used for all use cases with current consumption upto 150mA. For internal ballast configuration the VRC_CTL pin should be left floating. 4. The power consumption does not consider the dynamic current of I/Os 5. Tj=150°C. Assumes Ta=125°C • Assumes maximum θJA of 2s2p board. SeeThermal attributes 6. e200Z4 core, 160MHz, cache enabled; e200Z2 core , 80MHz, no FlexRay, no ENET, 7 CAN, 16 LINFlexD, 4 SPI, 1x ADC used constantly, includes HSM at start-up / periodic use, Memory: 3M flash, 256K RAM, Clocks: FIRC on, XOSC on, PLL on, SIRC on, no 32KHz crystal 7. e200Z4 core, 120MHz, cache enabled; e200Z2 core, 60MHz; no FlexRay, no ENET, 7 CAN, 16 LINFlexD, 4 SPI, 1x ADC used constantly, includes HSM at start-up / periodic use, Memory: 3M flash, 128K RAM, Clocks: FIRC on, XOSC on, PLL on, SIRC on, no 32KHz crystal 8. e200Z4 core, 160MHz, cache enabled; e200Z4 core, 80MHz; HSM fully operational (Z0 core @80MHz) FlexRay, 5x CAN, 5x LINFlexD, 2x SPI, 1x ADC used constantly, 1xeMIOS (5 ch), Memory: 3M flash, 384K RAM, Clocks: FIRC on, XOSC on, PLL on, SIRC on, no 32KHz crystal 9. Assuming Ta=Tj, as the device is in Stop mode. Assumes maximum θJA of 2s2p board. SeeThermal attributes. 10. Internal structures hold the input voltage less than VDD_HV_ADC_REF + 1.0 V on all pads powered by VDDA supplies, if the maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications. 11. This value is the total current for two ADCs.Each ADC might consume upto 2mA at max. 12. This assumes the default configuration of flash controller register. For more details, refer to Flash memory program and erase specifications MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 20 NXP Semiconductors General Table 12. Low Power Unit (LPU) Current consumption characteristics Symbol LPU_RUN Conditions1 Parameter with 256K RAM Ta = 25 °C Min Typ Max Unit — 10 — mA — 10.5 — — 11 — — — 26 SYS_CLK = 16MHz ADC0 = OFF, SPI0 = OFF, LIN0 = OFF, CAN0 = OFF Ta = 85 °C SYS_CLK = 16MHz ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON Ta = 105 °C SYS_CLK = 16MHz ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON Ta = 125 °C, 2 SYS_CLK = 16MHz ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON LPU_STOP with 256K RAM Ta = 25 °C — 0.18 Ta = 85 °C — 0.60 Ta = 105 °C — 1.00 Ta = 125 °C 2 — — — mA — — 10.6 1. The content of the Conditions column identifies the components that draw the specific current. 2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum θJA of 2s2p board. SeeThermal attributes Table 13. STANDBY Current consumption characteristics Symbol STANDBY0 Conditions1 Parameter STANDBY with 8K RAM Ta = 25 °C Ta = 85 °C Ta = 105 °C Ta = 125 °C STANDBY1 STANDBY2 STANDBY with 64K RAM STANDBY with 128K RAM ,2 Ta = 25 °C STANDBY3 FIRC ON Max Unit — 71 — µA — 125 700 — 195 1225 — 314 2100 72 — Ta = 85 °C — 140 715 Ta = 105 °C — 225 1275 Ta = 125 °C 2 — 358 2250 Ta = 25 °C — Ta = 85 °C Ta = 125 °C STANDBY with 256K RAM Typ — Ta = 105 °C STANDBY3 Min 2 Ta = 25 °C 75 — — 155 730 — 255 1350 — 396 2600 — 80 — Ta = 85 °C — 180 800 Ta = 105 °C — 290 1425 Ta = 125 °C 2 — 465 2900 Ta = 25 °C — 500 — µA µA µA µA MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 21 General 1. The content of the Conditions column identifies the components that draw the specific current. 2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum θJA of 2s2p board. SeeThermal attributes NOTE For the Precision channel Analog inputs, SIUL2_MSCRn[PUS] must be configured to 0 before entering STANDBY. An increase in current would be observed when SIUL2_MSCRn[PUS] is configured to be 1, irrespective of the state of IBE or PUE. The current numbers would increase irrespective of whether the pad is pulled low/high externally. 4.6 Electrostatic discharge (ESD) characteristics Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. NOTE A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 14. ESD ratings Symbol VESD(HBM) VESD(CDM) Parameter Conditions1 Electrostatic discharge TA = 25 °C (Human Body Model) conforming to AECQ100-002 Electrostatic discharge TA = 25 °C (Charged Device Model) conforming to AECQ100-011 Class Max value2 Unit H1C 2000 V C3A 500 V 750 (corners) 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. Data based on characterization results, not tested in production. 4.7 Electromagnetic Compatibility (EMC) specifications EMC measurements to IC-level IEC standards are available from NXP on request. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 22 NXP Semiconductors I/O parameters 5 I/O parameters 5.1 AC specifications @ 3.3 V Range Table 15. Functional Pad AC Specifications @ 3.3 V Range Prop. Delay (ns)1 Symbol Rise/Fall Edge (ns) L>H/H>L Min Max 1.9/1.5 25 2.5/2.5 8.25/7.5 0.8/0.6 3.25/3 50 6.4/5 19.5/19.5 3.5/2.5 12/12 200 2.2/2.5 8/8 0.55/0.5 3.9/3.5 25 pad_sr_hv Min 6/6 (output) pad_i_hv/ pad_sr_hv Drive Load (pF) Max MSB,LSB 0.090 1.1 0.035 1.1 asymmetry2 2.9/3.5 12.5/11 1/1 7/6 50 11/8 35/31 7.7/5 25/21 200 8.3/9.6 45/45 4/3.5 25/25 50 13.5/15 65/65 6.3/6.2 30/30 200 13/13 75/75 6.8/6 40/40 50 21/22 100/100 11/11 51/51 200 0.5/0.5 0.5 2/2 SIUL2_MSCRn[SRC 1:0] 11 10 01 003 NA (input)4 1. As measured from 50% of core side input to Voh/Vol of the output 2. This row specifies the min and max asymmetry between both the prop delay and the edge rates for a given PVT and 25pF load. Required for the Flexray spec. 3. Slew rate control modes 4. Input slope = 2ns NOTE The specification given above is based on simulation data into an ideal lumped capacitor. Customer should use IBIS models for their specific board/loading conditions to simulate the expected signal integrity and edge rates of their system. NOTE The specification given above is measured between 20% / 80%. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 23 I/O parameters 5.2 DC electrical specifications @ 3.3V Range Table 16. DC electrical specifications @ 3.3V Range Symbol Parameter Value Unit Min Max Vih (pad_i_hv) Pad_I_HV Input Buffer High Voltage 0.72*VDD_HV_ x VDD_HV_x + 0.3 V Vil (pad_i_hv) Pad_I_HV Input Buffer Low Voltage VDD_HV_x 0.3 0.45*VDD_HV_ x V Vhys (pad_i_hv) Pad_I_HV Input Buffer Hysteresis 0.11*VDD_HV_ x Vih_hys CMOS Input Buffer High Voltage (with hysteresis enabled) 0.67*VDD_HV_ x VDD_HV_x + 0.3 V Vil_hys CMOS Input Buffer Low Voltage (with hysteresis enabled) VDD_HV_x 0.3 0.35*VDD_HV_ x V Vih CMOS Input Buffer High Voltage (with hysteresis disabled) 0.57 * VDD_HV_x1 VDD_HV_x1 + 0.3 V Vil CMOS Input Buffer Low Voltage (with hysteresis disabled) VDD_HV_x 0.3 0.4 * VDD_HV_x1 V CMOS Input Buffer Hysteresis 0.09 * VDD_HV_x1 V 15 µA Vhys Pull_IIH (pad_i_hv) Weak Pullup Current2 Low Current3 Pull_IIH (pad_i_hv) Weak Pullup High 55 Pull_IIL (pad_i_hv) Weak Pulldown Current3 Low 28 Pull_IIL (pad_i_hv) Weak Pulldown Current2 High Pull_Ioh Weak Pulldown Iinact_d Digital Pad Input Leakage Current (weak pull inactive) Voltage6 Voh Output High Vol Output Low Voltage7 µA µA 15 50 µA 15 50 µA -2.5 2.5 µA 0.8 *VDD_HV_x1 — V — 0.2 *VDD_HV_x1 V Current5 Pull_Iol µA 85 Current4 Weak Pullup V Output Low Voltage8 0.1 *VDD_HV_x Ioh_f Iol_f Ioh_h Iol_h 1. 2. 3. 4. 5. 6. 7. 8. 9. Full drive Ioh9 Full drive Iol9 Half drive Ioh9 Half drive Iol9 (SIUL2_MSCRn.SRC[1:0] = 11) 18 70 mA 21 120 mA 9 35 mA 10.5 60 mA (SIUL2_MSCRn.SRC[1:0] = 11) (SIUL2_MSCRn.SRC[1:0] = 10) (SIUL2_MSCRn.SRC[1:0] = 10) VDD_HV_x = VDD_HV_A, VDD_HV_B, VDD_HV_C Measured when pad=0.69*VDD_HV_x Measured when pad=0.49*VDD_HV_x Measured when pad = 0 V Measured when pad = VDD_HV_x Measured when pad is sourcing 2 mA Measured when pad is sinking 2 mA Measured when pad is sinking 1.5 mA Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 24 NXP Semiconductors I/O parameters 5.3 AC specifications @ 5 V Range Table 17. Functional Pad AC Specifications @ 5 V Range Prop. Delay (ns)1 Symbol Rise/Fall Edge (ns) Drive Load (pF) SIUL2_MSCRn[SRC 1:0] L>H/H>L Min pad_sr_hv (output) pad_i_hv/ pad_sr_hv Max Min Max MSB,LSB 4.5/4.5 1.3/1.2 25 6/6 2.5/2 50 13/13 9/9 200 5.25/5.25 3/2 25 9/8 5/4 50 22/22 18/16 200 27/27 13/13 50 40/40 24/24 200 40/40 24/24 50 65/65 40/40 200 1.5/1.5 0.5/0.5 0.5 11 10 012 002 NA (input) 1. As measured from 50% of core side input to Voh/Vol of the output 2. Slew rate control modes NOTE The above specification is based on simulation data into an ideal lumped capacitor. Customer should use IBIS models for their specific board/loading conditions to simulate the expected signal integrity and edge rates of their system. NOTE The above specification is measured between 20% / 80%. 5.4 DC electrical specifications @ 5 V Range Table 18. DC electrical specifications @ 5 V Range Symbol Vih (pad_i_hv) Parameter pad_i_hv Input Buffer High Voltage Value Unit Min Max 0.7*VDD_HV_x VDD_HV_x + 0.3 V Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 25 I/O parameters Table 18. DC electrical specifications @ 5 V Range (continued) Symbol Vil (pad_i_hv) Vhys (pad_i_hv) Parameter pad_i_hv Input Buffer Low Voltage pad_i_hv Input Buffer Hysteresis Value Min Max VDD_HV_x 0.3 0.45*VDD_HV_ x 0.09*VDD_HV_ x V V Vih_hys CMOS Input Buffer High Voltage (with hysteresis enabled) 0.65* VDD_HV_x VDD_HV_x + 0.3 V Vil_hys CMOS Input Buffer Low Voltage (with hysteresis enabled) VDD_HV_x 0.3 0.35*VDD_HV_ x V Vih CMOS Input Buffer High Voltage (with hysteresis disabled) 0.55 * VDD_HV_x1 VDD_HV_x1 + 0.3 V Vil CMOS Input Buffer Low Voltage (with hysteresis disabled) VDD_HV_x 0.3 0.40 * VDD_HV_x1 V CMOS Input Buffer Hysteresis 0.09 * VDD_HV_x1 V 23 µA Vhys Pull_IIH (pad_i_hv) Weak Pullup Current2 Low Current3 Pull_IIH (pad_i_hv) Weak Pullup High Pull_IIL (pad_i_hv) Weak Pulldown Current3 Low Pull_IIL (pad_i_hv) Weak Pulldown Current2 High 82 40 µA µA 130 µA Pull_Ioh Weak Pullup Current4 30 80 µA Pull_Iol Weak Pulldown Current5 30 80 µA Iinact_d Digital Pad Input Leakage Current (weak pull inactive) -2.5 2.5 µA 0.8 * VDD_HV_x1 — V — 0.2*VDD_HV_x V Voltage6 Voh Output High Vol Output Low Voltage7 Output Low Ioh_f Iol_f 1. 2. 3. 4. 5. 6. 7. 8. 9. Unit Voltage8 Full drive Ioh9 Full drive Iol9 0.1*VDD_HV_x (SIUL2_MSCRn.SRC[1:0] = 11) (SIUL2_MSCRn.SRC[1:0] = 11) 18 70 mA 21 120 mA Ioh_h Half drive Ioh9 (SIUL2_MSCRn.SRC[1:0] = 10) 9 35 mA Iol_h Half drive Iol9 (SIUL2_MSCRn.SRC[1:0] = 10) 10.5 60 mA VDD_HV_x = VDD_HV_A, VDD_HV_B, VDD_HV_C Measured when pad=0.69*VDD_HV_x Measured when pad=0.49*VDD_HV_x Measured when pad = 0 V Measured when pad = VDD_HV_x Measured when pad is sourcing 2 mA Measured when pad is sinking 2 mA Measured when pad is sinking 1.5 mA Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test. 5.5 Reset pad electrical characteristics The device implements a dedicated bidirectional RESET pin. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 26 NXP Semiconductors I/O parameters AA A VDD_HV_IOx A VDDMIN PORST VIH VIL device reset forced by PORST device start-up phase Figure 3. Start-up reset requirements VPORST hw_rst VDD_HV_IO A ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter filtered by lowpass filter unknown reset state device under hardware reset WFRST WFRST WNFRST Figure 4. Noise filtering on reset signal Table 19. Functional reset pad electrical specifications Symbol Parameter Conditions Value Min VIH CMOS Input Buffer High Voltage — VIL CMOS Input Buffer Low Voltage — Typ 0.65*VD — Unit Max D_HV_x VDD_HV_x +0.3 VDD_HV_ — x-0.3 _x V 0.35*VDD_HV V Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 27 Peripheral operating requirements and behaviours Table 19. Functional reset pad electrical specifications (continued) Symbol Parameter Conditions Value Min Unit Typ Max VHYS CMOS Input Buffer hysterisis — 300 — — mV VDD_POR Minimum supply for strong pull-down activation — — — 1.2 V IOL_R Strong pull-down current 1 Device under power-on reset 0.2 — — mA 11 — — mA VDD_HV_IO= V DD_POR VOL = 0.35*VDD_HV_IO Device under power-on reset 3.0 V < VDD_HV_IO < 5.5 V VOL = 0.35*VDD_HV_IO WFRST RESET input filtered pulse — — — 500 ns WNFRST RESET input not filtered pulse — 2000 — — ns |IWPU| Weak pull-up current absolute value RESET pin VIN = VDD 23 — 82 µA 1. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for RESET. 5.6 PORST electrical specifications Table 20. PORST electrical specifications Symbol Parameter Value Min WFPORST PORST input filtered pulse WNFPORST PORST input not filtered pulse VIH VIL Unit Typ Max — — 200 ns 1000 — — ns Input high level 0.65 x VDD_HV_A — — V Input low level — — 0.35 x V VDD_HV_A 6 Peripheral operating requirements and behaviours 6.1 Analog 6.1.1 ADC electrical specifications The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 28 NXP Semiconductors Analog Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) 1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3V/ 4096 = 0.806 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 4.84mV code out 7 ( 1) 6 5 (5) 4 (4) 3 (3) 2 1 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 1 LSB (ideal) 0 1 2 3 Offset Error OSE 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Figure 5. ADC characteristics and error definitions MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 29 Analog 6.1.1.1 Input equivalent circuit and ADC conversion characteristics EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD_IO Source Filter RS Current Limiter RF Sampling RSW1 RAD RL CF VA Channel Selection CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 6. Input equivalent circuit NOTE The ADC performance specifications are not guaranteed if two ADCs simultaneously sample the same shared channel. Table 21. ADC conversion characteristics (for 12-bit) Min Typ1 Max Unit 15.2 80 80 MHz — — 1.00 MHz 80 MHz@ 100 ohm source impedance 250 — — ns Conversion time4 80 MHz 700 — — ns Total Conversion time tsample + tconv (for standard and extended channels) 80 MHz 1.55 — — µs 1 — — Symbol fCK fs Parameter Conditions ADC Clock frequency (depends on — ADC configuration) (The duty cycle depends on AD_CK2 frequency) Sampling frequency tsample tconv ttotal_conv Sample 80 MHz time3 Total Conversion time tsample + tconv (for precision channels) CS, 6 ADC input sampling capacitance — — 3 5 pF 6 ADC input pin capacitance 1 — — — 5 pF CP2 6 ADC input pin capacitance 2 — — — 0.8 pF RSW16 Internal resistance of analog source VREF range = 4.5 to 5.5 V — — 0.3 kΩ VREF range = 3.15 to 3.6 V — — 875 Ω CP1 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 30 NXP Semiconductors Analog Table 21. ADC conversion characteristics (for 12-bit) (continued) Symbol Parameter Conditions Min Typ1 Max Unit RAD6 Internal resistance of analog source — — — 825 Ω INL Integral non-linearity (precise channel) — –2 — 2 LSB INL Integral non-linearity (standard channel) — –3 — 3 LSB DNL Differential non-linearity — –1 — 1 LSB OFS Offset error — –6 — 6 LSB GNE Gain error — –4 — 4 LSB Max leakage (precision channel) 150 °C — — 250 nA Max leakage (standard channel) 150 °C — — 2500 nA Max leakage (standard channel) 105 °C TA — 5 250 nA ADC Analog Pad (pad going to one ADC) –5 — 5 mA TUEprecision channels Total unadjusted error for precision Without current injection channels With current injection7 Max positive/negative injection –6 +/-4 6 LSB TUEstandard/extended Total unadjusted error for standard/ Without current injection extended channels channels With current injection7 –8 trecovery +/-5 +/-6 LSB 8 +/-8 STOP mode to Run mode recovery time LSB LSB