SPC5777CCK3MMO3R

NXP Semiconductors Data Sheet: Technical Data Document Number MPC5777C Rev. 15, 03/2021 MPC5777C MPC5777C Microcontroller Data Sheet Features • This document provides electrical specifications, pin assignments, and package diagram information for the MPC5777C series of microcontroller units (MCUs). • For functional characteristics and the programming model, see the MPC5777C Reference Manual. NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Table of Contents 1 Introduction.......................................................................................... 3 3.11 Power management: PMC, POR/LVD, power sequencing.......39 1.1 Features summary......................................................................3 3.11.1 Power management electrical characteristics.........39 1.2 Block diagram........................................................................... 4 3.11.2 Power management integration.............................. 42 2 Pinouts..................................................................................................5 3.11.3 Device voltage monitoring..................................... 43 3.11.4 Power sequencing requirements............................. 45 2.1 416-ball MAPBGA pin assignments......................................... 5 2.2 516-ball MAPBGA pin assignments......................................... 6 3.12 Flash memory specifications..................................................... 46 3 Electrical characteristics.......................................................................7 3.12.1 Flash memory program and erase specifications... 47 3.12.2 Flash memory Array Integrity and Margin Read 3.1 Absolute maximum ratings....................................................... 7 3.2 Electromagnetic interference (EMI) characteristics..................9 3.3 Electrostatic discharge (ESD) characteristics............................9 3.12.3 Flash memory module life specifications...............48 3.4 Operating conditions................................................................. 9 3.12.4 Data retention vs program/erase cycles..................49 3.5 DC electrical specifications.......................................................12 3.12.5 Flash memory AC timing specifications................ 49 3.6 I/O pad specifications................................................................ 13 3.12.6 Flash memory read wait-state and address- 3.7 3.8 3.6.1 Input pad specifications..........................................13 pipeline control settings..........................................50 3.6.2 Output pad specifications....................................... 15 3.13 AC timing.................................................................................. 51 3.6.3 I/O pad current specifications.................................18 3.13.1 Generic timing diagrams........................................ 51 Oscillator and PLL electrical specifications..............................19 3.13.2 Reset and configuration pin timing........................ 51 3.7.1 PLL electrical specifications.................................. 20 3.13.3 IEEE 1149.1 interface timing................................. 52 3.7.2 Oscillator electrical specifications..........................21 3.13.4 Nexus timing.......................................................... 55 Analog-to-Digital Converter (ADC) electrical specifications...23 3.13.5 External Bus Interface (EBI) timing...................... 57 3.8.1 Enhanced Queued Analog-to-Digital Converter 3.13.6 External interrupt timing (IRQ/NMI pin)...............61 (eQADC)................................................................ 23 3.13.7 eTPU timing........................................................... 62 Sigma-Delta ADC (SDADC)................................. 25 3.13.8 eMIOS timing.........................................................63 Temperature Sensor...................................................................32 3.13.9 DSPI timing with CMOS and LVDS pads.............64 3.13.10 FEC timing............................................................. 77 3.8.2 3.9 specifications.......................................................... 47 3.10 LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical characteristics.............................................................33 3.10.1 LFAST interface timing diagrams..........................33 3.10.2 LFAST and MSC/DSPI LVDS interface electrical 3.10.3 4 Package information.............................................................................81 4.1 Thermal characteristics..............................................................81 4.1.1 General notes for thermal characteristics............... 82 characteristics......................................................... 35 5 Ordering information............................................................................85 LFAST PLL electrical characteristics.................... 38 6 Document revision history................................................................... 86 MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 2 NXP Semiconductors Introduction 1 Introduction 1.1 Features summary On-chip modules available within the family include the following features: • Three dual issue, 32-bit CPU core complexes (e200z7), two of which run in lockstep • Power Architecture embedded specification compliance • Instruction set enhancement allowing variable length encoding (VLE), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction • On the two computational cores: Signal processing extension (SPE1.1) instruction support for digital signal processing (DSP) • Single-precision floating point operations • On the two computational cores: 16 KB I-Cache and 16 KB D-Cache • Hardware cache coherency between cores • 16 hardware semaphores • 3-channel CRC module • 8 MB on-chip flash memory • Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation • 512 KB on-chip general-purpose SRAM including 64 KB standby RAM • Two multichannel direct memory access controllers (eDMA) • 64 channels per eDMA • Dual core Interrupt Controller (INTC) • Dual phase-locked loops (PLLs) with stable clock domain for peripherals and frequency modulation (FM) domain for computational shell • Crossbar Switch architecture for concurrent access to peripherals, flash memory, or RAM from multiple bus masters with End-To-End ECC • External Bus Interface (EBI) for calibration and application use • System Integration Unit (SIU) • Error Injection Module (EIM) and Error Reporting Module (ERM) • Four protected port output (PPO) pins • Boot Assist Module (BAM) supports serial bootload via CAN or SCI • Three second-generation Enhanced Time Processor Units (eTPUs) • 32 channels per eTPU • Total of 36 KB code RAM • Total of 9 KB parameter RAM MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 3 Introduction • Enhanced Modular Input/Output System (eMIOS) supporting 32 unified channels with each channel capable of single action, double action, pulse width modulation (PWM) and modulus counter operation • Two Enhanced Queued Analog-to-Digital Converter (eQADC) modules with: • Two separate analog converters per eQADC module • Support for a total of 70 analog input pins, expandable to 182 inputs with offchip multiplexers • Interface to twelve hardware Decimation Filters • Enhanced "Tap" command to route any conversion to two separate Decimation Filters • Four independent 16-bit Sigma-Delta ADCs (SDADCs) • 10-channel Reaction Module • Ethernet (FEC) • Two PSI5 modules • Two SENT Receiver (SRX) modules supporting 12 channels • Zipwire: SIPI and LFAST modules • Five Deserial Serial Peripheral Interface (DSPI) modules • Five Enhanced Serial Communication Interface (eSCI) modules • Four Controller Area Network (FlexCAN) modules • Two M_CAN modules that support FD • Fault Collection and Control Unit (FCCU) • Clock Monitor Units (CMUs) • Tamper Detection Module (TDM) • Cryptographic Services Engine (CSE) • Complies with Secure Hardware Extension (SHE) Functional Specification Version 1.1 security functions • Includes software selectable enhancement to key usage flag for MAC verification and increase in number of memory slots for security keys • PASS module to support security features • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard • Device and board test support per Joint Test Action Group (JTAG) IEEE 1149.1 and 1149.7 • On-chip voltage regulator controller (VRC) that derives the core logic supply voltage from the high-voltage supply • On-chip voltage regulator for flash memory • Self Test capability MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 4 NXP Semiconductors Pinouts 1.2 Block diagram The following figure shows a top-level block diagram of the MPC5777C. The purpose of the block diagram is to show the general interconnection of functional modules through the crossbar switch. COMPUTATIONAL SHELL FLEXCAN_A-B MCAN_0-1 e200z7 checker core complex SWT e200z7 (dual issue) e200z7 (dual issue) STM INTC FPU DEBUG SWT STM JTAG MMU Nexus 3+ DTS DSPI_A-C eSCI_A-C INTC FPU ETPU_C w/RAM VLE VLE 16K I-Cache 16K I-Cache 64ch eDMA 16K D-Cache 16K D-Cache 64ch eDMA MMU MMU Ethernet eMIOS_0 eQADC_A & Temp Sensors DECFILTER_A-L SDADC_1/3 SRX_0 Crossbar Switch with ECC Safety Monitor MPU PSI5_0 REACM2 SRAM Control EBI Flash Control Zipwire/ SIPI/LFAST Bridge A Dual PLL/ OSC/IRC Security Tamper Detection CRC CSE SRAM Flash w/ EEPROM Bridge B PCM/ERM SIU/SIU_B CMU_0-8 EBI registers FCCU STCU PMU/PMC PIT-RTI FlexCAN_C-D DSPI_D-E eSCI_D-F ETPU_A/B (w/RAM) eMIOS_1 eQADC_B SDADC_2/4 SRX_1 PSI5_1 Figure 1. MPC5777C block diagram 2 Pinouts 2.1 416-ball MAPBGA pin assignments Figure 2 shows the 416-ball MAPBGA pin assignments. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 5 Pinouts Figure 2. MPC5777C 416-ball MAPBGA (full diagram) 2.2 516-ball MAPBGA pin assignments Figure 3 shows the 516-ball MAPBGA pin assignments. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 6 NXP Semiconductors Electrical characteristics Figure 3. MPC5777C 516-ball MAPBGA (full diagram) 3 Electrical characteristics The following information includes details about power considerations, DC/AC electrical characteristics, and AC timing specifications. 3.1 Absolute maximum ratings Absolute maximum specifications are stress ratings only. Functional operation at these maxima is not guaranteed. CAUTION Stress beyond listed maxima may affect device reliability or cause permanent damage to the device. See Operating conditions for functional operation specifications. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 7 Electrical characteristics Table 1. Absolute maximum ratings Symbol Cycle VDD VDDEHx VDDEx Conditions1 Parameter Lifetime power cycles 1.2 V core supply voltage2, 3, 4 I/O supply voltage (medium I/O I/O supply voltage (fast I/O pads)5 pads)5 Value Unit Min Max — — 1000k — — –0.3 1.5 V — –0.3 6.0 V — –0.3 6.0 V VDDPMC Power Management Controller supply voltage5 — –0.3 6.0 V VDDFLA Decoupling pin for flash regulator6 — –0.3 4.5 V VSTBY RAM standby supply voltage5 — –0.3 6.0 V VSSA_SD SDADC ground voltage Reference to VSS –0.3 0.3 V VSSA_EQ eQADC ground voltage Reference to VSS –0.3 0.3 V VDDA_EQA/B eQADC supply voltage Reference to VSSA_EQ –0.3 6.0 V VDDA_SD SDADC supply voltage Reference to VSSA_SD –0.3 6.0 V VRL_SD SDADC ground reference Reference to VSS –0.3 0.3 V VRL_EQ eQADC ground reference Reference to VSS –0.3 0.3 V VRH_EQ eQADC alternate reference Reference to VRL_EQ –0.3 6.0 V VRH_SD SDADC alternate reference Reference to VRL_SD –0.3 6.0 V VREFBYPC eQADC reference decoupling capacitor pins REFBYPCA25, REFBYPCA75, REFBYPCB25, REFBYPC75 –0.3 6.0 V VDDA_MISC TRNG and IRC supply voltage — –0.3 6.0 V VDDPWR SMPS driver supply pin — –0.3 6.0 V VSSPWR SMPS driver supply pin Reference to VSS –0.3 0.3 V VSS – VSSA_EQ VSSA_EQ differential voltage — –0.3 0.3 V VSS – VSSA_SD VSSA_SD differential voltage — –0.3 0.3 V VSS – VRL_EQ VRL_EQ differential voltage — –0.3 0.3 V VSS – VRL_SD VRL_SD differential voltage — –0.3 0.3 V — –0.3 6.0 V — 0.3 V –0.3 — V VIN I/O input voltage range7 Relative to VDDEx/VDDEHx Relative to VSS IINJD Maximum DC injection current for digital Per pin, applies to all digital pins pad –5 5 mA IINJA Maximum DC injection current for analog pad Per pin, applies to all analog pins –5 5 mA Maximum current per I/O power segment — –120 120 mA Storage temperature range and nonoperating times — –55 175 °C Maximum storage time, assembled part No supply; storage temperature in programmed in ECU range –40 °C to 60 °C — 20 years Maximum solder temperature10 — 260 °C IMAXSEG8, 9 TSTG STORAGE TSDR — Pb-free package Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 8 NXP Semiconductors Electrical characteristics Table 1. Absolute maximum ratings (continued) Symbol Moisture sensitivity level11 MSL Value Conditions1 Parameter Min Max — 3 — Unit — 1. Voltages are referred to VSS if not specified otherwise 2. Allowed 1.45 V – 1.5 V for 60 seconds cumulative time at maximum TJ = 150 °C; remaining time as defined in note -1 and note -1 3. Allowed 1.375 V – 1.45 V for 10 hours cumulative time at maximum TJ = 150 °C; remaining time as defined in note -1 4. 1.32 V – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at maximum TJ = 150 °C 5. Allowed 5.5 V – 6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ = 150 °C; remaining time at or below 5.5 V 6. Allowed 3.6 V – 4.5 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ = 150 °C; remaining time at or below 3.6 V 7. The maximum input voltage on an I/O pin tracks with the associated I/P supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal calculations. 8. The sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDDEx/VDDEHx power segment is defined as one or more GPIO pins located between two VDDEx/VDDEHx supply pins. 9. The average current values given in I/O pad current specifications should be used to calculate total I/O segment current. 10. Solder profile per IPC/JEDEC J-STD-020D 11. Moisture sensitivity per JEDEC test method A112 3.2 Electromagnetic interference (EMI) characteristics Test reports with EMC measurements to IC-level IEC standards are available on request. To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to nxp.com and perform a keyword search for "radiated emissions." 3.3 Electrostatic discharge (ESD) characteristics Table 2. ESD Ratings1, 2 Symbol Parameter VHBM ESD for Human Body Model (HBM) VCDM ESD for Charged Device Model (CDM) Conditions Value Unit All pins 2000 V Corner pins 750 V Non-corner pins 500 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 9 Electrical characteristics 3.4 Operating conditions The following table describes the operating conditions for the device, and for which all specifications in the data sheet are valid, except where explicitly noted. If the device operating conditions are exceeded, the functionality of the device is not guaranteed. Table 3. Device operating conditions Symbol Parameter Conditions Value Unit Min Typ Max — — 264/3062 MHz — 132/153, 3 MHz MHz Frequency fSYS Device operating fPLATF frequency1 Platform operating frequency — — — eTPU operating frequency — — — 200/2404 fEBI EBI operating frequency — — — 66 MHz fPER Peripheral block operating frequency — — — 132/1533 MHz Frequency-modulated peripheral — block operating frequency — — 132/1503 MHz fETPU fFM_PER Platform clock period — — — 1/fPLATF ns tCYC_ETPU tCYC eTPU clock period — — — 1/fETPU ns tCYC_PER Peripheral clock period — — — 1/fPER ns Temperature TJ Junction operating temperature range Packaged devices –40.0 — 150.0 °C TA (TL to TH) Ambient operating temperature range Packaged devices –40.0 — 125.05 °C 1.2 — 1.32 V 1.2 — 1.38 3.5 — 5.5 V 4.5 — 5.5 V 3.3 V range 3.0 — 3.6 I/O supply voltage (medium I/O pads) 5 V range 4.5 — 5.5 3.3 V range 3.0 — 3.6 VDDEH1 eTPU_A, eSCI_A, eSCI_B, and configuration I/O supply voltage (medium I/O pads) 5 V range 4.5 — 5.5 V VDDPMC12 Power Management Controller (PMC) supply voltage Full functionality 3.15 — 5.5 V VDDPWR SMPS driver supply voltage Reference to VSSPWR 3.0 — 5.5 V VDDFLA Flash core voltage — 3.15 — 3.6 V — 0.9513 — 5.5 V Voltage VDD External core supply voltage6, 7 LVD/HVD enabled LVD/HVD VDDA_MISC VDDEx VDDEHx 11 VSTBY TRNG and IRC supply voltage disabled8, 9, 10, 11 — I/O supply voltage (fast I/O pads) 5 V range RAM standby supply voltage V Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 10 NXP Semiconductors Electrical characteristics Table 3. Device operating conditions (continued) Symbol VSTBY_BO Parameter Conditions Value Min Typ Max — — 0.914 Unit Standby RAM brownout flag trip point voltage — VRL_SD SDADC ground reference voltage — VDDA_SD SDADC supply voltage15 — 4.5 — 5.5 V eQADC supply voltage — 4.75 — 5.25 V SDADC reference VDDA_EQA/B VRH_SD V V VSSA_SD — 4.5 VDDA_SD 5.5 V VDDA_SD – VRH_SD SDADC reference differential voltage — — — 25 mV VSSA_SD – VRL_SD VRL_SD differential voltage — –25 — 25 mV eQADC reference — 4.75 — 5.25 V eQADC reference differential voltage — — — 25 mV VSSA_EQ – VRL_EQ VRL_EQ differential voltage — –25 — 25 mV VSSA_EQ – VSS VSSA_EQ differential voltage — –25 — 25 mV VSSA_SD – VSS VSSA_SD differential voltage — –25 — 25 mV Slew rate on power supply pins — — — 100 V/ms Digital pins and analog pins –3.0 — 3.0 mA — –80 — 80 mA VRH_EQ VDDA_EQA/B – VRH_EQ VRAMP Current IIC IMAXSEG DC injection current (per 17, 18 pin)16, Maximum current per power segment19, 20 1. Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clocking chapter in the MPC5777C Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device. 2. If frequency modulation (FM) is enabled for the maximum operating frequency of 264 MHz or 306 MHz, the maximum frequency still cannot exceed this value when frequency modulation is enabled (frequency modulation must spread down from the maximum). 3. 132 MHz applies to the MPC5777C part number with 264 MHz operating frequency. 153 MHz applies to the version with 306 MHz operating frequency. 4. 200 MHz applies to the MPC5777C part number with 264 MHz max operating frequency. 240 MHz applies to the version with 306 MHz operating frequency. 5. The maximum specification for operating junction temperature TJ must be respected. Thermal characteristics provides details. 6. Core voltage as measured on device pin to guarantee published silicon performance 7. During power ramp, voltage measured on silicon might be lower. Maximum performance is not guaranteed, but correct silicon operation is guaranteed. See power management and reset management for description. 8. Maximum core voltage is not permitted for entire product life. See absolute maximum rating. 9. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor externally supply voltage may result in erroneous operation of the device. 10. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the reset sequence, and the LVD/HVD are active until that point. 11. This spec does not apply to VDDEH1. 12. When internal flash memory regulator is used: • Flash memory read operation is supported for a minimum VDDPMC value of 3.15 V. • Flash memory read, program, and erase operations are supported for a minimum VDDPMC value of 3.5 V. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 11 Electrical characteristics 13. 14. 15. 16. 17. 18. 19. 20. When flash memory power is supplied externally (VDDPMC shorted to VDDFLA): The VDDPMC range must be within the limits specified for LVD_FLASH and HVD_FLASH monitoring. Table 1 provides the monitored LVD_FLASH and HVD_FLASH limits. If the standby RAM regulator is not used, the VSTBY supply input pin must be tied to ground. VSTBY_BO is the maximum voltage that sets the standby RAM brownout flag in the device logic. The minimum voltage for RAM data retention is guaranteed always to be less than the VSTBY_BO maximum value. For supply voltages between 3.0 V and 4.0 V there will be no guaranteed precision of ADC (accuracy/linearity). ADC will recover to a fully functional state when the voltage rises above 4.0 V. Full device lifetime without performance degradation I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the absolute maximum ratings table for maximum input current for reliability requirements. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network calculation, assume a typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. The sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDDEx/VDDEHx power segment is defined as one or more GPIO pins located between two VDDEx/VDDEHx supply pins. The average current values given in I/O pad current specifications should be used to calculate total I/O segment current. 3.5 DC electrical specifications NOTE IDDA_MISC is the sum of current consumption of IRC, ITRNG, and ISTBY in the 5 V domain. IRC current is provided in the IRC specifications. NOTE I/O, XOSC, EQADC, SDADC, and Temperature Sensor current specifications are in those components' dedicated sections. Table 4. DC electrical specifications Symbol IDD Parameter Conditions Operating current on the VDD core logic supply1 Value Min Typ Max LVD/HVD enabled, VDD = 1.2 V to 1.32 V — 0.65 1.35 LVD/HVD disabled, VDD = 1.2 V to 1.38 V — 0.65 1.4 Unit A IDD_PE Operating current on the VDD supply for flash memory program/erase — — — 85 mA IDDPMC Operating current on the VDDPMC supply2 Flash memory read — — 40 mA Flash memory program/erase — — 70 PMC only — — 35 Flash memory read — — 10 Flash memory program/erase — — 40 PMC only — — 5 Core regulator DC current output on VREGCTL pin — — — 25 mA Standby RAM supply current 1.08 V, TJ = 150°C — — 1140 μA Operating current on the VDDPMC supply (internal core regulator bypassed) IREGCTL ISTBY mA Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 12 NXP Semiconductors Electrical characteristics Table 4. DC electrical specifications (continued) Symbol IDD_PWR IBG_REF ITRNG Parameter Operating current on the VDDPWR supply Bandgap reference current Conditions Min Typ Max 1.25 V to 5.5 V, TJ = 150°C 1170 1.25 V to 5.5 V, TJ = 85°C 360 Unit 1.25 V to 5.5 V, TJ = 40°C — — 120 — — — 50 mA — — 600 μA — — 2.1 mA consumption3 True Random Number Generator current Value — 1. IDD measured on an application-specific pattern with all cores enabled at full frequency, TJ = 40°C to 150°C. Flash memory program/erase current on the VDD supply not included. 2. This value is considering the use of the internal core regulator with the simulation of an external transistor with the minimum value of hFE of 60. 3. This bandgap reference is for EQADC calibration and Temperature Sensors. 3.6 I/O pad specifications The following table describes the different pad types on the chip. Table 5. I/O pad specification descriptions Pad type Description General-purpose I/O pads General-purpose I/O and EBI data bus pads with four selectable output slew rate settings; also called SR pads EBI pads Provide necessary speed for fast external memory interfaces on the EBI CLKOUT, address, and control signals; also called FC pads LVDS pads Low Voltage Differential Signal interface pads Input-only pads Low-input-leakage pads that are associated with the ADC channels NOTE Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin. NOTE Throughout the I/O pad specifications, the symbol VDDEx represents all VDDEx and VDDEHx segments. 3.6.1 Input pad specifications Table 6 provides input DC electrical characteristics as described in Figure 4. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 13 Electrical characteristics V IN V DD V IH V HYS V IL V INTERNAL (SIU register) Figure 4. I/O input DC electrical characteristics definition Table 6. I/O input DC electrical characteristics Symbol VIHCMOS_H VIHCMOS VILCMOS_H VILCMOS VHYSCMOS Parameter Conditions Input high level CMOS (with hysteresis) 3.0 V < VDDEx < 3.6 V and Input high level CMOS (without hysteresis) 3.0 V < VDDEx < 3.6 V and Input low level CMOS (with hysteresis) 3.0 V < VDDEx < 3.6 V and Input low level CMOS (without hysteresis) 3.0 V < VDDEx < 3.6 V and Input hysteresis CMOS 3.0 V < VDDEx < 3.6 V and Value Unit Min Typ Max 0.65 * VDDEx — VDDEx + 0.3 V 0.55 * VDDEx — VDDEx + 0.3 V –0.3 — 0.35 * VDDEx V –0.3 — 0.4 * VDDEx V 0.1 * VDDEx — — V 4.5 V < VDDEx < 5.5 V 4.5 V < VDDEx < 5.5 V 4.5 V < VDDEx < 5.5 V 4.5 V < VDDEx < 5.5 V 4.5 V < VDDEx < 5.5 V Input Characteristics1 ILKG ILKG_FAST ILKGA CIN Digital input leakage VSS < VIN < VDDEx/VDDEHx — — 2.5 μA Digital input leakage for EBI address/control signal pads VSS < VIN < VDDEx/VDDEHx — — 2.5 μA Analog pin input leakage (5 V range) VSSA_SD < VIN < VDDA_SD, VSSA_EQ < VIN < VDDA_EQA/B — — 220 nA Digital input capacitance GPIO and EBI input pins — — 7 pF 1. For LFAST, microsecond bus, and LVDS input characteristics, see dedicated communication module sections. Table 7 provides current specifications for weak pullup and pulldown. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 14 NXP Semiconductors Electrical characteristics Table 7. I/O pullup/pulldown DC electrical characteristics Symbol IWPU Parameter Conditions Weak pullup current VIN = 0.35 * VDDEx Value Min Typ Max 40 — 120 25 — 80 40 — 120 25 — 80 Unit μA 4.5 V < VDDEx < 5.5 V VIN = 0.35 * VDDEx 3.0 V < VDDEx < 3.6 V IWPD Weak pulldown current VIN = 0.65 * VDDEx μA 4.5 V < VDDEx < 5.5 V VIN = 0.65 * VDDEx 3.0 V < VDDEx < 3.6 V The specifications in Table 8 apply to the pins ANA0_SDA0 to ANA7, ANA16_SDB0 to ANA23_SDC3, and ANB0_SDD0 to ANB7_SDD7. Table 8. I/O pullup/pulldown resistance electrical characteristics Symbol Parameter Conditions RPUPD Analog input bias / diagnostic pullup/ pulldown resistance ΔPUPD Value Min Typ Max 200 kΩ 130 200 280 100 kΩ 65 100 140 5 kΩ 1.4 5 7.5 — — 5 RPUPD pullup/pulldown resistance mismatch — Unit kΩ % 3.6.2 Output pad specifications Figure 5 shows output DC electrical characteristics. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 15 Electrical characteristics core side input VDD/2 tPD (low to high) tPD (high to low) VDDEx Voh PAD Vol VSSEx Rise Time Fall Time Figure 5. I/O output DC electrical characteristics definition The following tables specify output DC electrical characteristics. Table 9. GPIO and EBI data pad output buffer electrical characteristics (SR pads)1 Symbol IOH IOL Parameter Conditions2 GPIO pad output high current VOH = 0.8 * VDDEx GPIO pad output low current Value3 Min Typ Max PCR[SRC] = 11b or 01b 25 — — 4.5 V < VDDEx < 5.5 V PCR[SRC] = 10b or 00b 15 — — VOH = 0.8 * VDDEx PCR[SRC] = 11b or 01b 13 — — 3.0 V < VDDEx < 3.6 V PCR[SRC] = 10b or 00b 8 — — VOL = 0.2 * VDDEx PCR[SRC] = 11b or 01b 48 — — 4.5 V < VDDEx < 5.5 V PCR[SRC] = 10b or 00b 22 — — VOL = 0.2 * VDDEx 17 — — 10.5 — — CL = 25 pF — — 1.2 4.5 V < VDDEx < 5.5 V CL = 50 pF — — 2.5 CL = 200 pF — — 8 CL = 25 pF — — 1.7 3.0 V < VDDEx < 3.6 V CL = 50 pF — — 3.25 CL = 200 pF — — 12 CL = 50 pF — — 5 4.5 V < VDDEx < 5.5 V CL = 200 pF — — 18 PCR[SRC] = 10b — — 7 3.0 V < VDDEx < 3.6 V CL = 200 pF — — 25 PCR[SRC] = 01b — — 13 4.5 V < VDDEx < 5.5 V CL = 200 pF — — 24 PCR[SRC] = 01b — — 25 PCR[SRC] = 11b or 01b 3.0 V < VDDEx < 3.6 V PCR[SRC] = 10b or 00b tR_F GPIO pad output transition time (rise/fall) PCR[SRC] = 11b PCR[SRC] = 11b PCR[SRC] = 10b CL = 50 pF CL = 50 pF CL = 50 pF Unit mA mA ns Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 16 NXP Semiconductors Electrical characteristics Table 9. GPIO and EBI data pad output buffer electrical characteristics (SR pads)1 (continued) Symbol tPD Value3 Conditions2 Parameter GPIO pad output propagation delay time |tSKEW_W| Difference between rise and fall time Min Typ Max 3.0 V < VDDEx < 3.6 V CL = 200 pF — — 30 PCR[SRC] = 00b — — 24 4.5 V < VDDEx < 5.5 V CL = 200 pF — — 50 PCR[SRC] = 00b — — 40 3.0 V < VDDEx < 3.6 V CL = 200 pF — — 51 PCR[SRC] = 11b — — 6 4.5 V < VDDEx < 5.5 V CL = 200 pF — — 13 PCR[SRC] = 11b — — 8.25 3.0 V < VDDEx < 3.6 V CL = 200 pF — — 19.5 PCR[SRC] = 10b — — 9 4.5 V < VDDEx < 5.5 V CL = 200 pF — — 22 PCR[SRC] = 10b — — 12.5 3.0 V < VDDEx < 3.6 V CL = 200 pF — — 35 PCR[SRC] = 01b — — 27 4.5 V < VDDEx < 5.5 V CL = 200 pF — — 40 PCR[SRC] = 01b — — 45 3.0 V < VDDEx < 3.6 V CL = 200 pF — — 65 PCR[SRC] = 00b — — 40 4.5 V < VDDEx < 5.5 V CL = 200 pF — — 65 PCR[SRC] = 00b — — 75 3.0 V < VDDEx < 3.6 V CL = 200 pF — — 100 — — — 25 CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Unit ns % 1. All GPIO pad output specifications are valid for 3.0 V < VDDEx < 5.5 V, except where explicitly stated. 2. PCR[SRC] values refer to the setting of that register field in the SIU. 3. All values to be confirmed during device validation. The following table shows the EBI CLKOUT, address, and control signal pad electrical characteristics. These pads can also be used for GPIO. Table 10. GPIO and EBI CLKOUT, address, and control signal pad output buffer electrical characteristics (FC pads) Symbol Conditions1 Parameter Value Min Typ Max Unit EBI Mode Output Specifications: valid for 3.0 V < VDDEx < 3.6 V CDRV External bus load capacitance PCR[DSC] = 01b — — 10 PCR[DSC] = 10b — — 20 pF Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 17 Electrical characteristics Table 10. GPIO and EBI CLKOUT, address, and control signal pad output buffer electrical characteristics (FC pads) (continued) Symbol Value Conditions1 Parameter Unit Min Typ Max PCR[DSC] = 11b — — 30 CDRV = 10/20/30 pF — — 66 MHz mA fMAX_EBI External bus maximum operating frequency IOH_EBI GPIO and external bus VOH = 0.8 * VDDEx PCR[DSC] = 11b pad output high current 4.5 V < VDDEx < 5.5 V PCR[DSC] = 10b 30 — — 22 — — PCR[DSC] = 01b 13 — — PCR[DSC] = 00b 2 — — PCR[DSC] = 11b 16 — — 3.0 V < VDDEx < 3.6 V PCR[DSC] = 10b 12 — — PCR[DSC] = 01b 7 — — PCR[DSC] = 00b 1 — — PCR[DSC] = 11b 54 — — 4.5 V < VDDEx < 5.5 V PCR[DSC] = 10b 25 — — PCR[DSC] = 01b 16 — — PCR[DSC] = 00b 2 — — PCR[DSC] = 11b 17 — — 3.0 V < VDDEx < 3.6 V PCR[DSC] = 10b 14 — — PCR[DSC] = 01b 8 — — PCR[DSC] = 00b 1 — — CL = 30 pF — — 1.5 CL = 50 pF — — 2.4 PCR[DSC] = 10b CL = 20 pF — — 1.5 PCR[DSC] = 01b CL = 10 pF — — 1.85 PCR[DSC] = 00b CL = 50 pF — — 45 GPIO and external bus PCR[DSC] = 11b pad output propagation delay time PCR[DSC] = 10b CL = 30 pF — — 4.2 CL = 50 pF — — 5.5 CL = 20 pF — — 4.2 PCR[DSC] = 01b CL = 10 pF — — 4.4 PCR[DSC] = 00b CL = 50 pF — — 59 GPIO and EBI Mode Output Specifications VOH = 0.8 * VDDEx IOL_EBI GPIO and external bus pad output low current VOL = 0.2 * VDDEx VOL = 0.2 * VDDEx tR_F_EBI tPD_EBI GPIO and external bus pad output transition time (rise/fall) PCR[DSC] = 11b mA ns ns 1. PCR[DSC] values refer to the setting of that register field in the SIU. 3.6.3 I/O pad current specifications The I/O pads are distributed across the I/O supply segments. Each I/O supply segment is associated with a VDDEx supply segment. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 18 NXP Semiconductors Electrical characteristics Table 11 provides I/O consumption figures. To ensure device reliability, the average current of the I/O on a single segment should remain below the IMAXSEG value given in Table 1. To ensure device functionality, the average current of the I/O on a single segment should remain below the IMAXSEG value given in Table 3. NOTE The MPC5777C I/O Signal Description and Input Multiplexing Tables are contained in a Microsoft Excel® file attached to the Reference Manual. In the spreadsheet, select the I/O Signal Table tab. The EBI power segments have been designed to operate within the maximum persegment current specification when the pins on the segment are used for EBI function. If the pins are used instead for GPIO function, the user must ensure the sum of the current used on each pin in the segment does not exceed the spec. Table 11. I/O consumption Symbol IAVG_GPIO Parameter Conditions Average I/O current for GPIO pads CL = 25 pF, 2 MHz (per pad) VDDEx = 5.0 V ± 10% CL = 50 pF, 1 MHz Value Min Typ Max — — 0.42 — — 0.35 — — 9 — — 18 — — 30 Unit mA VDDEx = 5.0 V ± 10% IAVG_EBI Average I/O current for external bus output pins (per pad) CDRV = 10 pF, fEBI = 66 MHz mA VDDEx = 3.3 V ± 10% CDRV = 20 pF, fEBI = 66 MHz VDDEx = 3.3 V ± 10% CDRV = 30 pF, fEBI = 66 MHz VDDEx = 3.3 V ± 10% 3.7 Oscillator and PLL electrical specifications The on-chip dual PLL—consisting of the peripheral clock and reference PLL (PLL0) and the frequency-modulated system PLL (PLL1)—generates the system and auxiliary clocks from the main oscillator driver. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 19 Electrical characteristics PLL0_PHI IRC PLL0 PLL0_PHI1 XOSC PLL1_PHI PLL1 Figure 6. PLL integration 3.7.1 PLL electrical specifications Table 12. PLL0 electrical characteristics Symbol Parameter Conditions Value Min Typ Max Unit fPLL0IN PLL0 input clock1, 2 — 8 — 44 MHz ΔPLL0IN PLL0 input clock duty cycle2 — 40 — 60 % fPLL0VCO PLL0 VCO frequency — 600 — 1250 MHz fPLL0PHI PLL0 output frequency — 4.762 — 200/24 03 MHz PLL0 lock time — — — 110 μs PLL0_PHI single period jitter fPLL0PHI = 200 MHz, 6-sigma — — 200 ps fPLL0PHI1 = 40 MHz, 6-sigma — — 3004 ps 10 periods accumulated jitter (80 MHz equivalent frequency), 6-sigma pk-pk — — ±250 ps 16 periods accumulated jitter (50 MHz equivalent frequency), 6-sigma pk-pk — — ±300 ps long term jitter (< 1 MHz equivalent frequency), 6-sigma pk-pk) — — ±500 ps FINE LOCK state — — 7.5 mA tPLL0LOCK |ΔPLL0PHISPJ| fPLL0IN = 20 MHz (resonator) |ΔPLL0PHI1SPJ| PLL0_PHI1 single period jitter fPLL0IN = 20 MHz (resonator) ΔPLL0LTJ PLL0 output long term jitter4 fPLL0IN = 20 MHz (resonator), VCO frequency = 800 MHz IPLL0 PLL0 consumption 1. Ensure that the fPLL0IN frequency divided by PLLDIG_PLL0DV[PREDIV] is in the range 8 MHz to 20 MHz. 2. PLL0IN clock retrieved directly from either internal IRC or external XOSC clock. Input characteristics are granted when using internal IRC or external oscillator is used in functional mode. 3. 200 MHz applies to the MPC5777C part number with 264 MHz operating frequency. 240 MHz applies to the version with 306 MHz operating frequency. 4. Noise on the VDD supply with frequency content below 40 kHz and above 50 MHz is filtered by the PLL. Noise on the VDD supply with frequency content in the range of 40 kHz – 50 MHz must be filtered externally to the device. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 20 NXP Semiconductors Electrical characteristics Table 13. PLL1 electrical characteristics Symbol Parameter Conditions Value Min Typ Max Unit fPLL1IN PLL1 input clock1 — 38 — 78 MHz ΔPLL1IN PLL1 input clock duty cycle1 — 35 — 65 % fPLL1VCO PLL1 VCO frequency — 600 — 1250 MHz MHz fPLL1PHI tPLL1LOCK |ΔPLL1PHISPJ| fPLL1MOD |δPLL1MOD| IPLL1 PLL1 output clock PHI — 4.762 — 264/3002 PLL1 lock time — — — 100 μs ps PLL1_PHI single period peak-topeak jitter fPLL1PHI = 200 MHz, 6sigma — — 5003 PLL1 modulation frequency — — — 250 kHz PLL1 modulation depth (when enabled) Center spread 0.25 — 2 % Down spread 0.5 — 4 % PLL1 consumption FINE LOCK state — — 6 mA 1. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when using internal PLL0 or external oscillator in functional mode. 2. 264 MHz applies to the MPC5777C part number with 264 MHz operating frequency. 306 MHz applies to the version with 306 MHz operating frequency. 3. Noise on the VDD supply with frequency content below 40 kHz and above 50 MHz is filtered by the PLL. Noise on the VDD supply with frequency content in the range of 40 kHz – 50 MHz must be filtered externally to the device. 3.7.2 Oscillator electrical specifications NOTE All oscillator specifications in Table 14 are valid for VDDEH6 = 3.0 V to 5.5 V. Table 14. External oscillator (XOSC) electrical specifications Symbol fXTAL tcst trec Parameter Conditions Crystal frequency range Crystal start-up time1, 2 Crystal recovery time3 Max — 8 40 MHz TJ = 150 °C — 5 ms — — 0.5 ms VREF + 0.6 — V VREF = 0.28 * VDDEH6 — VREF – 0.6 V 416-ball MAPBGA 2.3 3.0 pF 516-ball MAPBGA 2.1 2.8 416-ball MAPBGA 2.3 3.0 516-ball MAPBGA 2.2 2.9 Low 3 10 Medium 10 27 EXTAL input high voltage (external reference) VREF = 0.28 * VDDEH6 VILEXT EXTAL input low voltage (external reference) CS_EXTAL Total on-chip stray capacitance on EXTAL CS_XTAL Total on-chip stray capacitance on XTAL pin4 gm Oscillator transconductance5 Unit Min VIHEXT pin4 Value pF mA/V Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 21 Electrical characteristics Table 14. External oscillator (XOSC) electrical specifications (continued) Symbol Parameter Value Conditions Unit Min Max High 12 35 Oscillation amplitude on the EXTAL pin after startup6 — 0.5 1.6 VHYS Comparator hysteresis — 0.1 1.0 V IXTAL XTAL current6, 7 — — 14 mA VEXTAL V 1. This value is determined by the crystal manufacturer and board design. 2. Proper PC board layout procedures must be followed to achieve specifications. 3. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load capacitor value. 4. See crystal manufacturer's specification for recommended load capacitor (CL) values.The external oscillator requires external load capacitors when operating in a "low" transconductance range. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL) and PCB capacitance when selecting a load capacitor value. When operating in a "medium" or "high" transconductance range, the integrated load capacitor value is selected via software to match the crystal manufacturer's specification, while accounting for on-chip and PCB capacitance. 5. Select a "low," "medium," or "high" setting using the UTEST Miscellaneous DCF client's XOSC_LF_EN and XOSC_EN_HIGH fields. "Low" is the setting commonly used for crystals at 8 MHz, "medium" is commonly used for crystals greater than 8 MHz to 20 MHz, and "high" is commonly used for crystals greater than 20 MHz to 40 MHz. However, the user must characterize carefully to determine the best gm setting for the intended application because crystal load capacitance, board layout, and other factors affect the gm value that is needed. The user may need an additional Rshunt to optimize gm depending on the system environment. Use of overtone crystals is not recommended. 6. Amplitude on the EXTAL pin after startup is determined by the ALC block (that is, the Automatic Level Control Circuit). The function of the ALC is to provide high drive current during oscillator startup, while reducing current after oscillation to reduce power, distortion, and RFI, and to avoid over-driving the crystal. The operating point of the ALC is dependent on the crystal value and loading conditions. 7. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum current during startup of the oscillator. The current after oscillation is typically in the 2–3 mA range and is dependent on the load and series resistance of the crystal. Test circuit is shown in Figure 1. Table 15. Selectable load capacitance load_cap_sel[4:0] from DCF record Load capacitance1, 2 (pF) 00000 1.8 00001 2.8 00010 3.7 00011 4.6 00100 5.6 00101 6.5 00110 7.4 00111 8.4 01000 9.3 01001 10.2 01010 11.2 01011 12.1 01100 13.0 Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 22 NXP Semiconductors Electrical characteristics Table 15. Selectable load capacitance (continued) load_cap_sel[4:0] from DCF record Load capacitance1, 2 (pF) 01101 13.9 01110 14.9 01111 15.8 1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values vary ±12% across process, 0.25% across voltage, and no variation across temperature. 2. Values in this table do not include the die and package capacitances given by CS_XTAL/CS_EXTAL in Table 1. VDDEH6 Bias Current ALC IXTAL XTAL EXTAL A OFF VSSOSC + Comparator V VSS Conditions Z = R + jωL Tester VEXTAL = 0 V VXTAL = 0 V ALC INACTIVE PCB GND Figure 7. Test circuit Table 16. Internal RC (IRC) oscillator electrical specifications Symbol Parameter Conditions Value Min Typ Max Unit fTarget IRC target frequency — — 16 — MHz δfvar_T IRC frequency variation T < 150 °C –8 — 8 % 3.8 Analog-to-Digital Converter (ADC) electrical specifications MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 23 Electrical characteristics 3.8.1 Enhanced Queued Analog-to-Digital Converter (eQADC) Table 17. eQADC conversion specifications (operating) Symbol fADCLK CC TSR Value Parameter ADC Clock (ADCLK) Frequency Conversion Cycles Stop Mode Recovery Min Max 2 33 2 + 13 Time2 128 + 10 — Unit MHz 151 ADCLK cycles μs — Resolution3 1.25 — mV INL INL: 16.5 MHz eQADC clock4 –4 4 LSB5 INL: 33 MHz eQADC clock4 –6 6 LSB –3 3 LSB –3 3 LSB DNL DNL: 16.5 MHz eQADC DNL: 33 MHz eQADC clock4 clock4 OFFNC Offset Error without Calibration 0 140 LSB OFFWC Offset Error with Calibration –8 8 LSB GAINNC Full Scale Gain Error without Calibration –150 0 LSB GAINWC Full Scale Gain Error with Calibration –8 8 LSB IINJ Disruptive Input Injection Current6, 7, 8, 9 –3 3 mA EINJ Incremental Error due to injection current10, 11 — +4 Counts — ±8 Counts - - Counts16 INL, 16.5 MHz ADC –4 4 INL, 33 MHz ADC –8 8 DNL, 16.5 MHz ADC –315 315 DNL, 33 MHz ADC –315 315 - - INL, 16.5 MHz ADC –5 5 INL, 33 MHz ADC –8 8 DNL, 16.5 MHz ADC –3 3 –3 3 - - INL, 16.5 MHz ADC –7 7 INL, 33 MHz ADC –8 8 DNL, 16.5 MHz ADC –4 4 DNL, 33 MHz ADC –4 4 IADC Current consumption per ADC (two ADCs per EQADC) — 10 mA IADR Reference voltage current consumption per EQADC — 200 μA TUE GAINVGA1 GAINVGA2 TUE value12, 13 (with calibration) Variable gain amplifier accuracy (gain = 1)14 Variable gain amplifier accuracy (gain = 2)14 DNL, 33 MHz ADC GAINVGA4 Variable gain amplifier accuracy (gain = 4)14 Counts Counts 1. 128 sampling cycles (LST=128), differential conversion, pregain of x4 2. Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms. 3. At VRH_EQ – VRL_EQ = 5.12 V, one count = 1.25 mV without using pregain. Based on 12-bit conversion result; does not account for AC and DC errors 4. INL and DNL are tested from VRL + 50 LSB to VRH – 50 LSB. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 24 NXP Semiconductors Electrical characteristics 5. At VRH_EQ – VRL_EQ = 5.12 V, one LSB = 1.25 mV. 6. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions. 7. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 8. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values. 9. Condition applies to two adjacent pins at injection limits. 10. Performance expected with production silicon. 11. All channels have same 10 kΩ < Rs < 100 kΩ Channel under test has Rs = 10 kΩ, IINJ=IINJMAX,IINJMIN. 12. The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors. 13. TUE, Gain, and Offset specifications do not apply to differential conversions. 14. Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of ×1, ×2, or ×4. Settings are for differential input only. Tested at ×1 gain. Values for other settings are guaranteed as indicated. 15. Guaranteed 10-bit monotonicity. 16. At VRH_EQ – VRL_EQ = 5.12 V, one LSB = 1.25 mV. 3.8.2 Sigma-Delta ADC (SDADC) The SDADC is a 16-bit Sigma-Delta analog-to-digital converter with a 333 Ksps maximum output conversion rate. NOTE The voltage range is 4.5 V to 5.5 V for SDADC specifications, except where noted otherwise. Table 18. SDADC electrical specifications Symbol VIN VIN_PK2PK 1 Parameter Conditions ADC input signal — Input range peak to peak Single ended VIN_PK2PK = VINP2 – VINM, 3 Value Min Typ Max 0 — VDDA_SD VRH_SD/GAIN Unit V V VINM = VRL_SD Single ended ±0.5*VRH_SD VINM = 0.5*VRH_SD GAIN = 1 Single ended ±VRH_SD/GAIN VINM = 0.5*VRH_SD GAIN = 2,4,8,16 Differential ±VRH_SD/GAIN 0 < VIN < VDDEx fADCD_M SD clock fADCD_S — frequency4 — 4 14.4 16 MHz Conversion rate — — — 333 Ksps Oversampling ratio Internal modulator 24 — 256 — RESOLUTION SD register resolution5 2's complement notation 16 bit Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 25 Electrical characteristics Table 18. SDADC electrical specifications (continued) Symbol Parameter Conditions GAIN ADC gain |δGAIN| Absolute value of the ADC gain error6, 7 Value Unit Min Typ Max Defined through SDADC_MCR[PGAN]. Only integer powers of 2 are valid gain values. 1 — 16 — Before calibration (applies to gain setting = 1) — — 1.5 % After calibration — — 5 mV — — 7.5 — — 10 Before calibration (applies to all gain settings: 1, 2, 4, 8, 16) — 10*(1+1/ gain) 20 After calibration — — 5 — — 7.5 — — 10 80 — — 77 — — 74 — — 71 — — 68 — — ΔVRH_SD < 5%, ΔVDDA_SD < 10% ΔTJ < 50 °C After calibration ΔVRH_SD < 5%, ΔVDDA_SD < 10% ΔTJ < 100 °C After calibration ΔVRH_SD < 5%, ΔVDDA_SD < 10% ΔTJ < 150 °C VOFFSET Conversion offset6, 7 mV ΔVDDA_SD < 10% ΔTJ < 50 °C After calibration ΔVDDA_SD < 10% ΔTJ < 100 °C After calibration ΔVDDA_SD < 10% ΔTJ < 150 °C SNRDIFF150 Signal to noise ratio in 4.5 V < VDDA_SD < 5.5 V, 8, 9 differential mode, 150 VRH_SD = VDDA_SD Ksps output rate GAIN = 1 4.5 V < VDDA_SD < 5.5 V8, 9 dB VRH_SD = VDDA_SD GAIN = 2 4.5 V < VDDA_SD < 5.5 V8, 9 VRH_SD = VDDA_SD GAIN = 4 4.5 V < VDDA_SD < 5.5 V8, 9 VRH_SD = VDDA_SD GAIN = 8 4.5 V < VDDA_SD < 5.5 V8, 9 Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 26 NXP Semiconductors Electrical characteristics Table 18. SDADC electrical specifications (continued) Symbol Parameter Conditions Value Min Typ Max Signal to noise ratio in 4.5 V < VDDA_SD < 5.5 V8, 9 differential mode, 333 VRH_SD = VDDA_SD Ksps output rate GAIN = 1 71 — — 4.5 V < VDDA_SD < 5.5 V8, 9 70 — — 68 — — 65 — — 62 — — Signal to noise ratio in 4.5 V < VDDA_SD < 5.5 V8, 9 single ended mode, VRH_SD = VDDA_SD 150 Ksps output rate GAIN = 1 72 — — 4.5 V < VDDA_SD < 5.5 V8, 9 69 — — 66 — — 62 — — 54 — — 72 — — 72 — — Unit VRH_SD = VDDA_SD GAIN = 16 SNRDIFF333 dB VRH_SD = VDDA_SD GAIN = 2 4.5 V < VDDA_SD < 5.5 V8, 9 VRH_SD = VDDA_SD GAIN = 4 4.5 V < VDDA_SD < 5.5 V8, 9 VRH_SD = VDDA_SD GAIN = 8 4.5 V < VDDA_SD < 5.5 V8, 9 VRH_SD = VDDA_SD GAIN = 16 SNRSE150 dB VRH_SD = VDDA_SD GAIN = 2 4.5 V < VDDA_SD < 5.5 V8, 9 VRH_SD = VDDA_SD GAIN = 4 4.5 V < VDDA_SD < 5.5 V8, 9 VRH_SD = VDDA_SD GAIN = 8 4.5 V < VDDA_SD < 5.5 V8, 9 VRH_SD = VDDA_SD GAIN = 16 SINADDIFF150 Signal to noise and distortion ratio in differential mode, 150 Ksps output rate Gain = 1 dBFS 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 2 4.5 V < VDDA_SD < 5.5 V Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 27 Electrical characteristics Table 18. SDADC electrical specifications (continued) Symbol Parameter Value Conditions Min Typ Max 69 — — 68.8 — — 64.8 — — 66 — — 66 — — 63 — — 62 — — 59 — — 66 — — 66 — — 63 — — 62 — — Unit VRH_SD = VDDA_SD Gain = 4 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 8 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 16 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD SINADDIFF333 Signal to noise and distortion ratio in differential mode, 333 Ksps output rate Gain = 1 dBFS 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 2 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 4 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 8 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 16 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD SINADSE150 Signal to noise and distortion ratio in single-ended mode, 150 Ksps output rate Gain = 1 dBFS 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 2 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 4 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 8 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 28 NXP Semiconductors Electrical characteristics Table 18. SDADC electrical specifications (continued) Symbol Parameter Conditions Gain = 16 Value Min Typ Max 54 — — 65 — — 68 — — 74 — — 80 — — 80 — — 65 — — 68 — — 74 — — 80 — — 80 — — 68 — — 68 — — Unit 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD THDDIFF150 Total harmonic Gain = 1 distortion in differential 4.5 V < VDDA_SD < 5.5 V mode, 150 Ksps VRH_SD = VDDA_SD output rate Gain = 2 dBFS 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 4 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 8 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 16 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD THDDIFF333 Total harmonic Gain = 1 distortion in differential 4.5 V < VDDA_SD < 5.5 V mode, 333 Ksps VRH_SD = VDDA_SD output rate Gain = 2 dBFS 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 4 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 8 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 16 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD THDSE150 Total harmonic distortion in singleended mode, 150 Ksps output rate Gain = 1 dBFS 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 2 Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 29 Electrical characteristics Table 18. SDADC electrical specifications (continued) Symbol Parameter Value Conditions Unit Min Typ Max 66 — — 68 — — 68 — — 60 — — dB GAIN = 1 1000 1250 1500 kΩ GAIN = 2 600 800 1000 GAIN = 4 300 400 500 GAIN = 8 200 250 300 GAIN = 16 200 250 300 GAIN = 1 1400 1800 2200 GAIN = 2 1000 1300 1600 GAIN = 4 700 950 1150 GAIN = 8 500 650 800 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 4 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 8 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 16 4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD SFDR Spurious free dynamic Any GAIN range ZDIFF Differential input impedance10, 11 ZCM Common Mode input impedance11, 12 kΩ GAIN = 16 500 650 800 RBIAS Bare bias resistance — 110 144 180 kΩ ΔVINTCM Common Mode input reference voltage13 — –12 — +12 % VBIAS Bias voltage — — VRH_SD/2 — V δVBIAS Bias voltage accuracy — –2.5 — +2.5 % CMRR Common mode rejection ratio — 20 — — dB RCaaf Anti-aliasing filter External series resistance — — 20 kΩ Filter capacitances 220 — — pF fPASSBAND band9 — 0.01 — 0.333 * fADCD_S kHz –1 — 1 % Stop band attenuation [0.5 * fADCD_S, 1.0 * fADCD_S] 40 — — dB [1.0 * fADCD_S, 1.5 * fADCD_S] 45 — — [1.5 * fADCD_S, 2.0 * fADCD_S] 50 — — [2.0 * fADCD_S, 2.5 * fADCD_S] 55 — — [2.5 * fADCD_S, fADCD_M/2] 60 — — δRIPPLE Frolloff Pass Pass band ripple14 0.333 * fADCD_S Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 30 NXP Semiconductors Electrical characteristics Table 18. SDADC electrical specifications (continued) Symbol Parameter Conditions δGROUP Group delay Value Typ Max Within pass band: Tclk is 2/fADCD_M — — — — OSR = 24 — — 235.5 Tclk OSR = 28 — — 275 OSR = 32 — — 314.5 OSR = 36 — — 354 OSR = 40 — — 393.5 OSR = 44 — — 433 OSR = 48 — — 472.5 OSR = 56 — — 551.5 OSR = 64 — — 630.5 OSR = 72 — — 709.5 OSR = 75 — — 696 OSR = 80 — — 788.5 OSR = 88 — — 867.5 OSR = 96 — — 946.5 OSR = 112 — — 1104.5 OSR = 128 — — 1262.5 OSR = 144 — — 1420.5 OSR = 160 — — 1578.5 OSR = 176 — — 1736.5 OSR = 192 — — 1894.5 OSR = 224 — — 2210.5 — — 2526.5 –0.5/ — +0.5/ fADCD_S — OSR = 256 Distortion within pass band fADCD_S fHIGH Unit Min High pass filter 3 dB frequency Enabled — 10e–5* fADCD_S — — tSTARTUP Startup time from power down state — — — 100 μs tLATENCY Latency between input HPF = ON data and converted data when input mux HPF = OFF does not change15 — — δGROUP + fADCD_S — — — δGROUP Settling time after mux Analog inputs are muxed change HPF = ON — — 2*δGROUP + 3*fADCD_S HPF = OFF — — 2*δGROUP + 2*fADCD_S After input comes within range from saturation — — 2*δGROUP + fADCD_S — — 2*δGROUP tSETTLING tODRECOVERY Overdrive recovery time — — HPF = ON HPF = OFF Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 31 Electrical characteristics Table 18. SDADC electrical specifications (continued) Symbol Parameter Conditions SDADC sampling capacitance after sampling switch16 Value Unit Min Typ Max GAIN = 1, 2, 4, 8 — — 75*GAIN fF GAIN = 16 — — 600 fF Bias consumption At least one SDADC enabled — — 3.5 mA IADV_D SDADC supply consumption Per SDADC enabled — — 4.325 mA IADR_D SDADC reference current consumption Per SDADC enabled — — 20 μA CS_D IBIAS 1. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the signal will only be “clipped.” 2. VINP is the input voltage applied to the positive terminal of the SDADC 3. VINM is the input voltage applied to the negative terminal of the SDADC 4. Sampling is generated internally fSAMPLING = fADCD_M/2 5. For Gain = 16, SDADC resolution is 15 bit. 6. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*VRH_SD for differential mode and single ended mode with negative input = 0.5*VRH_SD. Offset Calibration should be done with respect to 0 for single ended mode with negative input = 0. Both Offset and Gain Calibration is guaranteed for +/–5% variation of VRH_SD, +/–10% variation of VDDA_SD, +/–50 C temperature variation. 7. Offset and gain error due to temperature drift can occur in either direction (+/–) for each of the SDADCs on the device. 8. SDADC is functional in the range 3.6 V < VDDA_SD < 4.0 V: SNR parameter degrades by 3 dB. SDADC is functional in the range 3.0 V < VRH_SD < 4.0 V: SNR parameter degrades by 9 dB. 9. SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the frequency range of fADCD_M – fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency and fADCD_S is the output sample frequency. A proper external input filter should be used to remove any interfering signals in this frequency range. 10. Input impedance in differential mode ZIN = ZDIFF 11. Input impedance given at fADCD_M = 16 MHz. Impedance is inversely proportional to SDADC clock frequency. ZDIFF (fADCD_M) = (16 MHz / fADCD_M) * ZDIFF, ZCM (fADCD_M) = (16 MHz / fADCD_M) * ZCM. 12. Input impedance in single-ended mode ZIN = (2 * ZDIFF * ZCM) / (ZDIFF + ZCM) 13. VINTCM is the Common Mode input reference voltage for the SDADC. It has a nominal value of (VRH_SD - VRL_SD) / 2. 14. The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB. 15. Propagation of the information from the pin to the register CDR[CDATA] and the flags SFR[DFEF] and SFR[DFFF] is given by the different modules that must be crossed: delta/sigma filters, high pass filter, FIFO module, and clock domain synchronizers. The time elapsed between data availability at the pin and internal SDADC module registers is given by the following formula, where fADCD_S is the after decimation ADC output data rate, fADCD_M/2 is the modulator sampling rate and fFM_PER_CLK is the frequency of the peripheral bridge clock feeds to the ADC S/D module. REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)/fFM_PER_CLK The (~+1) symbol refers to the number of clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the signal during clock domain crossing. Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received from the SDADC module. 16. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before sampling switch. 3.9 Temperature Sensor The following table describes the Temperature Sensor electrical characteristics. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 32 NXP Semiconductors Electrical characteristics Table 19. Temperature Sensor electrical characteristics Symbol — Parameter Conditions Value Min Typ Max Unit Temperature monitoring range — –40 — 150 °C TSENS Sensitivity — — 5.18 — mV/°C TACC Accuracy –40°C < TJ < 150°C –5 — 5 °C VDDA_EQA power supply current, per Temp Sensor — — — 700 μA ITEMP_SENS 3.10 LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical characteristics The LFAST pad electrical characteristics apply to the SIPI interface on the chip. The same LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces, with different characteristics given in the following tables. 3.10.1 LFAST interface timing diagrams MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 33 Electrical characteristics Signal excursions above this level NOT allowed 1743 mV Max. common mode input at RX 1600 mV |Vo D| Max Differential Voltage = 285 mV p-p (LFAST) 400 mV p-p (MSC/DSPI) Minimum Data Bit Time Opening = 0.55 * T (LFAST) 0.50 * T (MSC/DSPI) “No-Go” Area VOS = 1.2 V +/- 10% TX common mode |Vo D| Min Differential Voltage = 100 mV p-p (LFAST) 150 mV p-p (MSC/DSPI) VICOM |PER EYE |PER EYE Data Bit Period T = 1 /FDATA Min. common mode input at RX Signal excursions below this level NOT allowed 150 mV 0V Figure 8. LFAST and MSC/DSPI LVDS timing definition MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 34 NXP Semiconductors Electrical characteristics H lfast_pwr_down L tPD2NM_TX Differential Data Lines TX pad_p/pad_n Data Valid Figure 9. Power-down exit time VIH Differential Data Lines TX 90% 10% pad_p/pad_n VIL tTR tTR Figure 10. Rise/fall time 3.10.2 LFAST and MSC/DSPI LVDS interface electrical characteristics The following table contains the electrical characteristics for the LFAST interface. Table 20. LVDS pad startup and receiver electrical characteristics1 Symbol Parameter Conditions Value Min Typ Max — 0.5 4 Unit STARTUP2,3 tSTRT_BIAS Bias current reference startup time4 — μs Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 35 Electrical characteristics Table 20. LVDS pad startup and receiver electrical characteristics1 (continued) Symbol Parameter Value Conditions Min Typ Max Unit tPD2NM_TX Transmitter startup time (power down to — Normal mode)5 — 0.4 2.75 μs tSM2NM_TX Transmitter startup time (Sleep mode to Not applicable to the MSC/DSPI Normal mode)6 LVDS pad — 0.2 0.5 μs tPD2NM_RX Receiver startup time (power down to Normal mode)7 — — 20 40 ns tPD2SM_RX Receiver startup time (power down to Sleep mode)8 Not applicable to the MSC/DSPI LVDS pad — 20 50 ns ILVDS_BIAS LVDS bias current consumption Tx or Rx enabled — — 0.95 mA 47.5 50 52.5 Ω 95 100 105 Ω TRANSMISSION LINE CHARACTERISTICS (PCB Track) Z0 ZDIFF Transmission line characteristic impedance — Transmission line differential impedance — RECEIVER VICOM Common mode voltage — 0.159 — 1.610 V |ΔVI| Differential input voltage — 100 — — mV VHYS Input hysteresis — 25 — — mV VDDEH = 3.0 V to 5.5 V 80 125 150 Ω — — 3.5 6.0 pF Enabled — — 0.5 mA RIN CIN ILVDS_RX Terminating resistance Differential input capacitance11 Receiver DC current consumption 1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST and the MSC/DSPI LVDS pad except where noted in the conditions. 2. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS control registers (LCR) of the LFAST and High-Speed Debug modules. 3. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter electrical characteristic tables. 4. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being enabled. 5. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock periods. 6. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode. 7. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods. 8. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode. 9. Absolute min = 0.15 V – (285 mV/2) = 0 V 10. Absolute max = 1.6 V + (285 mV/2) = 1.743 V 11. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions. For bare die devices, subtract the package value given in Figure 1. Table 21. LFAST transmitter electrical characteristics1 Symbol fDATA Parameter Data rate Conditions — Value Min Typ Max — — 240 Unit Mbps Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 36 NXP Semiconductors Electrical characteristics Table 21. LFAST transmitter electrical characteristics1 (continued) Symbol Parameter Conditions Value Min Typ Max Unit VOS Common mode voltage — 1.08 — 1.32 V |VOD| Differential output voltage swing (terminated)2,3 — 110 200 285 mV Rise/fall time (10% – 90% of swing)2,3 — 0.26 — 1.5 ns VDDE = 4.5 V — — 12.0 pF VDDE = 3.0 V — — 8.5 Enabled — — 3.2 tTR CL ILVDS_TX External lumped differential load capacitance2 Transmitter DC current consumption mA 1. The LFAST pad electrical characteristics are based on worst-case internal capacitance values shown in Figure 1. 2. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in Figure 1. 3. Valid for maximum external load CL. Table 22. MSC/DSPI LVDS transmitter electrical characteristics1 Symbol Parameter Conditions Value Min Typ Max Unit fDATA Data rate — — — 80 Mbps VOS Common mode voltage — 1.08 — 1.32 V |VOD| Differential output voltage swing (terminated)2,3 — 150 200 400 mV — 0.8 — 4.0 ns VDDE = 4.5 V — — 50 pF VDDE = 3.0 V — — 39 Enabled — — 4.0 tTR CL ILVDS_TX Rise/Fall time (10%–90% of swing)2,3 External lumped differential load capacitance2 Transmitter DC current consumption mA 1. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst-case internal capacitance values given in Figure 1. 2. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in Figure 1. 3. Valid for maximum external load CL. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 37 Electrical characteristics bond pad GPIO Driver CL 1pF 2.5pF 100Ω terminator LVDS Driver bond pad GPIO Driver CL 1pF 2.5pF Package Die PCB Figure 11. LVDS pad external load diagram 3.10.3 LFAST PLL electrical characteristics The following table contains the electrical characteristics for the LFAST PLL. Table 23. LFAST PLL electrical characteristics1 Symbol fRF_REF Parameter Conditions PN Unit Min Nominal Max — 10 — 26 MHz — –1 — 1 % — 45 — 55 % Integrated phase noise (single side band) fRF_REF = 20 MHz — — –58 dBc fRF_REF = 10 MHz — — –64 PLL reference clock frequency ERRREF PLL reference clock frequency error DCREF Value PLL reference clock duty cycle fVCO PLL VCO frequency — — 4802 — MHz tLOCK PLL phase lock3 — — — 40 μs — — 300 ps ΔPERREF Input reference clock jitter (peak to peak) Single period, fRF_REF = 10 MHz Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 38 NXP Semiconductors Electrical characteristics Table 23. LFAST PLL electrical characteristics1 (continued) Symbol Parameter Conditions Long term, fRF_REF = 10 MHz ΔPEREYE Output Eye Jitter (peak to peak)4 — Value Min Nominal Max –500 — 500 — — 400 Unit ps 1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces. 2. The 480 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 13 MHz or 26 MHz reference, the VCO frequency is 468 MHz. 3. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device. 4. Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. See Figure 1. 3.11 Power management: PMC, POR/LVD, power sequencing 3.11.1 Power management electrical characteristics The power management module monitors the different power supplies. It also generates the internal supplies that are required for correct device functionality. The power management is supplied by the VDDPMC supply. 3.11.1.1 LDO mode recommended power transistors Only specific orderable part numbers of MPC5777C support LDO regulation mode. See Ordering information for MPC5777C parts that support this regulation mode. The following NPN transistors are recommended for use with the on-chip LDO voltage regulator controller: ON Semiconductor™ NJD2873. The collector of the external transistor is preferably connected to the same voltage supply source as the output stage of the regulator. The following table describes the characteristics of the power transistors. Table 24. Recommended operating characteristics Symbol Parameter Value Unit 60-550 — hFE DC current gain (Beta) PD Absolute minimum power dissipation 1.60 W ICMaxDC Maximum DC collector current 2.0 A VCESAT Collector to emitter saturation voltage 300 mV Base to emitter voltage 0.95 V Minimum voltage at transistor collector 2.5 V VBE Vc MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 39 Electrical characteristics The following table shows the recommended components to be used in LDO regulation mode. Table 25. Recommended operating characteristics Part name Part type Nominal Description Q1 NPN BJT hFE = 400 NJD2873: ON Semiconductor LDO voltage regulator controller (VRC) CI Capacitor 4.7 µF - 20 V Ceramic capacitor, total ESR < 70 mΩ CE Capacitor 0.047–0.049 µF - 7 V Ceramic—one capacitor for each VDD pin CV Capacitor 22 µF - 20 V Ceramic VDDPMC (optional 0.1 µF) CD Capacitor 22 µF - 20 V Ceramic supply decoupling capacitor, ESR < 50 mΩ (as close as possible to NPN collector) CB Capacitor 0.1 µF - 7 V Ceramic VDDPWR R Resistor Application specific Optional; reduces thermal loading on the NPN with high VDDPMC levels The following diagram shows the LDO configuration connection. VDDPMC REGSEL CD R CV VSSPMC (clean ground) VDDPWR Q1 REGCTL CB VSSPWR VDD CI CE VSS Figure 12. VRC 1.2 V LDO configuration 3.11.1.2 SMPS mode recommended external components and characteristics The following table shows the recommended components to be used in SMPS regulation mode. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 40 NXP Semiconductors Electrical characteristics Table 26. Recommended operating characteristics Part name Part type Nominal Description Q1 p-MOS 3 A - 20 V SQ2301ES / FDC642P or equivalent: low threshold p-MOS, Vth < 2.0 V, Rdson @ 4.5 V < 100 mΩ, Cg < 5 nF D1 Schottky 2 A - 20 V SS8P3L or equivalent: Vishay™ low Vf Schottky diode L Inductor 3-4 μH - 1.5 A Buck shielded coil low ESR CI Capacitor 22 μF - 20 V Ceramic capacitor, total ESR < 70 mΩ CE Capacitor 0.1 μF - 7 V Ceramic—one capacitor for each VDD pin CV Capacitor 22 μF - 20 V Ceramic VDDPMC (optional 0.1 μF capacitor in parallel) CD Capacitor 22 μF - 20 V Ceramic supply decoupling capacitor, ESR < 50 mΩ (as close as possible to the p-MOS source) R Resistor 2.0-4.7 kΩ Pullup for power p-MOS gate CB Capacitor 22 μF - 20 V Ceramic, connect 100 nF capacitor in parallel (as close as possible to package to reduce current loop from VDDPWR to VSSPWR) The following diagram shows the SMPS configuration connection. VDDPMC REGSEL CD CV VSSPMC (clean ground) VDDPWR R REGCTL Q1 CB D1 VSSPWR L VDD CI CE VSS Figure 13. SMPS configuration NOTE The REGSEL pin is tied to VDDPMC to select SMPS. If REGSEL is 0, the chip boots with the linear regulator. See Power sequencing requirements for details about VDDPMC and VDDPWR. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 41 Electrical characteristics The SMPS regulator characteristics appear in the following table. Table 27. SMPS electrical characteristics Symbol Parameter Value Conditions Min Typ Max Unit SMPSCLOCK SMPS oscillator frequency Trimmed 825 1000 1220 kHz SMPSSLOPE SMPS soft-start ramp slope — 0.01 0.025 0.05 V/μs SMPS typical efficiency — — 70 — % SMPSEFF 3.11.2 Power management integration To ensure correct functionality of the device, use the following recommended integration scheme for LDO mode. C HV_PMC C SMPSPWR VDDFLA VDDPMC VDDPWR VSS C HV_FLA VDD n x C LV VSSPWR 1 VSS MPC5777C REF BYPC VDDE(H)x C REFEQ 2 VSSA_EQ VDDA_EQB VSS C HV_ADC_EQB VDDA_EQA VSSA_SD VSSA_EQ C HV_ADC_EQA 1 One capacitance near each VDD pin 2 One capacitance near each VDDE(H)x pin C HV_ADC_D VSS VDDA_SD n x C HV_IO Figure 14. Recommended supply pin circuits MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 42 NXP Semiconductors Electrical characteristics The following table describes the supply stability capacitances required on the device for proper operation. Table 28. Device power supply integration Symbol CLV CSMPSPWR CHV_PMC CHV_IO CHV_FLA Parameter Minimum VDD external bulk capacitance, 2, 3 Minimum SMPS driver supply capacitance Minimum VDDPMC external bulk Minimum VDDEx/VDDEHx external Minimum VDD_FLA external CREFEQ capacitance2 capacitance7 CHV_ADC_EQA/B Minimum VDDA_EQA/B external CHV_ADC_SD capacitance4, 5 Conditions Value1 Min LDO mode 4.7 SMPS mode 22 — 22 LDO mode 22 SMPS mode 22 — Typ Max — Unit — μF — μF — — μF — — μF — — μF — 4.76 — μF — — 1.0 2.0 — μF capacitance8 — 0.01 — — μF capacitance9 — 0.01 — — μF — 1.0 2.2 — μF Minimum REFBYPCA/B external Minimum VDDA_SD external capacitance10 1. 2. 3. 4. 5. 6. See Figure 1 for capacitor integration. Recommended X7R or X5R ceramic low ESR capacitors, ±15% variation over process, voltage, temperature, and aging. Each VDD pin requires both a 47 nF and a 0.01 μF capacitor for high-frequency bypass and EMC requirements. Recommended X7R or X5R ceramic low ESR capacitors, ±15% variation over process, voltage, temperature, and aging. Each VDDPMC pin requires both a 47 nF and a 0.01 μF capacitor for high-frequency bypass and EMC requirements. The actual capacitance should be selected based on the I/O usage in order to keep the supply voltage within its operating range. 7. The recommended flash regulator composition capacitor is 2.0 μF typical X7R or X5R, with -50% and +35% as min and max. This puts the min cap at 0.75 μF. 8. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 μF between VDDA_EQA/B and VSSA_EQ. 9. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 μF between REFBYPCA/B and VSS. 10. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 μF between VDDA_SD and VSSA_SD. 3.11.3 Device voltage monitoring The LVD/HVDs for the device and their levels are given in the following table. Voltage monitoring threshold definition is provided in the following figure. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 43 Electrical characteristics V DD_xxx V HVD(rise) V HVD(fall) V LVD(rise) V LVD(fall) t VDASSERT t VDRELEASE HVD TRIGGER (INTERNAL) t VDRELEASE t VDASSERT LVD TRIGGER (INTERNAL) Figure 15. Voltage monitor threshold definition Table 29. Voltage monitor electrical characteristics1, 2 Configuration Symbol POR098_c3 Parameter LV internal supply power on reset LVD_core_hot LV internal4 supply low voltage monitoring external5 LVD_core_cold LV supply low voltage monitoring HVD_core LV internal cold supply high voltage monitoring Conditions Rising voltage (powerup) Trim bits N/A Mask Pow. Opt. Up No Enab. Value Min Typ Max 960 1010 1060 940 990 1040 Enab. 1100 1140 1183 Falling voltage (untrimmed) 1080 1120 1163 Rising voltage (trimmed) 1142 1165 1183 Falling voltage (trimmed) 1122 1145 1163 Disab. 1165 1180 1198 1136 1160 1178 Disab. 1338 1365 1385 1318 1345 1365 Falling voltage (power down) Rising voltage (untrimmed) Rising voltage 4bit 4bit No Yes Falling voltage Rising voltage 4bit Yes Falling voltage Unit mV mV mV mV Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 44 NXP Semiconductors Electrical characteristics Table 29. Voltage monitor electrical characteristics1, 2 (continued) Configuration Symbol POR_HV LVD_HV HVD_HV LVD_FLASH HVD_FLASH LVD_IO Parameter HV VDDPMC supply power on reset threshold Conditions Trim bits Mask Pow. Opt. Up Value Min Typ Max Enab. 2444 2600 2756 2424 2580 2736 Enab. 2935 3023 3112 2922 3010 3099 Rising voltage (trimmed) 2946 3010 3066 Falling voltage (trimmed) 2934 2998 3044 Disab. 5696 5860 5968 5666 5830 5938 Enab. 2935 3023 3112 2922 3010 3099 Rising voltage (trimmed) 2956 3010 3053 Falling voltage (trimmed) 2944 2998 3041 Disab. 3456 3530 3584 3426 3500 3554 Enab. 3250 3350 3488 Falling voltage (untrimmed) 3220 3320 3458 Rising voltage (trimmed) 3347 3420 3468 Falling voltage (trimmed) 3317 3390 3438 Rising voltage (powerup) N/A No Falling voltage (power down) HV internal VDDPMC supply Rising voltage (untrimmed) low voltage monitoring Falling voltage (untrimmed) 4bit HV internal VDDPMC supply Rising voltage high voltage monitoring Falling voltage 4bit FLASH supply low voltage Rising voltage (untrimmed) monitoring6 Falling voltage (untrimmed) 4bit FLASH supply high voltage monitoring6 Rising voltage Main I/O VDDEH1 supply low voltage monitoring Rising voltage (untrimmed) 4bit No Yes No Yes Falling voltage 4bit No Unit mV mV mV mV mV mV tVDASSERT Voltage detector threshold — crossing assertion — — — 0.1 — 2.0 μs tVDRELEASE Voltage detector threshold — crossing de-assertion — — — 5 — 20 μs 1. LVD is released after tVDRELEASE temporization when upper threshold is crossed; LVD is asserted tVDASSERT after detection when lower threshold is crossed. 2. HVD is released after tVDRELEASE temporization when lower threshold is crossed; HVD is asserted tVDASSERT after detection when upper threshold is crossed. 3. POR098_c threshold is an untrimmed value, before the completion of the power-up sequence. All other LVD/HVD thresholds are provided after trimming. 4. LV internal supply levels are measured on device internal supply grid after internal voltage drop. 5. LV external supply levels are measured on the die side of the package bond wire after package voltage drop. 6. VDDFLA range is guaranteed when internal flash memory regulator is used. 3.11.4 Power sequencing requirements Requirements for power sequencing include the following. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 45 Electrical characteristics NOTE In these descriptions, star route layout means a track split as close as possible to the power supply source. Each of the split tracks is routed individually to the intended end connection. 1. For both LDO mode and SMPS mode, VDDPMC and VDDPWR must be connected together (shorted) to ensure aligned voltage ramping up/down. In addition: • For SMPS mode, a star route layout of the power track is required to minimize mutual noise. If SMPS mode is not used, the star route layout is not required. VDDPWR is the supply pin for the SMPS circuitry. • For 3.3 V operation, VDDFLA must also be star routed and shorted to VDDPWR and VDDPMC. This triple connection is required because 3.3 V does not guarantee correct functionality of the internal VDDFLA regulator. Consequently, VDDFLA is supplied externally. 2. VDDA_MISC: IRC operation is required to provide the clock for chip startup. • The VDDPMC, VDD, and VDDEH1 (reset pin pad segment) supplies are monitored. They hold IRC until all of them reach operational voltage. In other words, VDDA_MISC must reach its specified minimum operating voltage before or at the same time that all of these monitored voltages reach their respective specified minimum voltages. • An alternative is to connect the same supply voltage to both VDDEH1 and VDDA_MISC. This alternative approach requires a star route layout to minimize mutual noise. 3. Multiple VDDEx supplies can be powered up in any order. During any time when VDD is powered up but VDDEx is not yet powered up: pad outputs are unpowered. During any time when VDDEx is powered up before all other supplies: all pad output buffers are tristated. 4. Ramp up VDDA_EQ before VDD. Otherwise, a reset might occur. 5. When the device is powering down while using the internal SMPS regulator, VDDPMC and VDDPWR supplies must ramp down through the voltage range from 2.5 V to 1.5 V in less than 1 second. Slower ramp-down times might result in reduced lifetime reliability of the device. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 46 NXP Semiconductors Electrical characteristics 3.12 Flash memory specifications 3.12.1 Flash memory program and erase specifications NOTE All timing, voltage, and current numbers specified in this section are defined for a single embedded flash memory within an SoC, and represent average currents for given supplies and operations. Table 30 shows the estimated Program/Erase times. Table 30. Flash memory program and erase specifications Characteristic1 Symbol Typ2 Factory Programming3, 4 Field Update Initial Max Initial Max, Full Temp Typical End of Life5 20°C ≤TA ≤30°C -40°C ≤TJ ≤150°C -40°C ≤TJ ≤150°C Unit Lifetime Max6 ≤ 1,000 cycles ≤ 250,000 cycles tdwpgm Doubleword (64 bits) program time 43 100 150 55 500 μs tppgm Page (256 bits) program time 73 200 300 108 500 μs tqppgm Quad-page (1024 bits) program time 268 800 1,200 396 2,000 μs t16kers 16 KB Block erase time 168 290 320 250 1,000 ms t16kpgm 16 KB Block program time 34 45 50 40 1,000 ms t32kers 32 KB Block erase time 217 360 390 310 1,200 ms t32kpgm 32 KB Block program time 69 100 110 90 1,200 ms t64kers 64 KB Block erase time 315 490 590 420 1,600 ms t64kpgm 64 KB Block program time 138 180 210 170 1,600 ms t256kers 256 KB Block erase time 884 1,520 2,030 1,080 4,000 — ms t256kpgm 256 KB Block program time 552 720 880 650 4,000 — ms 1. Program times are actual hardware programming times and do not include software overhead. Block program times assume quad-page programming. 2. Typical program and erase times represent the median performance and assume nominal supply values and operation at 25 °C. Typical program and erase times may be used for throughput calculations. 3. Conditions: ≤ 150 cycles, nominal voltage. 4. Plant Programing times provide guidance for timeout limits used in the factory. 5. Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical End of Life program and erase values may be used for throughput calculations. 6. Conditions: -40°C ≤ TJ ≤ 150°C, full spec voltage. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 47 Electrical characteristics 3.12.2 Flash memory Array Integrity and Margin Read specifications Table 31. Flash memory Array Integrity and Margin Read specifications Symbol Characteristic Min Typical Max1 Units tai16kseq Array Integrity time for sequential sequence on 16 KB block. — — 512 x Tperiod x Nread — tai32kseq Array Integrity time for sequential sequence on 32 KB block. — — 1024 x Tperiod x Nread — tai64kseq Array Integrity time for sequential sequence on 64 KB block. — — 2048 x Tperiod x Nread — tai256kseq Array Integrity time for sequential sequence on 256 KB block. — — 8192 x Tperiod x Nread — tmr16kseq Margin Read time for sequential sequence on 16 KB block. 73.81 — 110.7 μs tmr32kseq Margin Read time for sequential sequence on 32 KB block. 128.43 — 192.6 μs tmr64kseq Margin Read time for sequential sequence on 64 KB block. 237.65 — 356.5 μs tmr256kseq Margin Read time for sequential sequence on 256 KB block. 893.01 — 1,339.5 μs 2 1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires 6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the address pipeline set to 2, Nread would equal 4 (or 6 - 2).) 2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the equation, the results of the equation are also unit accurate. 3.12.3 Flash memory module life specifications Table 32. Flash memory module life specifications Symbol Array P/E cycles Data retention Characteristic Conditions Min Typical Units Number of program/erase cycles per block for 16 KB, 32 KB and 64 KB blocks.1 — 250,000 — P/E cycles Number of program/erase cycles per block for 256 KB blocks.2 — 1,000 250,000 P/E cycles Minimum data retention. Blocks with 0 - 1,000 P/E cycles. 50 — Years Blocks with 100,000 P/E cycles. 20 — Years Blocks with 250,000 P/E cycles. 10 — Years 1. Program and erase supported across standard temperature specs. 2. Program and erase supported across standard temperature specs. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 48 NXP Semiconductors Electrical characteristics 3.12.4 Data retention vs program/erase cycles Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the qualification limits. 3.12.5 Flash memory AC timing specifications Table 33. Flash memory AC timing specifications Symbol tpsus tesus tres Characteristic Min Typical Max Units Time from setting the MCR-PSUS bit until MCR-DONE bit is set to a 1. — 9.4 11.5 μs plus four system clock periods plus four system clock periods Time from setting the MCR-ESUS bit until MCR-DONE bit is set to a 1. — 16 20.8 plus four system clock periods plus four system clock periods Time from clearing the MCR-ESUS or PSUS bit with EHV = 1 until DONE goes low. — — 100 μs ns Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 49 Electrical characteristics Table 33. Flash memory AC timing specifications (continued) Symbol Characteristic Min Typical Max Units tdone Time from 0 to 1 transition on the MCR-EHV bit initiating a program/erase until the MCR-DONE bit is cleared. — — 5 ns tdones Time from 1 to 0 transition on the MCR-EHV bit aborting a program/erase until the MCR-DONE bit is set to a 1. — 16 20.8 μs plus four system clock periods plus four system clock periods Time to recover once exiting low power mode. 16 — 45 tdrcv plus seven system clock periods. μs plus seven system clock periods taistart Time from 0 to 1 transition of UT0-AIE initiating a Margin Read or Array Integrity until the UT0-AID bit is cleared. This time also applies to the resuming from a suspend or breakpoint by clearing AISUS or clearing NAIBP — — 5 ns taistop Time from 1 to 0 transition of UT0-AIE initiating an Array Integrity abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Array Integrity suspend request. — — 80 ns Time from 1 to 0 transition of UT0-AIE initiating a Margin Read abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Margin Read suspend request. 10.36 tmrstop plus fifteen system clock periods — plus four system clock periods 20.42 μs plus four system clock periods 3.12.6 Flash memory read wait-state and address-pipeline control settings The following table describes the recommended settings of the Flash Memory Controller's PFCR1[RWSC] and PFCR1[APC] fields at various flash memory operating frequencies, based on specified intrinsic flash memory access times of the C55FMC array at 150°C. Table 34. Flash memory read wait-state and address-pipeline control combinations Flash memory frequency RWSC APC Flash memory read latency on mini-cache miss (# of fPLATF clock periods) Flash memory read latency on mini-cache hit (# of fPLATF clock periods) 0 MHz < fPLATF ≤ 33 MHz 0 0 3 1 33 MHz < fPLATF ≤ 100 MHz 2 1 5 1 100 MHz < fPLATF ≤ 153 MHz 3 1 6 1 MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 50 NXP Semiconductors Electrical characteristics 3.13 AC timing 3.13.1 Generic timing diagrams The generic timing diagrams in Figure 16 and Figure 17 apply to all I/O pins with pad types SR and FC. See the associated MPC5777C Microsoft Excel® file in the Reference Manual for the pad type for each pin. D_CLKOUT VDDE / 2 A B VDDEn / 2 VDDEHn / 2 I/O Outputs A – Maximum Output Delay Time B – Minimum Output Hold Time Figure 16. Generic output delay/hold timing D_CLKOUT VDDE / 2 B A I/O Inputs VDDEn / 2 VDDEHn / 2 A – Maximum Input Delay Time B – Minimum Input Hold Time Figure 17. Generic input setup/hold timing MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 51 Electrical characteristics 3.13.2 Reset and configuration pin timing Table 35. Reset and configuration pin timing1 Spec Characteristic Symbol Min Max Unit 1 RESET Pulse Width tRPW 10 — tcyc, 2 2 RESET Glitch Detect Pulse Width tGPW 2 — tcyc2 3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid tRCSU 10 — tcyc2 4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid tRCH 0 — tcyc2 1. Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA = TL to TH. 2. For further information on tcyc, see Table 1. 2 RESET 1 RSTOUT 3 PLLCFG BOOTCFG WKPCFG 4 Figure 18. Reset and configuration pin timing 3.13.3 IEEE 1149.1 interface timing Table 36. JTAG pin AC electrical characteristics1 # Symbol 1 tJCYC 2 tJDC 3 tTCKRISE Characteristic Value Unit Min Max TCK cycle time 100 — ns TCK clock pulse width 40 60 % TCK rise and fall times (40%–70%) — 3 ns 4 tTMSS, tTDIS TMS, TDI data setup time 5 — ns 5 tTMSH, tTDIH TMS, TDI data hold time 5 — ns 6 tTDOV TCK low to TDO data valid — 162 ns 7 tTDOI TCK low to TDO data invalid 0 — ns Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 52 NXP Semiconductors Electrical characteristics Table 36. JTAG pin AC electrical characteristics1 (continued) # Symbol 8 tTDOHZ 9 tJCMPPW 10 tJCMPS Value Characteristic Unit Min Max — 15 ns JCOMP assertion time 100 — ns JCOMP setup time to TCK low 40 — ns ns TCK low to TDO high impedance 11 tBSDV TCK falling edge to output valid — 6003 12 tBSDVZ TCK falling edge to output valid out of high impedance — 600 ns 13 tBSDHZ TCK falling edge to output high impedance — 600 ns 14 tBSDST Boundary scan input valid to TCK rising edge 15 — ns 15 tBSDHT TCK rising edge to boundary scan input invalid 15 — ns 1. These specifications apply to JTAG boundary scan only. See Table 1 for functional specifications. 2. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 3. Applies to all pins, limited by pad slew rate. Refer to I/O delay and transition specification and add 20 ns for JTAG delay. TCK 2 3 2 1 3 Figure 19. JTAG test clock input timing MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 53 Electrical characteristics TCK 4 5 TMS, TDI 6 8 7 TDO Figure 20. JTAG test access port timing TCK 10 JCOMP 9 Figure 21. JTAG JCOMP timing MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 54 NXP Semiconductors Electrical characteristics TCK 13 11 Output Signals 12 Output Signals 14 15 Input Signals Figure 22. JTAG boundary scan timing 3.13.4 Nexus timing Table 37. Nexus debug port timing1 Spec Characteristic 1 MCKO Cycle Time 2 MCKO Duty Cycle 3 Min Max Unit tMCYC 2 8 tCYC tMDC 40 60 % tMDOV –0.1 0.2 tMCYC MCKO Low to MSEO Data Valid2 tMSEOV –0.1 0.2 tMCYC 5 MCKO Low to EVTO Data Valid2 tEVTOV –0.1 0.2 tMCYC 6 EVTI Pulse Width tEVTIPW 4.0 — tTCYC 7 EVTO Pulse Width tEVTOPW 1 — tMCYC 8 TCK Cycle Time tTCYC 23 — tCYC 4 MCKO Low to MDO Data Valid2 Symbol Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 55 Electrical characteristics Table 37. Nexus debug port timing1 (continued) Spec 8 Characteristic Absolute minimum TCK cycle time4 (TDO sampled on posedge of TCK) Symbol Min Max Unit tTCYC 405 — ns 205 — tTDC 40 60 % tNTDIS, tNTMSS 8 — ns TNTDIH, tNTMSH 5 — ns tNTDOV 0 18 ns — — — — tNTDOH 1 — ns Absolute minimum TCK cycle time4 (TDO sampled on negedge of TCK) 9 10 TCK Duty Cycle TDI, TMS Data Setup Time6 Time6 11 TDI, TMS Data Hold 12 TCK Low to TDO Data Valid6 13 RDY Valid to MCKO7 14 TDO hold time after TCLK low6 1. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. 2. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the absolute minimum TCK period specification. 4. This value is TDO propagation time plus 2 ns setup time to sampling edge. 5. This may require a maximum clock speed that is less than the maximum functional capability of the design depending on the actual system frequency being used. 6. Applies to TMS pin timing for the bit frame when using the 1149.7 advanced protocol. 7. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly. 1 2 MCKO 3 4 5 MDO MSEO EVTO Output Data Valid 7 EVTI 6 Figure 23. Nexus timings MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 56 NXP Semiconductors Electrical characteristics 8 9 TCK 10 11 TMS, TDI 14 12 TDO Figure 24. Nexus TCK, TDI, TMS, TDO Timing 3.13.5 External Bus Interface (EBI) timing Table 38. Bus operation timing1 Spec Characteristic Symbol 66 MHz (Ext. bus freq.)2, 3 Min Max tC 15.2 — 1 D_CLKOUT Period 2 D_CLKOUT Duty Cycle tCDC 45% 3 D_CLKOUT Rise Time tCRT — 4 D_CLKOUT Fall Time tCFT 5 D_CLKOUT Posedge to Output Signal Invalid or High Z (Hold Time) tCOH Unit Notes ns Signals are measured at 50% VDDE. 55% tC — —4 ns — — —4 ns — 1.0/1.5 — ns Hold time selectable via SIU_ECCR[EBTS] bit: Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 57 Electrical characteristics Table 38. Bus operation timing1 (continued) Spec Characteristic Symbol 66 MHz (Ext. bus freq.)2, 3 Min Max Unit Notes D_ADD[9:30] EBTS = 0: 1.0 ns D_BDIP EBTS = 1: 1.5 ns D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0:3] 6 D_CLKOUT Posedge to Output Signal Valid (Output Delay) tCOV — 8.5/9.0 ns Output valid time selectable via SIU_ECCR[EBTS] bit: D_ADD[9:30] EBTS = 0: 8.5 ns D_BDIP EBTS = 1: 9.0 ns D_CS[0:3] D_DAT[0:15] 11.5 D_OE — 8.5/9.0 Output valid time selectable via SIU_ECCR[EBTS] bit: D_RD_WR EBTS = 0: 8.5 ns D_TA EBTS = 1: 9.0 ns D_TS D_WE[0:3]/D_BE[0:3] 7 Input Signal Valid to D_CLKOUT Posedge (Setup Time) tCIS 7.5 — ns — tCIH 1.0 — ns — D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS 8 D_CLKOUT Posedge to Input Signal Invalid (Hold Time) D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS 9 D_ALE Pulse Width tAPW 6.5 — ns The timing is for Asynchronous external memory system. 10 D_ALE Negated to Address Invalid tAAI 2.0/1.0 5 — ns The timing is for Asynchronous external memory system. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 58 NXP Semiconductors Electrical characteristics Table 38. Bus operation timing1 Spec Characteristic Symbol 66 MHz (Ext. bus freq.)2, 3 Min Max Unit Notes ALE is measured at 50% of VDDE. 1. EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with SIU_PCR[DSC] = 11b for ADDR/CTRL and SIU_PCR[SRC] = 11b for DATA/ALE. 2. Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 3. Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency. The maximum external bus frequency is 66 MHz. 4. Refer to D_CLKOUT pad timing in Table 2. 5. ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0°C. 2.0ns spec applies to temperatures > 0°C. This spec has no dependency on the SIU_ECCR[EBTS] bit. VOH_F VDDE / 2 D_CLKOUT VOL_F 3 2 2 4 1 Figure 25. D_CLKOUT timing MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 59 Electrical characteristics VDDE / 2 D_CLKOUT 6 5 5 Output Bus VDDE / 2 6 5 5 Output Signal VDDE / 2 6 Output Signal VDDE / 2 Figure 26. Synchronous output timing MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 60 NXP Semiconductors Electrical characteristics D_CLKOUT VDDE / 2 7 8 Input Bus VDDE / 2 7 8 Input Signal VDDE / 2 Figure 27. Synchronous input timing ipg_clk D_CLKOUT D_ALE D_TS D_ADD/D_DAT DATA ADDR 9 10 Figure 28. ALE signal timing MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 61 Electrical characteristics 3.13.6 External interrupt timing (IRQ/NMI pin) Table 39. External Interrupt timing1 Spec Characteristic Symbol Min Max Unit 1 IRQ/NMI Pulse Width Low tIPWL 3 — tcyc, 2 2 IRQ/NMI Pulse Width High tIPWH 3 — tcyc2 3 IRQ/NMI Edge to Edge Time3 tICYC 6 — tcyc2 1. IRQ/NMI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, TA = TL to TH. 2. For further information on tcyc, see Table 1. 3. Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both. IRQ 1 2 3 Figure 29. External interrupt timing 3.13.7 eTPU timing Table 40. eTPU timing1 Spec Characteristic Symbol Min Max Unit 1 eTPU Input Channel Pulse Width tICPW 4 — tCYC_ETPU, 2 eTPU Output Channel Pulse Width tOCPW 13 — tCYC_ETPU2 2 1. eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00. 2. For further information on tCYC_ETPU, see Table 1. 3. This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 62 NXP Semiconductors Electrical characteristics eTPU Input and TCRCLK 1 2 eTPU Output Figure 30. eTPU timing 3.13.8 eMIOS timing Table 41. eMIOS timing1 Spec Characteristic Symbol Min Max Unit 1 eMIOS Input Pulse Width tMIPW 4 — tCYC_PER, 2 2 eMIOS Output Pulse Width tMOPW 13 — tCYC_PER2 1. eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. 2. For further information on tCYC_PER, see Table 1. 3. This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). eMIOS Input 1 2 eMIOS Output Figure 31. eMIOS timing MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 63 Electrical characteristics 3.13.9 DSPI timing with CMOS and LVDS pads NOTE The DSPI in TSB mode with LVDS pads can be used to implement the Micro Second Channel (MSC) bus protocol. DSPI channel frequency support is shown in Table 42. Timing specifications are shown in Table 43, Table 44, Table 45, Table 46, and Table 47. Table 42. DSPI channel frequency support Max usable frequency (MHz)1, 2 DSPI use mode CMOS (Master mode) LVDS (Master mode) Full duplex – Classic timing (Table 43) 17 Full duplex – Modified timing (Table 44) 30 Output only mode (SCK/SOUT/PCS) (Table 43 and Table 44) 30 Output only mode TSB mode (SCK/SOUT/PCS) (Table 47) 30 Full duplex – Modified timing (Table 45) 30 Output only mode TSB mode (SCK/SOUT/PCS) (Table 46) 40 1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads. 2. Maximum usable frequency does not take into account external device propagation delay. 3.13.9.1 3.13.9.1.1 DSPI master mode full duplex timing with CMOS and LVDS pads DSPI CMOS Master Mode — Classic Timing Table 43. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11 # Symbol 1 tSCK 2 tCSC Characteristic SCK cycle time PCS to SCK delay Condition2 Value3 Pad drive4 Load (CL) Min Max PCR[SRC]=11b 25 pF 33.0 — PCR[SRC]=10b 50 pF 80.0 — PCR[SRC]=01b 50 pF 200.0 — 25 pF (N5 50 pF (N5 PCR[SRC]=01b 50 pF (N5 – 18 — PCS: PCR[SRC]=01b 50 pF (N5 × tSYS, 6) – 45 — PCS: 0 pF (M7 × tSYS6) – 35 — (M7 × tSYS, 6) – 35 — PCR[SRC]=11b PCR[SRC]=10b , 6) – 16 — , 6) – 16 — , 6) × tSYS × tSYS × tSYS Unit ns ns SCK: PCR[SRC]=10b 3 tASC After SCK delay PCR[SRC]=11b ns SCK: 50 pF PCR[SRC]=10b PCS: 0 pF SCK: 50 pF Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 64 NXP Semiconductors Electrical characteristics Table 43. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11 (continued) # Symbol Characteristic Condition2 Value3 Pad drive4 Load (CL) Min Max PCR[SRC]=01b PCS: 0 pF (M7 × tSYS, 6) – 35 — (M7 × tSYS, 6) – 35 — Unit SCK: 50 pF 4 tSDC SCK duty cycle8 PCS: PCR[SRC]=01b PCS: 0 pF SCK: PCR[SRC]=10b SCK: 50 pF PCR[SRC]=11b 0 pF 1/2tSCK – 2 1/2tSCK + 2 PCR[SRC]=10b 0 pF 1/2tSCK – 2 1/2tSCK + 2 PCR[SRC]=01b 0 pF 1/2tSCK – 5 1/2tSCK + 5 ns PCS strobe timing 5 tPCSC PCSx to PCSS time, 9 PCR[SRC]=10b 25 pF 13.0 — ns 6 tPASC PCSS to PCSx time9 PCR[SRC]=10b 25 pF 13.0 — ns ns SIN setup time 7 tSUI SIN setup time to SCK10 PCR[SRC]=11b 25 pF 29.0 — PCR[SRC]=10b 50 pF 31.0 — PCR[SRC]=01b 50 pF 62.0 — SIN hold time 8 tHI SIN hold time from SCK10 PCR[SRC]=11b 0 pF –1.0 — PCR[SRC]=10b 0 pF –1.0 — PCR[SRC]=01b 0 pF –1.0 — ns SOUT data valid time (after SCK edge) 9 tSUO SOUT data valid time from SCK11 PCR[SRC]=11b 25 pF — 7.0 PCR[SRC]=10b 50 pF — 8.0 PCR[SRC]=01b 50 pF — 18.0 ns SOUT data hold time (after SCK edge) 10 tHO SOUT data hold time after SCK11 PCR[SRC]=11b 25 pF –9.0 — PCR[SRC]=10b 50 pF –10.0 — PCR[SRC]=01b 50 pF –21.0 — ns 1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 2. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified otherwise. 3. All timing values for output signals in this table are measured to 50% of the output voltage. 4. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 5. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 7. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 65 Electrical characteristics clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 8. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 9. PCSx and PCSS using same pad configuration. 10. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds. 11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. t CSC t ASC PCSx t SCK t SDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN t SDC t SUI t HI First Data Last Data Data t SUO SOUT t HO Data First Data Last Data Figure 32. DSPI CMOS master mode – classic timing, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) t SUI SIN t HI First Data Data t SUO SOUT First Data Data Last Data t HO Last Data Figure 33. DSPI CMOS master mode – classic timing, CPHA = 1 MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 66 NXP Semiconductors Electrical characteristics tPCSC tPASC PCSS PCSx Figure 34. DSPI PCS strobe (PCSS) timing (master mode) 3.13.9.1.2 DSPI CMOS Master Mode – Modified Timing Table 44. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11 # Symbol 1 tSCK 2 tCSC Characteristic SCK cycle time PCS to SCK delay Condition2 Value3 Pad drive4 Load (CL) Min Max PCR[SRC]=11b 25 pF 33.0 — PCR[SRC]=10b 50 pF 80.0 — PCR[SRC]=01b 50 pF 200.0 — PCR[SRC]=11b PCR[SRC]=10b PCR[SRC]=01b PCS: PCR[SRC]=01b 25 pF (N5 , 6) 50 pF (N5 – 16 — , 6) 50 pF (N5 – 16 — , 6) 50 pF (N5 – 18 — , 6) – 45 — (M7 × tSYS6) – 35 — (M7 × tSYS, 6) – 35 — (M7 × tSYS, 6) – 35 — (M7 × tSYS, 6) – 35 — × tSYS × tSYS × tSYS × tSYS Unit ns ns SCK: PCR[SRC]=10b 3 tASC After SCK delay PCR[SRC]=11b PCS: 0 pF ns SCK: 50 pF PCR[SRC]=10b PCS: 0 pF SCK: 50 pF PCR[SRC]=01b PCS: 0 pF SCK: 50 pF 4 tSDC SCK duty cycle8 PCS: PCR[SRC]=01b PCS: 0 pF SCK: PCR[SRC]=10b SCK: 50 pF PCR[SRC]=11b 0 pF 1/2tSCK – 2 1/2tSCK + 2 PCR[SRC]=10b 0 pF 1/2tSCK – 2 1/2tSCK + 2 PCR[SRC]=01b 0 pF 1/2tSCK – 5 1/2tSCK + 5 ns PCS strobe timing 5 tPCSC PCSx to PCSS time, 9 PCR[SRC]=10b 25 pF 13.0 — ns 6 tPASC PCSS to PCSx time9 PCR[SRC]=10b 25 pF 13.0 — ns — ns SIN setup time 7 tSUI SIN setup time to SCK CPHA = 010 PCR[SRC]=11b PCR[SRC]=10b PCR[SRC]=01b 25 pF 50 pF 50 pF 29 – (P11 × tSYS6) 31 – (P11 62 – (P11 × tSYS, 6) — × tSYS, 6) — Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 67 Electrical characteristics Table 44. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11 (continued) # Symbol Characteristic SIN setup time to SCK CPHA = 110 Condition2 Value3 Pad drive4 Load (CL) Min Max PCR[SRC]=11b 25 pF 29.0 — PCR[SRC]=10b 50 pF 31.0 — PCR[SRC]=01b 50 pF 62.0 — Unit ns SIN hold time 8 tHI12 SIN hold time from SCK CPHA = 010 SIN hold time from SCK CPHA = 110 PCR[SRC]=11b 0 pF –1 + (P11 × tSYS, 6) — PCR[SRC]=10b 0 pF –1 + (P11 × tSYS, 6) — –1 + (P11 × tSYS, 6) PCR[SRC]=01b 0 pF PCR[SRC]=11b 0 pF –1.0 — PCR[SRC]=10b 0 pF –1.0 — PCR[SRC]=01b 0 pF –1.0 — ns — ns SOUT data valid time (after SCK edge) 9 tSUO SOUT data valid time from SCK CPHA = 013 SOUT data valid time from SCK CPHA = 113 PCR[SRC]=11b 25 pF — 7.0 + tSYS6 PCR[SRC]=10b 50 pF — 8.0 + tSYS6 PCR[SRC]=01b 50 pF — 18.0 + tSYS6 PCR[SRC]=11b 25 pF — 7.0 PCR[SRC]=10b 50 pF — 8.0 PCR[SRC]=01b 50 pF — 18.0 ns ns SOUT data hold time (after SCK edge) 10 tHO SOUT data hold time after SCK CPHA = 013 SOUT data hold time after SCK CPHA = 113 PCR[SRC]=11b 25 pF –9.0 + tSYS6 6 — PCR[SRC]=10b 50 pF –10.0 + tSYS — PCR[SRC]=01b 50 pF –21.0 + tSYS6 — PCR[SRC]=11b 25 pF –9.0 — PCR[SRC]=10b 50 pF –10.0 — PCR[SRC]=01b 50 pF –21.0 — ns ns 1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 2. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified otherwise. 3. All timing values for output signals in this table are measured to 50% of the output voltage. 4. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 5. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 7. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 8. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 9. PCSx and PCSS using same pad configuration. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 68 NXP Semiconductors Electrical characteristics 10. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds. 11. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. 12. The 0 pF load condition given in the DSPI AC timing applies to theoretical worst-case hold timing. This guarantees worstcase operation, and additional margin can be achieved in the applications by applying a realistic load. 13. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. t CSC t ASC PCSx t SCK t SDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN t SDC t SUI t HI First Data Last Data Data t SUO SOUT t HO Data First Data Last Data Figure 35. DSPI CMOS master mode – modified timing, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) t SUI SIN t HI t HI Data First Data t SUO SOUT First Data Data Last Data t HO Last Data Figure 36. DSPI CMOS master mode – modified timing, CPHA = 1 MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 69 Electrical characteristics tPCSC tPASC PCSS PCSx Figure 37. DSPI PCS strobe (PCSS) timing (master mode) 3.13.9.1.3 DSPI LVDS Master Mode – Modified Timing Table 45. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1 # Symbol Characteristic 1 tSCK SCK cycle time 2 tCSC PCS to SCK delay (LVDS SCK) Condition1 tASC After SCK delay (LVDS SCK) Unit Pad drive3 Load (CL) Min Max LVDS 15 pF to 25 pF differential 33.3 — ns PCS: PCR[SRC]=11b 25 pF (N4 × tSYS, 5) – 10 — ns 50 pF (N4 50 pF (N4 PCS: PCR[SRC]=10b PCS: PCR[SRC]=01b 3 Value2 PCS: PCR[SRC]=11b PCS: 0 pF , 5) – 10 — ns , 5) – 32 — ns –8 — ns (M6 × tSYS, 5) – 8 — ns (M6 × tSYS, 5) – 8 — ns 1/2tSCK – 2 1/2tSCK +2 ns × tSYS × tSYS (M6 5) × tSYS SCK: 25 pF PCS: PCR[SRC]=10b PCS: 0 pF SCK: 25 pF PCS: PCR[SRC]=01b PCS: 0 pF LVDS 15 pF to 25 pF differential SCK: 25 pF 4 tSDC 7 tSUI SCK duty cycle7 SIN setup time SIN setup time to SCK LVDS 15 pF to 25 pF differential 23 – (P9 × tSYS5) — ns LVDS 15 pF to 25 pF differential 23 — ns CPHA = 08 SIN setup time to SCK CPHA = 18 8 SIN hold time tHI SIN hold time from SCK LVDS 0 pF differential –1 + (P9 × tSYS, 5) — ns LVDS 0 pF differential –1 — ns CPHA = 08 SIN hold time from SCK CPHA = 18 9 tSUO SOUT data valid time (after SCK edge) Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 70 NXP Semiconductors Electrical characteristics Table 45. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1 (continued) # Symbol Characteristic SOUT data valid time from SCK Condition1 Pad drive3 Value2 Load (CL) Min Max Unit LVDS 15 pF to 25 pF differential — 7.0 + tSYS5 ns LVDS 15 pF to 25 pF differential — 7.0 ns CPHA = 010 SOUT data valid time from SCK CPHA = 110 10 SOUT data hold time (after SCK edge) tHO SOUT data hold time after SCK LVDS 15 pF to 25 pF differential –7.5 + tSYS5 — ns LVDS 15 pF to 25 pF differential –7.5 — ns CPHA = 010 SOUT data hold time after SCK CPHA = 110 1. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified otherwise. 2. All timing values for output signals in this table are measured to 50% of the output voltage. 3. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = ±100 mV. 9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. 10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 71 Electrical characteristics t CSC t ASC PCSx t SCK t SDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN t SDC t SUI t HI First Data Last Data Data t SUO SOUT t HO Data First Data Last Data Figure 38. DSPI LVDS master mode – modified timing, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) t SUI SIN t HI t HI Data First Data t SUO SOUT First Data Data Last Data t HO Last Data Figure 39. DSPI LVDS master mode – modified timing, CPHA = 1 MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 72 NXP Semiconductors Electrical characteristics 3.13.9.1.4 DSPI Master Mode – Output Only Table 46. DSPI LVDS master timing — output only — timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock1, 2 # Symbol 1 tSCK SCK cycle time 2 tCSV 3 4 tCSH tSDC Characteristic Condition3 Value4 Unit Pad drive5 Load (CL) Min Max LVDS 15 pF to 50 pF differential 25 — ns PCS valid after SCK6 (SCK with 50 pF differential load cap.) PCR[SRC]=11b 25 pF — 8 ns PCR[SRC]=10b 50 pF — 12 ns PCS hold after SCK6 (SCK with 50 pF differential load cap.) PCR[SRC]=11b 0 pF –4.0 — ns PCR[SRC]=10b 0 pF –4.0 — ns SCK duty cycle (SCK with 50 pF differential load cap.) LVDS 15 pF to 50 pF differential 1/2tSCK – 2 1/2tSCK + 2 ns — 6 ns –7.0 — ns SOUT data valid time (after SCK edge) 5 tSUO SOUT data valid time from SCK7 LVDS 15 pF to 50 pF differential SOUT data hold time (after SCK edge) 6 tHO SOUT data hold time after SCK7 LVDS 15 pF to 50 pF differential 1. All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may degrade for weaker output drivers. 2. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1. 3. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified otherwise. 4. All timing values for output signals in this table are measured to 50% of the output voltage. 5. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 6. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays. 7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. Table 47. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock 1, 2 # Symbol 1 tSCK 2 tCSV Characteristic SCK cycle time PCS valid after SCK6 Condition3 Value4 Unit Pad drive5 Load (CL) Min Max PCR[SRC]=11b 25 pF 33.0 — ns PCR[SRC]=10b 50 pF 80.0 — ns PCR[SRC]=01b 50 pF 200.0 — ns PCR[SRC]=11b 25 pF 7 — ns PCR[SRC]=10b 50 pF 8 — ns PCR[SRC]=01b 50 pF 18 — ns PCS: PCR[SRC]=01b 50 pF 45 — ns SCK: PCR[SRC]=10b Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 73 Electrical characteristics Table 47. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock 1, 2 (continued) # Symbol 3 tCSH Characteristic PCS hold after SCK6 Condition3 Value4 Unit Pad drive5 Load (CL) Min Max PCR[SRC]=11b PCS: 0 pF –14 — ns –14 — ns –33 — ns –35 — ns SCK: 50 pF PCR[SRC]=10b PCS: 0 pF SCK: 50 pF PCR[SRC]=01b PCS: 0 pF SCK: 50 pF 4 tSDC SCK duty cycle7 PCS: PCR[SRC]=01b PCS: 0 pF SCK: PCR[SRC]=10b SCK: 50 pF PCR[SRC]=11b 0 pF 1/2tSCK – 2 1/2tSCK + 2 ns PCR[SRC]=10b 0 pF 1/2tSCK – 2 1/2tSCK + 2 ns PCR[SRC]=01b 0 pF 1/2tSCK – 5 1/2tSCK + 5 ns SOUT data valid time (after SCK edge) 9 tSUO SOUT data valid time from SCK CPHA = 18 PCR[SRC]=11b 25 pF — 7.0 ns PCR[SRC]=10b 50 pF — 8.0 ns PCR[SRC]=01b 50 pF — 18.0 ns SOUT data hold time (after SCK edge) 10 tHO SOUT data hold time after SCK CPHA = 18 PCR[SRC]=11b 25 pF –9.0 — ns PCR[SRC]=10b 50 pF –10.0 — ns PCR[SRC]=01b 50 pF –21.0 — ns 1. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1. 2. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 3. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified otherwise. 4. All timing values for output signals in this table are measured to 50% of the output voltage. 5. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 6. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays. 7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 8. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 74 NXP Semiconductors Electrical characteristics PCSx tCSV tSCK tSDC tCSH SCK Output (CPOL = 0) tSUO First Data SOUT Data tHO Last Data Figure 40. DSPI LVDS and CMOS master timing – output only – modified transfer format MTFE = 1, CHPA = 1 3.13.9.2 DSPI CMOS slave mode NOTE DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that case only. Table 48. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1) # Symbol Characteristic1 Condition Pad drive Value Load Unit Min Max 1 tSCK SCK Cycle Time — — 62 — ns 2 tCSC SS to SCK Delay — — 16 — ns 3 tASC SCK to SS Delay — — 16 — ns 4 tSDC SCK Duty Cycle — — 30 — ns Time2 PCR[SRC]=11b 25 pF — 50 ns (SS active to SOUT driven) PCR[SRC]=10b 50 pF — 50 ns PCR[SRC]=01b 50 pF — 50 ns Slave SOUT Disable PCR[SRC]=11b Time2 PCR[SRC]=10b (SS inactive to SOUT PCR[SRC]=01b High-Z or invalid) 25 pF — 40 ns 50 pF — 40 ns 50 pF — 40 ns Data Setup Time for Inputs — — 10 — ns 10 tHI Data Hold Time for Inputs — — 10 — ns 11 tSUO SOUT Valid Time2 PCR[SRC]=11b 25 pF — 30 ns (after SCK edge) PCR[SRC]=10b 50 pF — 30 ns PCR[SRC]=01b 50 pF — 60 ns PCR[SRC]=11b 25 pF 2.5 — ns 5 6 9 tA tDIS tSUI 12 tHO Slave Access SOUT Hold Time2 Table continues on the next page... MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 75 Electrical characteristics Table 48. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1) (continued) # Symbol Characteristic1 Condition Pad drive (after SCK edge) Value Load Unit Min Max PCR[SRC]=10b 50 pF 2.5 — ns PCR[SRC]=01b 50 pF 2.5 — ns 1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds. 2. All timing values for output signals in this table, are measured to 50% of the output voltage. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. tASC tCSC SS tSCK S C K In p u t (C P O L = 0 ) tSDC tSDC S C K In p u t (C P O L = 1 ) tSUO tA F irs t D a ta SOUT D a ta tDIS L a s t D a ta tSUI tHI D a ta F irst D a ta S IN tHO L a s t D a ta Figure 41. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 0 SS S C K In p u t (C P O L = 0 ) S C K In p u t (C P O L = 1 ) tSUO tA SOUT tHO F irs t D a ta tSUI S IN D a ta L a s t D a ta D a ta L a s t D a ta tDIS tHI F irs t D a ta Figure 42. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 1 MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 76 NXP Semiconductors Electrical characteristics 3.13.10 FEC timing 3.13.10.1 MII receive signal timing (RXD[3:0], RX_DV, and RX_CLK) The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency. Table 49. MII receive signal timing1 Symbol Value Characteristic Min Max 5 — Unit M1 RXD[3:0], RX_DV to RX_CLK setup ns M2 RX_CLK to RXD[3:0], RX_DV hold 5 — ns M3 RX_CLK pulse width high 35% 65% RX_CLK period M4 RX_CLK pulse width low 35% 65% RX_CLK period 1. All timing specifications valid to the pad input levels defined in I/O pad current specifications. M3 RX_CLK (input) M4 RXD[3:0] (inputs) RX_DV M1 M2 Figure 43. MII receive signal timing diagram 3.13.10.2 MII transmit signal timing (TXD[3:0], TX_EN, and TX_CLK) The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency. The transmit outputs (TXD[3:0], TX_EN) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of noncompliant MII PHYs. Refer to the MPC5777C Microcontroller Reference Manual's Fast Ethernet Controller (FEC) chapter for details of this option and how to enable it. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 77 Electrical characteristics Table 50. MII transmit signal timing1 Symbol Value2 Characteristic Min Max Unit M5 TX_CLK to TXD[3:0], TX_EN invalid 4.5 — ns M6 TX_CLK to TXD[3:0], TX_EN valid — 25 ns M7 TX_CLK pulse width high 35% 65% TX_CLK period M8 TX_CLK pulse width low 35% 65% TX_CLK period 1. All timing specifications valid to the pad input levels defined in I/O pad specifications. 2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value. M7 TX_CLK (input) M5 M8 TXD[3:0] (outputs) TX_EN M6 Figure 44. MII transmit signal timing diagram 3.13.10.3 Symbol M9 MII async inputs signal timing (CRS) Table 51. MII async inputs signal timing Value Characteristic CRS minimum pulse width Min Max 1.5 — Unit TX_CLK period CRS M9 Figure 45. MII async inputs timing diagram 3.13.10.4 MII and RMII serial management channel timing (MDIO and MDC) The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 78 NXP Semiconductors Electrical characteristics Table 52. MII serial management channel timing1 Symbol Value2 Characteristic Min Max Unit M10 MDC falling edge to MDIO output invalid (minimum propagation delay) 0 — ns M11 MDC falling edge to MDIO output valid (max prop delay) — 25 ns M12 MDIO (input) to MDC rising edge setup 10 — ns M13 MDIO (input) to MDC rising edge hold 0 — ns M14 MDC pulse width high 40% 60% MDC period M15 MDC pulse width low 40% 60% MDC period 1. All timing specifications valid to the pad input levels defined in I/O pad specifications. 2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value M14 M15 MDC (output) M10 MDIO (output) M11 MDIO (input) M12 M13 Figure 46. MII serial management channel timing diagram 3.13.10.5 RMII receive signal timing (RXD[1:0], CRS_DV) The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 79 Electrical characteristics Table 53. RMII receive signal timing1 Symbol Value Characteristic Min Max Unit R1 RXD[1:0], CRS_DV to REF_CLK setup 4 — ns R2 REF_CLK to RXD[1:0], CRS_DV hold 2 — ns R3 REF_CLK pulse width high 35% 65% REF_CLK period R4 REF_CLK pulse width low 35% 65% REF_CLK period 1. All timing specifications valid to the pad input levels defined in I/O pad specifications. R3 REF_CLK (input) R4 RXD[1:0] (inputs) CRS_DV R1 R2 Figure 47. RMII receive signal timing diagram 3.13.10.6 RMII transmit signal timing (TXD[1:0], TX_EN) The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency. The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This options allows the use of non-compliant RMII PHYs. Table 54. RMII transmit signal timing1 Symbol Characteristic Value2 Min Max Unit R5 REF_CLK to TXD[1:0], TX_EN invalid 2 — ns R6 REF_CLK to TXD[1:0], TX_EN valid — 16 ns R7 REF_CLK pulse width high 35% 65% REF_CLK period R8 REF_CLK pulse width low 35% 65% REF_CLK period 1. All timing specifications valid to the pad input levels defined in I/O pad specifications. 2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 80 NXP Semiconductors Package information R7 REF_CLK (input) R5 R8 TXD[1:0] (outputs) TX_EN R6 Figure 48. RMII transmit signal timing diagram 4 Package information To find the package drawing for each package, go to http://www.nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 416-ball MAPBGA 98ASA00562D 516-ball MAPBGA 98ASA00623D 4.1 Thermal characteristics Table 55. Thermal characteristics, 416-ball MAPBGA package Characteristic Symbol Value Unit Natural Convection (Single layer board) RΘJA 28.8 °C/W Natural Convection (Four layer board 2s2p) RΘJA 19.6 °C/W Junction to Ambient (@200 ft./min., Single layer board) RΘJMA 21.3 °C/W Junction to Ambient (@200 ft./min., Four layer board 2s2p) RΘJMA 15.1 °C/W RΘJB 9.5 °C/W RΘJC 4.8 °C/W ΨJT 0.2 °C/W Junction to Ambient 1, 2 Junction to Ambient 1, 3 Junction to Board Junction to Case 4 5 Junction to Package Top 6 Natural Convection 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 81 Package information 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Table 56. Thermal characteristics, 516-ball MAPBGA package Characteristic Symbol Value Unit Junction to Ambient 1, 2 Natural Convection (Single layer board) RΘJA 28.5 °C/W Junction to Ambient 1, 3 Natural Convection (Four layer board 2s2p) RΘJA 20.0 °C/W Junction to Ambient (@200 ft./min., Single layer board) RΘJMA 21.3 °C/W Junction to Ambient (@200 ft./min., Four layer board 2s2p) RΘJMA 15.5 °C/W RΘJB 8.8 °C/W RΘJC 4.8 °C/W ΨJT 0.2 °C/W Junction to Board Junction to Case 4 5 6 Junction to Package Top Natural Convection 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 4.1.1 General notes for thermal characteristics An estimation of the chip junction temperature, TJ, can be obtained from the equation: Equation 1 where: TA = ambient temperature for the package (°C) RΘJA = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: • Construction of the application board (number of planes) MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 82 NXP Semiconductors Package information • Effective size of the board which cools the component • Quality of the thermal and electrical connections to the planes • Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: • One oz. (35 micron nominal thickness) internal planes • Components are well separated • Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: Equation 2 where: TB = board temperature for the package perimeter (°C) RΘJB = junction-to-board thermal resistance (°C/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 83 Package information The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: Equation 3 where: RΘJA = junction-to-ambient thermal resistance (°C/W) RΘJC = junction-to-case thermal resistance (°C/W) RΘCA = case to ambient thermal resistance (°C/W) RΘJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RΘCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-toboard thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be generated upon request. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (ΨJT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: Equation 4 where: TT = thermocouple temperature on top of the package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 84 NXP Semiconductors Ordering information The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter (ΨJPB) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed pad) using the following equation: Equation 5 where: TT = thermocouple temperature on bottom of the package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) 5 Ordering information Figure 49 and Table 57 describe orderable part numbers for the MPC5777C. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 85 Document revision history M PC 5777C X K3 M ME 3/4 R Qualification status Core code Device number Optional features field Fab/Revision Temperature range Package identifier Operating frequency Tape and reel status Temperature range M = –40 °C to 125 °C Operating frequency 3 = 2 x 264 MHz Package identifier ME = 416 MAPBGA Pb-Free MO = 516 MAPBGA Pb-Free Tape and reel status R = Tape and reel (blank) = Trays Qualification status P = Pre-qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow 4 = 2 x 306 MHz Optional features field (blank) = ISO-compliant CAN FD not available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.07 A = ISO-compliant CAN FD not available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.08 R = ISO-compliant CAN FD not available, trimmed for LDO regulator, and includes SHE-compliant security firmware version 2.08 C = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.07 D = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.08 L = ISO-compliant CAN FD available, trimmed for LDO regulator, and includes SHE-compliant security firmware version 2.08 S = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes RSA-enhanced security firmware T = ISO-compliant CAN FD available, trimmed for LDO regulator, and includes RSA-enhanced security firmware Note: Not all options are available on all devices. Figure 49. MPC5777C Orderable part number description Table 57. Example orderable part numbers Part number1 SPC5777CCK3MME3 Package description Speed (MHz)2 MPC5777C 416 package Operating temperature3 Min (TL) Max (TH) 264 –40 °C 125 °C 264 –40 °C 125 °C 264 –40 °C 125 °C 264 –40 °C 125 °C Lead-free (Pb-free) SPC5777CK3MME3 MPC5777C 416 package Lead-free (Pb-free) SPC5777CCK3MMO3 MPC5777C 516 package Lead-free (Pb-free) SPC5777CK3MMO3 MPC5777C 516 package Lead-free (Pb-free) 1. All packaged devices are PPC5777C, rather than MPC5777C or SPC5777C, until product qualifications are complete. The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete. Not all configurations are available in the PPC parts. 2. For the operating mode frequency of various blocks on the device, see Table 1. 3. The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH. 6 Document revision history The following table summarizes revisions to this document since the previous release. MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 86 NXP Semiconductors Document revision history Table 58. Revision history Revision Date 15 03/2021 Description of changes Added DSPI CMOS slave mode. In Table 3 : • Changed the Max frequency of fSYS, fPLATF and fPER. • Updated the Max frequency footnotes of fSYS, fPLATF and fETPU. In Table 12, updated the fPLL0PHI Max frequency footnote. In Table 13, updated the fPLL1PHI Max frequency footnote. In Table 34, changed 100 MHz < fPLATF ≤ 150 MHz to 100 MHz < fPLATF ≤ 153 MHz In Figure 49, Changed the Operating frequency from 4 = 2 x 300 MHz to 4 = 2 x 306 MHz. In Table 18 : • Changed the condition of δGROUP from "Within pass band – Tclk is fADCD_M/ 2" to "Within pass band – Tclk is 2/fADCD_M". • In the footnote of tLATENCY changed the Register Latency formula from "where fADCD_S is the after-decimation ADC output data rate, fADCD_M is the modulator sampling rate and fFM_PER_CLK is the frequency of the peripheral bridge clock feeds to the ADC S/D module. REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fFM_PER_CLK" to "where fADCD_S is the after-decimation ADC output data rate, fADCD_M/2 is the modulator sampling rate and fFM_PER_CLK is the frequency of the peripheral bridge clock feeds to the ADC S/D module. REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~ +1)/fFM_PER_CLK". 14 01/2020 In Table 17, updated the footnote from "TUE does not apply to differential conversions" to "TUE, Gain, and Offset specifications do not apply to differential conversions". In Table 4 added Max value 120 μA for 40°C and 360 μA for 85°C for ISTBY. 13 08/2018 In Table 3, added information for 300 MHZ frequency: • fSYS • fPLATF • fETPU • fPER • ffFM_PER In Table 12 added Max value 240 MHz for fPLL0PHI and Table 13 added Max value 300 MHz for fPLL1PHI. In Table 34 updated the row from "100 MHz > fPLATF ≤ 133 MHz" to "100 MHz > fPLATF ≤ 150 MHz" under "Flash memory frequency" column. In Figure 49 added 300 MHz frequency orderable part number. 12 08/2018 In Table 12 of PLL electrical specifications, changed text of footnote 1: • from: "fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range 8 MHz to 20 MHz." • to: "Ensure that the fPLL0IN frequency divided by PLLDIG_PLL0DV[PREDIV] is in the range 8 MHz to 20 MHz." In Table 17 of Enhanced Queued Analog-to-Digital Converter (eQADC), added footnote about Max value of Conversion Cycles (CC): "128 sampling cycles (LST=128), differential conversion, pregain of x4" In Table 38 of External Bus Interface (EBI) timing, changed text of footnote 1: MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 NXP Semiconductors 87 Document revision history Table 58. Revision history Revision Date Description of changes • from: "EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with SIU_PCR[DSC] = 10b for ADDR/CTRL and SIU_PCR[DSC] = 11b for CLKOUT/DATA." • to: "EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with SIU_PCR[DSC] = 11b for ADDR/CTRL and SIU_PCR[SRC] = 11b for DATA/ ALE." In I/O pad current specifications added the text "The EBI power segments have..........segment does not exceed the spec". MPC5777C Microcontroller Data Sheet, Rev. 15, 03/2021 88 NXP Semiconductors How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. 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