TEA2093TS/1Z

TEA2093TS GreenChip synchronous rectifier controller Rev. 1 — 7 June 2022 1 Product data sheet General description The TEA2093TS is a member of a new generation of synchronous rectifier (SR) controller ICs for switched mode power supplies. It includes an adaptive gate drive for maximum efficiency at any load. The TEA2093TS is a dedicated controller IC for synchronous rectification on the secondary side of asymmetrical half-bridge flyback and standard flyback converters. It incorporates the sensing stage and driver stage for driving the SR MOSFET, which is rectifying the output of the secondary transformer winding. The TEA2093TS can generate its own supply voltage for battery-charging applications with low output voltage or for applications with high-side rectification. The TEA2093TS is fabricated in a silicon-on-insulator (SOI) process. 2 Features and benefits 2.1 Efficiency features • Adaptive gate drive for maximum efficiency at any load • Typical supply current in no-load operation below 200 μA 2.2 Application features • • • • • • • Operates in a wide output voltage range down to 0 V Drain sense pin capable of handling input voltages up to 120 V Self-supplying for operation with low output voltage Self-supplying for high-side rectification without the use of an auxiliary winding Operates with standard and logic level SR MOSFETs Supports USB BC, USB PD, and quick charge applications TSOP6 package 2.3 Control features • Adaptive gate drive for fast turn-off at the end of conduction • Undervoltage lockout (UVLO) with active gate pull-down TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 3 Applications The TEA2093TS is intended for flyback power supplies. In such applications, it can drive the external synchronous rectifier MOSFET, which replaces the diode for the rectification of the voltage on the secondary winding of the transformer. It can be used in all power supplies needing high efficiency, like: • • • • 4 Chargers Adapters Asymmetrical half-bridge flyback power supplies Flyback power supplies with very low and/or variable output voltage Ordering information Table 1. Ordering information Type number TEA2093TS/1 5 Package Name Description Version TSOP6 plastic surface-mounted package; 6 leads SOT457 Marking Table 2. Marking codes TEA2093TS Product data sheet Type number Marking code TEA2093TS/1 TEA2093 All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 2 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 6 Block diagram CAP XV V AND I REFERENCE Ich(CAP) UNDER VOLTAGE LOCKOUT DRIVER SUPPLY 4 V - 12 V TEA2093 ENERGY SAVE CONTROL LOGIC enable on regulation off regulation DRAIN -37 mV SOURCE GATE SWITCH-OFF - -30 mV - +300 mV - GND aaa-045353 Figure 1.  TEA2093TS block diagram TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 3 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 7 Pinning information 7.1 Pinning CAP 1 GND 2 XV 3 IC 6 DRAIN 5 SOURCE 4 GATE aaa-021171 Figure 2. TEA2093TS pin configuration (SOT457) 7.2 Pin description Table 3. Pin description TEA2093TS Product data sheet Symbol Pin Description CAP 1 capacitor input for internal supply voltage GND 2 ground XV 3 external supply input GATE 4 gate driver output for SR MOSFET SOURCE 5 source sense input of SR MOSFET DRAIN 6 drain sense input of SR MOSFET All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 4 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 8 Functional description 8.1 Introduction The TEA2093TS is a controller IC for synchronous rectification (SR) in asymmetrical halfbridge flyback and standard flyback applications. It can drive the external synchronous rectifier MOSFET for the rectification of the voltage on the secondary winding of the transformer. Figure 3 shows a typical configuration. SR low side VCC HV GND CTRL PROTECT 8 2 6 3 PRIMARY CONTROLLER 7 4 5 1 DRIVER S1 SECONDARY OPTO CONTROLLER ISENSE AUX VCC XV GND DRAIN GATE TEA2093 CAP SOURCE GND aaa-045354 Figure 3. TEA2093TS configuration with low-side rectification 8.2 Start-up and undervoltage lockout (UVLO; CAP and XV pins) The capacitor on the CAP pin supplies the TEA2093TS. It is charged via the DRAIN pin when the XV voltage is < 4.7 V. The charge current (Ich(CAP)) charges the capacitor to 4 V. When this voltage is reached, it stops charging. If the external voltage exceeds 4.7 V, the XV pin increases the capacitor voltage via an integrated diode. The increase of the capacitor voltage gives a higher gate driver voltage (VG(max)). When the voltage on the CAP pin exceeds Vstart(CAP) (3.7 V typical), the IC leaves the UVLO state and activates the synchronous rectifier circuitry. When the voltage drops to below 3.6 V (typical), the UVLO state is reentered and the SR MOSFET gate driver output is actively kept low. 8.3 Drain sense (DRAIN pin) The drain sense pin is an input pin capable of handling input voltages up to 120 V. At a positive drain sense voltage, the gate driver is in off-mode with the gate driver pulled down (pin GATE). At a negative drain sense voltage, the IC enables the synchronous rectification (SR) by sensing the drain source differential voltage. TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 5 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 8.4 Synchronous rectification (DRAIN and SOURCE pins) The IC senses the voltage difference between the drain sense (DRAIN pin) and the source sense (SOURCE pin) connections. This drain source differential voltage of the SR MOSFET is used to drive the gate of the SR MOSFET. In the regulation phase, the IC regulates the difference between the drain and the source sense inputs to an absolute level of 37 mV. When the absolute difference exceeds 37 mV (Vreg(drv)), the gate driver output increases the gate voltage of the external SR MOSFET until the 37 mV level is reached. The SR MOSFET does not switch off at low current. When the absolute difference is < 30 mV, the gate driver output decreases the gate voltage of the external SR MOSFET. The voltage waveform on the SR MOSFET gate follows the waveform of the current through the SR MOSFET. When the current through the SR MOSFET reaches zero, the SR MOSFET is quickly switched off. After SR MOSFET switch-off, the drain voltage increases. When the drain voltage exceeds 300 mV, a low ohmic gate pull-down of 7 Ω keeps the gate of the SR MOSFET switched off. 8.5 Gate driver (GATE pin) The gate driver circuit charges the gate of the external SR MOSFET during the rising part of the current. The driver circuit discharges the gate during the falling part of the current. The gate driver has a source capability of typically 0.50 A and a sink capability of typically 0.65 A, allowing fast turn-on and fast turn-off of the external SR MOSFET. The maximum output voltage of the driver is limited to 12 V. This high output voltage drives all MOSFET brands to the minimum on-state resistance. In applications where the IC is supplied with 5 V, the maximum output voltage of the driver is 4.2 V and logic level SR MOSFETs can be used (see Figure 3). The IC is self-supplying in applications with high-side rectification or in battery-charging applications with an output voltage below 4.7 V. When the XV pin is connected to ground for driving standard SR MOSFETs, the driver is regulated to 9 V. When the XV pin is connected to the converter output for driving logic-level SR MOSFETs, the driver is regulated to 4 V if the output voltage is below 4.7 V. VCAP VG(MAX) VCAP 12 V VG(MAX) 10 V 9V 4V 0 1V 5V 12 V XV aaa-021190 Figure 4. Maximum gate voltage Vg(max) TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 6 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller During start-up conditions (VCAP < Vstart(CAP)) and UVLO, the driver output voltage is actively pulled low. 8.6 Source sense (SOURCE pin) The IC is equipped with an additional source sense pin (SOURCE). This pin is used for measuring the drain-to-source voltage of the external SR MOSFET. The source sense input must be connected as close as possible to the SOURCE pin of the external SR MOSFET. It minimizes errors, caused by voltage differences on PCB tracks due to parasitic inductance in combination with large dI/dt values. TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 7 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 9 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to ground (pin 2); positive currents flow into the chip. Voltage ratings are valid provided other ratings are not violated; current ratings are valid provided the other ratings are not violated. Symbol Parameter Conditions Min Max Unit Voltages VXV voltage on pin XV −0.4 +38 V Vsense(DRAIN) sense voltage on pin DRAIN −0.8 +120 V Vsense(SOURCE) sense voltage on pin SOURCE −0.4 +0.4 V Currents IXV current on pin XV peak current - 0.5 A Ptot total power dissipation Tamb = 90 °C - 300 mW Tstg storage temperature −55 +150 °C Tj junction temperature −40 +150 °C - 2000 V - 500 V General Electrostatic discharge (ESD) VESD electrostatic discharge voltage class 2 human body model charged device model [1] [1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. 10 Thermal characteristics Table 5. Thermal characteristics TEA2093TS Product data sheet Symbol Parameter Rth(j-a) Rth(j-c) Conditions Typ Unit thermal resistance from junction to JEDEC test board ambient 200 K/W thermal resistance from junction to JEDEC test board case 115 K/W All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 8 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 11 Characteristics Table 6. Characteristics −25 °C < Tj < +125 °C; Vxv = 12 V; CCAP = 1 μF; CGATE = 10 nF (capacitor between the GATE and the GND pins); all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Limits are production tested at 25 °C. Statistical characterization in the temperature operating range ensure these limits. Symbol Parameter Conditions Min Typ Max Unit Supply voltage management (XV and CAP pins) Vstart(CAP) start voltage on pin CAP VXV = 0 V 3.55 3.70 3.90 V Vstop(CAP) stop voltage on pin CAP VXV = 0 V 3.45 3.60 3.80 V Ich(CAP) charge current on pin CAP VXV = 0 V; VCAP = 7 V; VDRAIN = 12 V; Tj = 25 °C −95 −70 −50 mA VXV = 2 V; VCAP = 3.65 V; VDRAIN = 12 V; Tj = 25 °C −95 −70 −50 mA VXV = 0 V; VDRAIN = 12 V 8.70 9.20 9.60 V VXV = 2 V; VDRAIN = 12 V 3.80 4.00 4.15 V VXV = 5 V 4.15 4.30 4.75 V VXV = 12 V 11.0 11.3 11.7 V power save operation; VXV = 5 V 90 160 300 μA 1.60 1.85 mA VI(CAP) II(XV) input voltage on pin CAP input current on pin XV normal operation; 1.35 without gate charge; VXV = 5 V; Tj = 25 °C Synchronous rectification sense input (DRAIN and SOURCE pins) Vreg(drv) driver regulation voltage VSOURCE = 0 V; Tj = 25 °C −40 −37 −35 mV Vswoff switch-off voltage VSOURCE = 0 V; Tj = 25 °C 200 300 400 mV td(act)(drv) driver activation delay time VSOURCE = 0 V; normal operation; time for step on VDRAIN (2 V to −0.5 V) to rising of VGATE at 10 % of end value - 65 - ns td(deact)(drv) driver deactivation delay time VSOURCE = 0 V; normal operation; time for step on VDRAIN (−0.5 V to 2 V) to falling of VGATE at 10 % begin value - 40 - ns TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 9 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller Table 6. Characteristics...continued −25 °C < Tj < +125 °C; Vxv = 12 V; CCAP = 1 μF; CGATE = 10 nF (capacitor between the GATE and the GND pins); all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Limits are production tested at 25 °C. Statistical characterization in the temperature operating range ensure these limits. Symbol Parameter Conditions Min Typ Max Unit VXV = 5 V; Vds = −0.5 V; Vg = 0 V - −0.13 - A VXV = 12 V; Vds = −0.5 V; Vg = 0 V - −0.50 - A VXV = 5 V; Vds = 0 V; Vg = 4 V - 150 - mA VXV = 12 V; Vds = 0 V; Vg = 10 V - 210 - mA VXV = 5 V; Vds = 4 V; Vg = 4 V - 0.35 - A VXV = 12 V; Vds = 4 V; Vg = 4 V - 0.65 - A Gate driver (GATE pin) Isource Isink source current peak current sink current regulation current peak current Rpd(G) gate pull-down resistance VDRAIN = 4 V; IGATE = 30 mA; VXV = 12 V; Tj = 25 °C 6.00 6.80 7.60 Ω VG(max) maximum gate voltage VXV = 0 V 7.80 8.90 9.60 V VXV = 2 V 3.75 3.95 4.15 V VXV = 5 V 4.00 4.20 4.40 V VXV = VCAP = 5 V 4.90 4.95 5.00 V VXV = 12 V 9.40 9.80 10.70 V VXV = 18 V to 38 V 11.80 12.30 12.70 V TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 10 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 11.1 Temperature curves 11.1.1 Charge current (CAP pin) aaa-022432 0 Ich(CAP) (mA) -20 -40 (1) -60 -80 (2) -100 -50 -25 0 25 50 75 100 125 T (°C) 150 (1) Ich(CAP) at VCAP = 7 V; VXV = 0 V (2) Ich(CAP) at VCAP = 3.65 V; VXV = 2 V Figure 5. Ich(CAP) as a function of temperature 11.1.2 Operating current (XV pin) aaa-022437 2000 II(XV) (µA) (2) 1600 1200 800 400 (1) 0 -50 -25 0 25 50 75 100 125 T (°C) 150 (1) II(XV)) - power save operation (2) II(XV) - normal operation Figure 6. II(XV) as a function of temperature TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 11 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 11.1.3 Driver regulation voltage -50 0 -25 0 25 50 75 100 T (°C) 125 150 Vreg(drv) (mV) -10 -20 -30 -40 -50 aaa-022449 Figure 7. Vreg(drv) as a function of temperature 11.1.4 Gate pull-down resistance aaa-022462 10 Rpd(G) (Ω) 8 6 4 2 0 -50 -25 0 25 50 75 100 125 T (°C) 150 Figure 8. Rpd(G) as a function of temperature TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 12 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 11.1.5 Switch-off voltage aaa-022464 400 Vswoff (mV) 300 200 100 0 -50 -25 0 25 50 75 100 125 T (°C) 150 Figure 9. Vswoff as a function of temperature TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 13 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 12 Application information A flyback switched mode power supply with the TEA2093TS consists of a primary side controller with a primary switch, a transformer, and an output stage. To obtain low conduction loss rectification, an SR MOSFET is used in the output stage. The SR MOSFET can be placed low-side (see Figure 3) or can be placed high-side (see Figure 10). In the high-side application, the TEA2093TS is self-supplying. The capacitor on the CAP pin supplies the TEA2093TS. When the drain voltage is positive, it is charged via the DRAIN pin. The gate drive voltage for the synchronous rectifier switch is derived from the voltage difference between the corresponding drain sense and source sense pins. Special attention must be paid to the connection of the drain sense and source sense pins. The voltages measured on these pins are used for the gate drive voltage. Wrong measurement results in a less efficient gate drive because a gate voltage that is either too low or too high. The connections to these pins must not interfere with the power wiring. The power wiring conducts currents with high dI/dt values. It can easily cause measurement errors resulting from induced voltages due to parasitic inductances. The separate source sense pins make it possible to sense the source voltage of the external MOSFETs directly. So, the current carrying power ground tracks are not required. SR high side XV DRAIN GATE TEA2093 CAP SOURCE GND VCC SECONDARY OPTO CONTROLLER HV GND CTRL PROTECT 8 2 6 7 3 PRIMARY CONTROLLER 4 5 1 DRIVER S1 GND ISENSE AUX VCC aaa-045357 Figure 10. TEA2093TS configuration with high-side rectification TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 14 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 13 Package outline Table 7.  Plastic surface-mounted package (TSOP6); 6 leads D SOT457 B E y A HE 6 5 X v M A 4 Q pin 1 index A A1 1 2 c 3 Lp e bp w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT457 JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Figure 11. Package outline SOT457 (TSOP6) TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 15 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 14 Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes TEA2093TS v.1 20220607 Product data sheet - - TEA2093TS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 7 June 2022 © NXP B.V. 2022. All rights reserved. 16 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller 15 Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 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All rights reserved. 17 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 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All rights reserved. 18 / 19 TEA2093TS NXP Semiconductors GreenChip synchronous rectifier controller Contents 1 2 2.1 2.2 2.3 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 9 10 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 12 13 14 15 General description ............................................ 1 Features and benefits .........................................1 Efficiency features ............................................. 1 Application features ........................................... 1 Control features ................................................. 1 Applications .........................................................2 Ordering information .......................................... 2 Marking .................................................................2 Block diagram ..................................................... 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 4 Functional description ........................................5 Introduction ........................................................ 5 Start-up and undervoltage lockout (UVLO; CAP and XV pins) ............................................. 5 Drain sense (DRAIN pin) ...................................5 Synchronous rectification (DRAIN and SOURCE pins) .................................................. 6 Gate driver (GATE pin) ......................................6 Source sense (SOURCE pin) ............................ 7 Limiting values .................................................... 8 Thermal characteristics ......................................8 Characteristics .................................................... 9 Temperature curves ......................................... 11 Charge current (CAP pin) ................................11 Operating current (XV pin) .............................. 11 Driver regulation voltage ..................................12 Gate pull-down resistance ............................... 12 Switch-off voltage ............................................ 13 Application information .................................... 14 Package outline .................................................15 Revision history ................................................ 16 Legal information .............................................. 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2022. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 June 2022 Document identifier: TEA2093TS