TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-asMicrophone
Rev. 1 — 12 April 2017
1
Product short data sheet
COMPANY PUBLIC
General description
The TFA9872 is a 9.5 V boosted class-D audio amplifier featuring Speaker-asMicrophone (SaM) and Receiver-as-Microphone (RaM) modes. It can deliver up to
10.0 W peak output power into an 8 Ω speaker and up to 11.8 W peak output power into
a 6 Ω speaker, at a supply voltage of 4.0 V. The internal adaptive DC-to-DC converter
raises the supply voltage to 9.5 V, providing ample headroom for major improvements in
sound quality.
Internal adaptive DC-to-DC conversion boosts the supply rail to provide additional
headroom and power output. The supply voltage is only raised when necessary,
maximizing the output power of the class-D audio amplifier while limiting quiescent power
consumption.
The device can be configured to drive either a hands-free speaker (4 Ω to 8 Ω) for audio
playback, or a receiver speaker (32 Ω) for handset playback, allowing it to be embedded
in platforms that support either or both options. The maximum output power, gain, and
noise levels are lower in the Handset Call use case than in the Hands-free Call use case.
The SaM feature allows the speaker to be used as an additional microphone when
not configured for audio playback. This function performs best in high sound pressure
environments (like concert recording or wind noise calls) and is targeted at such use
cases.
The TFA9872 also incorporates battery protection. By limiting the supply current when
the battery voltage is low, the device is prevented from switching off unexpectedly due to
excessive load currents (excessive load currents can lead to a system undervoltage).
Because it has a digital input interface that is insensitive to clock jitter, the TFA9872
features low RF susceptibility. The second order closed loop architecture used in a classD audio amplifier provides excellent audio performance and high supply voltage ripple
2
rejection. The audio input interface is I S and the control settings are communicated via
2
an I C-bus interface.
The TFA9872 is available in a 42-bump WLCSP (Wafer Level Chip-Size Package) with a
400 mm pitch.
TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3
High output power: 5.1 W (average) into 8 W at 4.0 V supply voltage (THD = 1 %)
Supports handset (16 Ω or 32 Ω) and hands-free (4 Ω or 8 Ω) speaker configurations
High efficiency, low power dissipation and low-noise speaker driver
Adaptive DC-to-DC converter increases the supply voltage smoothly when switching
between fixed boost and adaptive boost modes, preventing large battery supply spikes
and limiting quiescent power consumption.
Wide supply voltage range (fully operational from 2.7 V to 5.5 V)
Very low noise output 9 V, Po = 2.0 W, RL = 4 Ω
[2]
-
-
0.09
%
A-weighted; DATAI = 0 V; Low Noise
mode (ISTLA = 1); fs = 8 kHz
[2]
-
19
24
μV
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
A-weighted; DATAI = 0 V; Low Noise
mode (ISTLA = 1); fs = 16 kHz
[2]
-
55
60
μV
[2]
100
-
-
dB
S/N
signal-to-noise ratio
A-weighted, VBAT = 3.4 V to 5 V,
maximum signal at THD = 1 %
PSRR
power supply rejection ratio
from VBAT; booster in follower mode
(VDDP = VBAT); fripple = 217 Hz square
wave, Vripple = 50 mV(p-p), VBAT =
4.0 V
-
80
-
dB
from VBAT; booster in follower mode
(VDDP = VBAT); fripple = 20 Hz to 1 kHz
sine wave, Vripple = 200 mV (RMS),
VBAT = 3.4 V to 5.0 V; Low Power
and Low Noise modes on
60
80
-
dB
from VBAT; fripple = 20 Hz to 1 kHz
sine wave, Vripple = 200 mV (RMS),
VBAT = 3.4 V to 5.0 V; DC-DC in
follower OR booster; Low Power and
Low Noise modes off
-
75
-
dB
from VBAT; booster in follower mode
(VDDP = VBAT); fripple = 1 kHz to 20
kHz sine wave, Vripple = 200 mV
(RMS), VBAT = 3.4 V to 5.0 V
-
70
-
dB
-0.1
-
0.7
dB
2
mV
∆G/Δf
gain variation with frequency
BW = 20 Hz to 15 kHz, VBAT = 3.4 V
to 5 V
VPOP
pop noise voltage
at mode transition and gain change.
RL
load resistance
CL
load capacitance
2
fsw
switching frequency
directly coupled to the I S input
frequency
Gv
voltage gain
I S/TDM to VO; INPLEV = 0 (0 dB)
2
4
8
32
Ω
-
-
200
pF
256
-
384
kHz
6
-
21
dB
Amplifier power-up, power-down and propagation delays
td(on)PLL
PLL turn-on delay time
PLL locked on BCK, fs = 48 kHz
-
2
-
ms
td(on)amp
amplifier turn-on delay time
fs = 48 kHz
-
1
-
ms
td(off)
turn-off delay time
-
32
-
μs
td(alarm)
alarm delay time
-
200
-
ms
tPD
propagation delay
-
1750
-
μs
2
fs = 16 kHz (I S/TDM)
2
fs = 48 kHz (I S/TDM)
-
600
-
μs
2
fs = 96/192 kHz (I S/TDM)
-
320
-
μs
fs = 48 kHz (PDM)
-
70
-
μs
0.7
1.0
2.2
μH
30
-
-
μH
Booster Inductance
Lbst
boost inductance
Current-sensing performance
LL(spk)
speaker load inductance
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Product short data sheet
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
S/N
signal-to-noise ratio
IO = 1.1A (peak); A-weighted
62
65
-
dB
ΔIsense
current sense mismatch
over frequency; 20 Hz to 4 kHz
-
-
3
%
over temperature; fi = 1 kHz; Tj =
-20 °C to 85 °C
-
2
-
%
over VDDP; fi = 1 kHz, VDDP = 2.7 V to
9.5 V
-
1
-
%
fi = 20 Hz to 20 kHz; Vi = -6 dBFS;
TDMSPKG = 0110
-
-
0.75
%
0.02
-
20
kHz
PGAGAIN = 30 dB (± 1.5 dB
accuracy)
-
27.6
-
dB
PGAGAIN = 24 dB (± 1.5 dB
accuracy)
-
22.2
-
dB
PGAGAIN = 18 dB (± 1.5 dB
accuracy)
-
16.8
-
dB
PGAGAIN = 16 dB (± 1.5 dB
accuracy)
-
14.9
-
dB
THD+N
total harmonic distortion-plus-noise
B
bandwidth
[2]
Speaker-as-microphone performance; pins OUTA, OUTB
GPGA
Vi(max)
Vn(i)(eq)
S/N
THD+N
PGA gain
maximum input voltage
equivalent input noise voltage
signal-to-noise ratio
total harmonic distortion-plus-noise
TFA9872_SDS
Product short data sheet
COMPANY PUBLIC
PGAGAIN = 18 dB; RMS value
[3]
-
10.5
-
mV
PGAGAIN = 30 dB; RMS value
[4]
-
3.0
-
mV
A-weighted, PGAGAIN: 30 dB; TDM
Output; RMS value
-
1.05
-
μV
A-weighted, PGAGAIN: 16 dB; TDM
Output; RMS value
-
2.35
-
μV
A-weighted, PGAGAIN: 30 dB; PDM
Output; RMS value
-
1.20
-
μV
A-weighted, PGAGAIN: 16 dB; PDM
Output; RMS value
-
1.35
-
μV
A-weighted; PDM output; full scale
input; PGAGAIN: 18 dB;
-
78.6
-
dB
A-weighted; PPDM Output
Full scale input, PGA gain setting
GAIN_00
-
70.3
-
dB
A-weighted; PTDM output; full scale
input; PGAGAIN: 18 dB;
-
76.9
-
dB
TDM output; full scale input;
PGAGAIN: 30 dB
-
69.6
-
dB
fi = 1 kHz, Vi = 0.5ΩmV (RMS),
maximum PGA gain setting (30 dB),
on pin OUTA/OUTB
-
0.3
-
%
fi = 1 kHz, Vi = 0. 5 mV (RMS),
maximum PGA gain setting (30 dB),
on pin AUXSAMN/AUXSAMP
-
0.45
-
%
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PSRR
power supply rejection ratio
square wave on VDDD, fripple = 217
Hz, Vripple = 50 mV (p-p), maximum
PGA gain setting (30 dB)
-
70
-
dB
sine wave on VDDD, fripple = 20 Hz to
1 kHz, Vripple = 100 mV (RMS),
maximum PGA gain setting (30 dB)
-
70
-
dB
sine wave on VDDD, fripple = 1 kHz to
20 kHz, Vripple = 100 mV (RMS),
maximum PGA gain setting (30 dB)
-
60
-
dB
-10
-
10
%
VO(offset)
[1]
[2]
[3]
[4]
[5]
output offset voltage
% of Full Scale; PDM output only
(offset is removed on TDM output)
[5]
LBST = boost converter inductance; RL = load resistance; LL = load inductance (speaker).
This parameter is not tested during production; the value is guaranteed by design and checked during product validation.
Overload level at input; output is specified at 0 dBFS for TDM/PDM output max, or output limited at THD+N =1 % if reached before 0 dBFS; THD = 1 %.
Overload level at input; output is specified at 0 dBFS for TDM/PDM output max, or output limited at THD+N = 1 % if reached before 0 dBFS; THD = 1 %.
When using PDM output for Speaker-as-Microphone, PDM stream decimation shall be done in codec or AP running SAM software and it must include a
DC offset remover.
TFA9872_SDS
Product short data sheet
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
2
11.3 I S timing characteristics
2
Table 8. I S bus interface characteristics; see Figure 4
[1]
All parameters are guaranteed for VBAT = 3.6 V; VDDD = 1.8 V; VDDP = VBST = 9.0 V, Adaptive Boost mode; LBST = 1 μH ;RL
[1]
[1]
= 8 Ω ; LL = 44 μH ; fi = 1 kHz; fs = 48 kHz; Tamb = 25 °C; default settings, unless otherwise specified.
Symbol Parameter
Conditions
fs
on pin WS, audio mode
sampling frequency
[2]
on pin WS, ultrasonic mode
fclk
clock frequency
[2]
on pin BCK, audio mode
on pin BCK, ultrasonic mode
tsu
[3]
WS edge to BCK HIGH
set-up time
DATA edge to BCK HIGH
th
[3]
BCK HIGH to WS edge
hold time
BCK HIGH to DATA edge
[1]
[2]
[3]
Min
Typ
Max
Unit
16
-
48
kHz
96
-
192
kHz
32fs
-
384fs
kHz
-
-
96fs
MHz
10
-
-
ns
10
-
-
ns
10
-
-
ns
10
-
-
ns
LBST = boost converter inductance; RL = load resistance; LL = load inductance.
2
The I S bit clock input (BCK) is used as a clock input for the amplifier and the DC-to-DC converter. Note that both the BCK and WS signals must be
present for the clock to operate correctly.
This parameter is not tested during production; the value is guaranteed by design and checked during product validation.
BCK
th
tsu
FS
DATA
010aaa750
2
Figure 4. I S timing
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
2
11.4 I C timing characteristics
2
Table 9. I C-bus interface characteristics; see Figure 5
[1]
All parameters are guaranteed for VBAT = 3.6 V; VDDD = 1.8 V; VDDP = VBST = 9.0 V, Adaptive Boost mode; LBST = 1 μH ;RL
[1]
[1]
= 8 Ω ; LL = 44 μH ; fi = 1 kHz; fs = 48 kHz; Tamb = 25 °C; default settings, unless otherwise specified.
Symbol
Parameter
fSCL
Min
Typ Max
Unit
SCL clock frequency
-
-
400
kHz
tLOW
LOW period of the SCL clock
1.3
-
-
μs
tHIGH
HIGH period of the SCL clock
0.6
tr
Conditions
rise time
tf
fall time
-
-
μs
SDA and SCL signals
[2]
20 + 0.1 Cb -
-
ns
SDA and SCL signals
[2]
20 + 0.1 Cb -
-
ns
[3]
0.6
-
-
μs
tHD;STA
hold time (repeated) START condition
tSU;STA
set-up time for a repeated START condition
0.6
-
-
μs
tSU;STO
set-up time for STOP condition
0.6
-
-
μs
tBUF
bus free time between a STOP and START
condition
1.3
-
-
μs
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
μs
0
-
50
ns
-
-
400
pF
tSP
pulse width of spikes that must be
suppressed by the input filter
Cb
capacitive load for each bus line
[1]
[2]
[3]
[4]
[4]
LBST = boost converter inductance; RL = load resistance; LL = load inductance.
Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
After this period, the first clock pulse is generated.
To be suppressed by the input filter.
SDA
tLOW
tBUF
tr
tf
tHD;STA
tSP
SCL
tHD;STA
P
S
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
Sr
tSU;STO
P
010aaa225
2
Figure 5. I C timing
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
11.5 PDM timing characteristics
Table 10. PDM interface characteristics; see Figure 6
[1]
All parameters are guaranteed for VBAT = 3.6 V; VDDD = 1.8 V; VDDP = VBST = 9.0 V, Adaptive Boost mode; LBST = 1 μH ;RL
[1]
[1]
= 8 Ω ; LL = 44 μH ; fi = 1 kHz; fs = 48 kHz; Tamb = 25 °C; default settings, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
[2]
Max
Unit
-
MHz
fclk
clock frequency
-
3.072
δclk
clock duty cycle
45
-
55
%
th
hold time
after clock HIGH
30
-
-
ns
after clock LOW
30
-
-
ns
after clock HIGH
30
-
-
ns
after clock LOW
30
-
-
ns
tsu
[1]
[2]
set-up time
LBST = boost converter inductance; RL = load resistance; LL = load inductance.
PDM Clock is 64xfs, with fs selected by AUDFS. Typical 3.072 Mhz is corresponding to fs = 48 kHz.
CLK
tsu(CLKH)
tsu(CLKL)
th(CLKH)
th(CLKL)
DATA
010aaa711
Figure 6. PDM timing
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
12 Application information
12.1 Application diagrams
RFVBAT
5.1 Ω
1.8 V
CTRL (I2C)
l2C
CBST
1 nF
INB
VBAT
CVBAT
22 µF
SDA
SCL
AUDIO IN (TDM)
VDDP
DATAIN
VBST
FS
SPK
l2S
BASEBAND
PROCESSOR
CFVBAT
1 µF
VDDD/
VDDE
CVDDD
100 nF
LBST
1 µH
CVDDP
33 µF
BCK
SPKBST (TDM)
TFA9872
DATAO
OUTA
RST
speaker
OUTB
INT
+
-
PDMCLK
AUXSAMP
AUXSAMN
TRSTN
TEST2
TEST1
GNDD
GNDP
GNDB
ADS2
ADS1
PDMDAT
aaa-021842
Figure 7. Typical mono application
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
CTRL (I2C)
LBST 1 µH
CVBAT
22 µF
VBAT
CFVBAT
1 µF
VDDD/
VDDE
CVDDD
100 nF
RFVBAT
5.1 Ω
CBST
1 nF
INB
1.8 V
SDA
l2C
SCL
VDDP
AUDIO IN (TDM)
DATAIN
VBST
FS
SPK
l2S
CVDDP
33 µF
BCK
SPKBST (TDM)
TFA9872
DATAO
BASEBAND
PROCESSOR
OUTA
RST
speaker
INT
OUTB
+
-
PDMCLK
AUXSAMP
AUXSAMN
TRSTN
TEST2
TEST1
GNDD
GNDP
GNDB
ADS2
ADS1
PDMDAT
1.8 V
RFVBAT
5.1 Ω
CVBAT
22 µF
CBST
1 nF
INB
VDDD/
VDDE
CFVBAT
1 µF
LBST 1 µH
VBAT
CVDDD
100 nF
SDA
SCL
VDDP
DATAIN
VBST
FS
CVDDP
33 µF
BCK
TFA9872
DATAO
OUTA
RST
INT
speaker
OUTB
PDMCLK
+
-
AUXSAMP
AUXSAMN
1.8 V
TRSTN
TEST2
TEST1
GNDD
GNDP
GNDB
ADS2
ADS1
PDMDAT
aaa-021843
Figure 8. Typical stereo application (using separated coils)
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
RFVBAT
5.1 Ω
CVDDD
100 nF
CTRL (I2C)
CVBAT
22 µF
VBAT
VDDD/
VDDE
CFVBAT
1 µF
LBST 1 µH
CBST
1 nF
INB
1.8 V
SDA
l2C
SCL
VDDP
AUDIO IN (TDM)
DATAIN
VBST
FS
SPK
l2S
CVDDP
33 µF
BCK
SPKBST (TDM)
TFA9872
DATAO
BASEBAND
PROCESSOR
OUTA
RST
INT
speaker
OUTB
+
-
PDMCLK
AUXSAMP
AUXSAMN
TRSTN
TEST2
TEST1
GNDD
GNDP
GNDB
ADS2
ADS1
PDMDAT
1.8 V
RFVBAT
5.1 Ω
VBAT
VDDD/
VDDE
CFVBAT
1 µF
RHVBAT
1 MΩ
INB
CVDDD
100 nF
SDA
SCL
VDDP
DATAIN
FS
VBST
CVDDP
33 µF
BCK
TFA9872
DATAO
OUTA
RST
INT
speaker
OUTB
PDMCLK
+
-
AUXSAMP
AUXSAMN
TRSTN
TEST2
TEST1
GNDD
GNDP
GNDB
ADS2
ADS1
PDMDAT
1.8 V
aaa-026445
Figure 9. Typical stereo application (using a single coil)
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
RFVBAT
5.1 Ω
1.8 V
LBST
1 µH
CFVBAT
1 µF
CTRL (I2C)
l2C
CBST
1 nF
CVBAT
22 µF
INB
VBAT
VDDD/
VDDE
CVDDD
100 nF
SDA
VDDP
SCL
CVDDP
33 µF
VBST
AUDIO IN (TDM) DATAIN
FS
SPK
l2S
OUTA
BCK
SPKBST (TDM)
speaker
TFA9872
DATAO
OUTB
RST
BASEBAND
PROCESSOR
+
FAUX1 RAUX1
AUXSAMN
INT
CAUX1
100 pF
CAUX2
100 pF
PDMCLK
PDM
SaM (PDM)
PDMDAT
AUXSAMP
+
CAUX3
33 nF speaker
-
TRSTN
TEST2
TEST1
GNDD
GNDP
GNDB
ADS2
ADS1
FAUX2 RAUX2
aaa-021844
The configuration shown also supports speaker playback
Figure 10. Typical SaM application
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
13 Package outline
WLCSP42: wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.50 mm
ball A1
index area
B
E
SOT1459-2
A
A
A2
D
A1
detail X
e1
C
e
ZD1
Øv
Øw
b
G
C A B
C
y
e
F
E
e2
D
C
B
A
ball A1
index area
ZD2
1
2
3
4
5
6
ZE1
X
ZE2
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A
max 0.54
nom 0.50
min 0.46
A1
A2
0.23
0.20
0.17
0.325
0.300
0.275
b
D
E
0.29 3.16 2.49
0.26 3.13 2.46
0.23 3.10 2.43
e
e1
e2
0.4
2.0
2.4
ZD1
ZD2
ZE1
0.365 0.365 0.245
ZE2
0.215
v
w
y
0.05 0.02 0.03
sot1459-2_po
Outline
version
SOT1459-2
References
IEC
JEDEC
JEITA
---
European
projection
Issue date
16-02-25
16-03-01
Figure 11. Package outline TFA9872AUK/N1 (WLSCP42)
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TFA9872_SDS
NXP Semiconductors
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
WLCSP42: wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.525 mm (backside coating included)
ball A1
index area
E
B
SOT1459-3
A
A
A2
D
A1
detail X
e1
C
e
ZD1
Øv
Øw
b
G
C A B
C
y
e
F
E
e2
D
C
B
A
ZD2
1
ball A1
index area
2
3
4
5
6
ZE1
X
ZE2
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A
max 0.565
nom 0.525
min 0.485
A1
A2
0.20
0.33
b
D
E
3.16 2.49
0.26 3.13 2.46
3.10 2.43
e
e1
e2
0.4
2.0
2.4
ZD1
ZD2
ZE1
0.365 0.365 0.245
ZE2
0.215
v
w
y
0.05 0.02 0.03
Note: Backside coating 25 µm
Outline
version
SOT1459-3
sot1459-3_po
References
IEC
JEDEC
JEITA
---
European
projection
Issue date
16-03-01
16-05-09
Figure 12. Package outline TFA9872CUK/N1 (WLCSP42)
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14 Soldering of WLCSP packages
14.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
14.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
14.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 1) than a SnPb process, thus reducing
the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 11.
Table 11. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
3
Volume (mm )
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 1.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
14.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
14.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and
the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the
bumps after reflow can occur during the reflow process in bumps with high ratio of bump
diameter to bump height, i.e. low bumps with large diameter. No failures have been found
to be related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
14.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing
the chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
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Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must
be done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues and/
or underfill removed. When a new chip is placed on the substrate, use the flux process
instead of solder on the solder lands. Apply flux on the bumps at the chip side as well
as on the solder pads on the substrate. Place and align the new chip while viewing with
a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
14.3.4 Cleaning
Cleaning can be done after reflow soldering.
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15 Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TFA9872_SDS v.1
20170412
Product data sheet
-
-
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16 Legal information
16.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
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such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
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Contents
1
2
3
4
5
6
7
7.1
7.2
8
9
10
11
11.1
11.2
11.3
11.4
11.5
12
12.1
13
14
14.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.3.4
15
16
General description ............................................ 1
Features and benefits .........................................2
Applications .........................................................2
Quick reference data .......................................... 3
Ordering information .......................................... 4
Block diagram ..................................................... 5
Pinning information ............................................ 6
Pinning ............................................................... 6
Pin description ................................................... 7
Functional description ........................................9
Limiting values .................................................. 10
Thermal characteristics ....................................10
Characteristics .................................................. 11
DC Characteristics ...........................................11
AC characteristics ............................................13
I2S timing characteristics .................................17
I2C timing characteristics ................................ 18
PDM timing characteristics .............................. 19
Application information .................................... 20
Application diagrams ....................................... 20
Package outline .................................................24
Soldering of WLCSP packages ........................26
Introduction to soldering WLCSP packages .....26
Board mounting ............................................... 26
Reflow soldering .............................................. 26
Stand off .......................................................... 27
Quality of solder joint .......................................27
Rework .............................................................27
Cleaning ...........................................................28
Revision history ................................................ 29
Legal information .............................................. 30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 April 2017
Document identifier: TFA9872_SDS
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