MSC1205

E2C0018-27-Y3 ¡ Semiconductor MSC1205 ¡ Semiconductor This version: Nov. 1997 MSC1205 Previous version: Jul. 1996 32-Bit Duplex Controller/Driver with Digital Dimming Function GENERAL DESCRIPTION The MSC1205 is a Bi-CMOS display driver for a 1/2-duty vacuum fluorescent display tube. It consists of a 64-bit shift register, latch circuits, a digital diming circuit, and drivers. The MSC1205 provides an interface with a microcomputer only by three signal lines: LOAD, DATA, and CLOCK. FEATURES • Power Supply Voltage: 8 to 18V (built-in 5V regulator for logic) • Built-in 1-terminal RC oscillation circuit (with external capacitor) • Built-in digital dimming circuit 10-bit resolution Programmable in the duty range of 0/2048 (0%) to 1015.5/2048 (49.6%). • Can directly drive 32 ¥ 2 display anodes. • Built-in power-on reset circuit • Package options: 42-pin plastic DIP (DIP42-P-600-2.54) (Product name: MSC1205-RS) 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSC1205GS-2K) 1/15 ¡ Semiconductor MSC1205 BLOCK DIAGRAM SEG32 SEG31 GRID1 GRID2 VOLTAGE REGULATOR SEG2 SEG1 VDD VSS DRIVER 8 to 18V 32 bits LEVEL SHIFTER 5V BLANK DOWN COUNTER 10 bits 32 bits TIMING GENERATOR BL MULTIPLEXER ST 5V R (fosc) bo COMPARATOR (bo) 10 bits LATCH OSC OSC (SEGLD) (DIMLD) L LOAD (POR) LOAD TIMING CONTROL LATCH Q1-Q10 Q1-Q64 64 bits 32 bits L L LATCH 32 bits DATA CLOCK D (2 bits) D Q1-Q64 (64 bits) TEST SHIFT REGISTER 2/15 ¡ Semiconductor MSC1205 INPUT AND OUTPUT CONFIGURATION • Schematic Diagrams of Logic Portion Input Circuit 1 VDD (5V Reg.) INPUT VSS VSS • Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input Circuit 2 Circuit 3 VDD (5V Reg.) VDD (5V Reg.) BLANK TEST VSS VSS VSS VSS • Schematic Diagrams of Driver Output Circuit VDD VDD OUTPUT VSS VSS 3/15 ¡ Semiconductor MSC1205 PIN CONFIGURATION (TOP VIEW) DATA 1 CLOCK 2 LOAD 3 SEG1 4 SEG2 5 SEG3 6 SEG4 7 SEG5 8 SEG6 9 SEG7 10 SEG8 11 SEG9 12 SEG10 13 SEG11 14 SEG12 15 SEG13 16 SEG14 17 SEG15 18 SEG16 19 SEG17 20 SEG18 21 42-Pin Plastic DIP 42 VSS 41 TEST 40 OSC 39 BLANK 38 GRID2 37 GRID1 36 VDD 35 SEG32 34 SEG31 33 SEG30 32 SEG29 31 SEG28 30 SEG27 29 SEG26 28 SEG25 27 SEG24 26 SEG23 25 SEG22 24 SEG21 23 SEG20 22 SEG19 4/15 ¡ Semiconductor MSC1205 PIN CONFIGURATION (TOP VIEW) 12 13 14 15 16 17 18 19 20 21 SEG14 SEG15 SEG16 SEG17 SEG18 NC SEG19 SEG20 SEG21 SEG22 NC : No-connection pin 44-Pin Plastic QFP SEG23 22  CLOCK LOAD DATA SEG2 SEG1 TEST 44 43 42 41 40 39 38 VSS NC 37 36 OSC BLANK 35 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 1 2 3 4 5 6 7 8 9 34 GRID2 33 GRID1 32 VDD 31 SEG32 30 SEG31 29 SEG30 28 SEG29 27 SEG28 26 SEG27 25 SEG26 24 SEG25 23 SEG24 SEG10 SEG11 SEG12 SEG13 10 11 5/15 ¡ Semiconductor MSC1205 PIN DESCRIPTION Symbol Type DATA CLOCK LOAD SEG1 -SEG32 VDD GRID1 I I I O Description Serial data input pin. This pin receives display data, dimming data, enable bit and mode bit. Shift clock input pin with Schmitt circuit. Serial data is clocked in this pin at the rising edge of the shift clock pulse. Load pulse input pin. The load signal is input when dimming data and segment data transfer is finished. Segment driver output pins. These pins provide large current driving (IOH = –5.5mA at VDD = 12V) and small current driving (IOH = –1.8mA at VDD = 12V). Power supply voltage. This pin is connected to a power supply of 8 to 18V. Grid driver output pin. When this pin is set to "L", the display is turned on. This pin is connected to external PNP transistor. The segment data of the first bit (S1) to the 32nd bit (S32) is valid in the segment data of 64 bits. Grid driver output pin. When this pin is set to "L", the display is turned on. This pin is connected to external PNP transistor. The segment data of the 33rd bit (S33) to the 64th bit (S64) is valid in the segment data of 64 bits. Display blank input pin with a pull-up resistor. When this pin is set to "L", the display is turned off (SEGn = "L") Oscillation input pin. This pin is connected to an external capacitor of 82pF. A standard oscillation frequency is 512kHz. Test input pin with a pull-down resistor. Normally this pin should be left open or should be connected to ground. Ground pin. This pin is connected to ground (VSS = 0) — O GRID2 O BLANK OSC TEST VSS I I I — 6/15 ¡ Semiconductor MSC1205 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Input Voltage Storage Temperature Range Symbol VDD VIN TSTG Condition Ta = 25°C Ta = 25°C — Rating –0.3 to +20 –0.3 to +6.0 –65 to +150 Unit V V °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Range Symbol VDD Top Condition — — Range 8 to 18 –40 to +85 Unit V °C ELECTRICAL CHARACTERISTICS DC Characteristics (Ta = –40 to +85˚C, VDD = 8 to 18V) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Symbol VIH VIL IIH1 IIH3 Low Level Input Current IIL1 IIL2 IIL3 High Level Output Voltage (1) (Small Current Driver) High Level Output Voltage (2) (Large Current Driver) Low Level Output Voltage VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOL1 VOL2 VOL3 High Level Output Voltage (3) Current Consumption VOH7 IDD Condition — — VI = 5V VI = 5V VI = 0V VI = 0V VI = 0V VDD = 9.5V, IOH1 = –1.3mA VDD = 12V, IOH2 = –1.8mA VDD = 15V, IOH3 = –2.3mA VDD = 9.5V, IOH4 = –4.1mA VDD = 12V, IOH5 = –5.5mA VDD = 15V, IOH6 = –7.0mA VDD = 9.5V, IOL1 = 1mA VDD = 9.5V, IOL2 = 500mA VDD = 9.5V, IOL3 = 2mA VDD = 9.5V, IOH7 = –0.8mA fOSC = 512kHz, no load Min. 3.8 –0.3 –1 — –1 –500 –1 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 — — — VDD-0.5 — Max. 5.5 0.8 1 500 1 –100 1 — — — — — — 4 2 0.3 — 20 Unit V V mA mA mA mA mA V V V V V V V V V V mA GRID1, GRID2 — SEG1-SEG32 GRID1, GRID2 SEG (2n-1) n = 1-16 Applicable pin — — DATA, LOAD CLOCK TEST DATA, LOAD CLOCK BLANK TEST SEG (2n) n = 1-16 7/15 ¡ Semiconductor AC Characteristics MSC1205 (Ta = –40 to +85˚C, VDD = 8 to 18V) Parameter Clock Frequency Clock Pulse Width Clock Rise/Fall Time DATA Setup Time DATA Hold Time Clock Æ Load Time Load Æ Clock Time Load Pulse Width SEGn Rise/Fall Time Grid Frequency Oscillation Frequency Large Current Small Current Symbol fC(1/tclock) tCW tcr, tcf tDS tDH tCL tLC tLW tr, tf tr, tf fGRID fOSC Condition — — — — — — — — CL = 20pF CL = 20pF CL = 82pF±5% Min. — 500 — 200 200 100 50 1.3 0 0 150 307.2 Typ. — — — — — — — — 4/120 15/120 250 512 Max. 1 — 500 — — — — — 400 400 350 716.8 Unit MHz ns ns ns ns ns ns ms ns ns Hz kHz DATA CLOCK LOAD SEGMENT DATA DIMMING DATA 3.8V DATA tDS tDH fC tCW CLOCK tCL tcr LOAD tr SEGn GRIDn tf 0.9VDD 0.1VDD tLW tcf tLC 3.8V 0.8V tCW 3.8V 0.8V 0.8V 8/15 ¡ Semiconductor MSC1205 FUNCTIONAL DESCRIPTION DATA Input This device uses 10-bit dimming and 64-bit segment data. In order to transfer this data, the enable bit (M0) and mode bit (M1) should be set to an initial state. The data format is shown below. M0 M1 D1 D2 D10 M0 M1 S1 S2 S63 S64 DATA CLOCK Figure 1. Data Transfer Timing M0 : This bit is an enable bit. M0 = "0" : Subsequent data is disabled; preceding data is held. M0 = "1" : The beginning of data transfer. The following data is clocked in sequentially. M1 : This bit is used to select the mode. M1 = "0" : Subsequent data is handled as the segment data. M1 = "1" : Subsequent data is handled as the dimming data. D1 : LSB of dimming data. S1 : data for grid1 of SEG1. S2 : data for grid1 of SEG2. . . . S32 : data for grid1 of SEG32. S33 : data for grid2 of SEG1. . . . S64 : data for grid2 of SEG32. Notes: 1. Be sure to set the enable bit to "1" before data is transferred. Data following M0 is handled to be enable. If data is input with the enable bit not set to "1", the first "1" data coming next is handled as the enable bit. 2. If the number of the data bits applied is greater (for example, 67 bits are applied for the segment data of 64 bits), the data bits are pushed out in the same order that they are applied, and thus S1, S2, and S3 are ignored. 3. If the number of the data bits applied is smaller (for example, 62 bits are applied for the segment data of 64 bits), S63 and S64 prior to data transfer are shifted to S1 and S2 respectively. 9/15 ¡ Semiconductor CLOCK Input DATA is shifted at the rising edge of the clock. LOAD Input MSC1205 The contents of the shift register are shifted in while the LOAD input is "H" and latched at "H" to "L" transition. The LOAD signal is reproduced in the VF driver for the latch pulse for dimming data and segment data. After 10-bit dimming data and 64-bit segment data are transferred, input the LOAD signal prior to the next clock. Blank Function A low-level voltage at the BLANK pin turns the display off (segment output = "L"). When segment data transfer is finished, the display is turned on. The relationship between this data transfer and the display is shown in Figure 2. Initial Setting When powered on (i.e., when the segment data has never been transferred) the display is turned off (the segment output is "L"). When segment data transfer is finished, display is turned on. The relationship between this data transfer and the display is shown in Figure 2. VDD DATA LOAD Display OFF Display ON DIMMING DATA SEGMENT DATA SEGn Figure 2. Relationship Between Data Transfer and Display 10/15 ¡ Semiconductor MSC1205 If the segment data is transferred before the dimming data is transferred after powered on, the display is turned on at the completion of segment data transfer, with undefined dimming values. The relationship between data transfer and display is shown in Figure. 3. VDD DATA SEGMENT DATA DIMMING DATA LOAD Display OFF Dimming value is undefined Display ON SEGn Figure 3. Relationship Between Advance Transfer of Segment Data and Display Oscillator Connect an external capacitor (C), as shown in Figure 4. The oscillating frequency fOSC depends on the external capacitor used. The following equation is true between fOSC and grid frequency (fGRID): fGRID = fOSC/2048 Terminal fOSC C (82pF) Figure 4. Oscillation Equivalent Circuit 11/15 ¡ Semiconductor MSC1205 Dimming Function The duty cycle of grid output can be changed in 1/2048 step with respect to 10-bit dimming data. Table 1 shows the relationship between dimming data and duty ratio. Table 1. Dimming Data and Duty Ratio (MSB) dimming data (LSB) 00 00 11 11 11 0000 0000 1111 1111 1111 0000 0001 0111 1000 1110 Duty ratio 0/2048 1/2048 1015/2048 1015.5/2048 1015.5/2048 Max ~ ~ ~ ~ ~ ~ ~ Æ ~ Max Note: Setting for address 3FFH is invalid. Duty ratios are programmable within the range of 0/2048 (0%) to 1015.5/2048 (49.6%). 12/15 ¡ Semiconductor MSC1205 APPLICATION CIRCUIT SEG1-SEG32 45 SEG1 SEG2 1 2 3 CPU DATA CLOCK LOAD GRID1 37 GRID2 38 VFD 35 SEG32 MSC1205 40 OSC VSS 42 VDD 36 82pF 13/15 ¡ Semiconductor MSC1205 PACKAGE DIMENSIONS (Unit : mm) DIP42-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.20 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/15 ¡ Semiconductor MSC1205 (Unit : mm) QFP44-P-910-0.80-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/15