MSM6896

E2U0022-28-81 ¡ Semiconductor MSM6895/6896 ¡ Semiconductor Multi-Function PCM CODEC This version: Aug. 1998 MSM6895/6896 Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM6895/MSM6896, developed especially for low-power and multi-function applications in ISDN telephone terminals, are single +5 V power supply CODEC LSI devices. The devices consist of the analog speech paths directly connectable to a handset, the calling circuit directly connectable to a piezosounder, the push-button key scanning interface between push buttons and control processors, the dial tone generator, the B-channel interface, the CODEC, and the processor interface. The functions can be controlled via the 8-bit data bus. FEATURES • Single +5 V Power Supply • Low Power Dissipation Power ON Mode : 20 mW Typ. 53 mW Max. CODEC Power Down Mode : 10 mW Typ. 21 mW Max. • In compliance with ITU-T’s companding law m-law : MSM6895 A-law : MSM6896 • Transmission clocks Continuous CLK : 64, 128, 256 kHz Burst CLK : 192, 384, 768, 1536, 2048 kHz • Built-in PLL • Built-in Reference Voltage Supply • Ringing Tone : Controlled by processor, 9 modes • Ringing Tone Combination : Controlled by processor, 6 modes • Information Tone : Controlled by processor, 9 modes • Built-in PB Tone Generator • B-Channel Selectable • General Latch Output for Speech path Control : 4 bits • Watchdog Timer : 500 ms • Key Scanning I/O Output : 5 bits Input : 8 bits • Direct Connection to Handset • Built-in Preamplifier for Loudspeaker • Handfree Interface • Digital and Analog Interface for the phone-conference speech paths • Package: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM6895GS-BK) (Product name : MSM6896GS-BK) 1/43 ¡ Semiconductor MSM6895/6896 BLOCK DIAGRAM TMX1I TPAO TPBI MLDY TMX2I T2O T1O CAI TEST CK1536 TEST CHANNEL SELECTOR B1T B1R B2T B2R BR1 BT1 BR2 BT2 CK8 CK64 F-TONE GEN R-TONE GEN SW0 SW1 RMI RMO0 B1 B2 M TPAI SW & MIX AIN CODEC AOUT PLL CAO R1I R2I HANDSET SW & MIX RPO 8K 64K + – SW RMO1 DTMF TONE GEN MPU INTF. WR RD CE RESET 8BIT Data Bus AD0 AD1 INTT LA ~ LD TIME 4BIT LOSS LML SP SPO SW & MIX S-TONE GEN LATCH SA0 SA1 BUZZER SGGEN VSG VA VD VAG VDG PO0 ~ VSGC PO4 0 1 2 3 4 0 1 2 3 45 SCANNING OUTPUT KEY INTF. KEY DATA INPUT SW CONT. PI0 to PI7 67 SWITCH HOOK PUSH-BOTTON SWITCH 2/43 ¡ Semiconductor MSM6895/6896 PIN CONFIGURATION (TOP VIEW) 77 RESET 78 TIME 79 LML 76 BR2 75 BR1 72 B2R 71 B1R LB 1 LC 2 LD 3 SW0 4 SW1 5 VDG 6 VAG 7 SA0 8 SA1 9 NC 10 RM1 11 NC 12 RMO0 13 RMO1 14 SPO 15 RPO 16 R2I 17 R1I 18 NC 19 NC 20 TMX2I 21 MLDY 22 TPBI 23 TMX1I 24 66 WR 68 CE 65 AD1 64 VD 63 AD0 62 DB7 61 DB6 60 DB5 59 DB4 58 DB3 57 DB2 56 DB1 55 DB0 54 INTT 53 PI7 52 PI6 51 PI5 50 PI4 49 PI3 48 PI2 47 PI1 46 PI0 45 PO4 44 PO3 43 PO2 42 PO1 41 PO0 74 BT2 73 BT1 70 B2T 69 B1T CK64 38 67 RD 80 LA VSG 26 TPAO 27 VSGC 34 TEST 36 CK1536 37 CK8 39 T1O 28 T2O 29 NC 31 NC 30 VA 32 CAI 33 CA0 35 NC : No connect pin 80-Pin Plastic QFP LOSS 40 TPAI 25 3/43 ¡ Semiconductor MSM6895/6896 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol LB LC LD SW0 SW1 VDG VAG SA0 SA1 — RMI — RMO0 RMO1 SPO RPO R2I R1I — — TMX2I MLDY TPBI TMX1I TPAI VSG TPAO T1O T2O — Type DO DO DO DI DI — — DO DO — AI — AO AO AO AO AI AI — — AI AI AI AI AI AO AO AO AO — Description Data Latch Output B Data Latch Output C Data Latch Output D Sounder Tone Select (1) Sounder Tone Select (2) Digital Ground Analog Ground Sounder Output (+) Sounder Output (–) NC Receive Main Amp Input NC Receive MainAmp Output (+) Receive MainAmp Output (–) Speaker Pre-Amp Output Receive Pre-Amp Output Receive Addition Signal Input Receive Signal Input NC NC Transmit Addtion Signal Input (2) Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol — VA CAI VSGC CAO TEST CK1536 CK64 CK8 LOSS PO0 PO1 PO2 PO3 PO4 PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 INTT DB0 DB1 DB2 DB3 DB4 DB5 Type — — AI AO AO DI DI DI DI DO DO DO DO DO DO DI DI DI DI DI DI DI DI DO I/O I/O I/O I/O I/O I/O NC Description +5 V Analog Power Supply Analog Signal Input to CODEC Bypass Capacitor for Signal Ground Analog Signal Output from CODEC Control Input for Test Clock Input for Test Transmission Colck Input Frame Synchronous Clock Input Howler Tone Control Signal Key Scanning Signal Output (0) Key Scanning Signal Output (1) Key Scanning Signal Output (2) Key Scanning Signal Output (3) Key Scanning Signal Output (4) Key Scanned Data Input (0) Key Scanned Data Input (1) Key Scanned Data Input (2) Key Scanned Data Input (3) Key Scanned Data Input (4) Key Scanned Data Input (5) Key Scanned Data Input (6) Key Scanned Data Input (7) Interrupt Output Data Bus (0) Data Bus (1) Data Bus (2) Data Bus (3) Data Bus (4) Data Bus (5) Hold Tone Input Transmit Pre-Amp (B) Input Transmit Addtion Signal Input (1) Transmit Pre-Amp (A) Input Signal Ground Transmit Pre-Amp (A) Output Transmit Signal Output (1) Transmit Signal Output (2) NC 4/43 ¡ Semiconductor MSM6895/6896 PIN DESCRIPTION (Continued) Pin 61 62 63 64 65 66 67 68 69 70 Symbol DB6 DB7 AD0 VD AD1 WR RD CE B1T B2T Type I/O I/O DI — DI DI DI DI DO DO Description Data Bus (6) Data Bus (7) Address Data (0) +5 V Digital Power Supply Address Data Input (1) Write Signal Input Read Signal Input Chip Enable B1 Channel Transmit Output B2 Channel Transmit Output Pin 71 72 73 74 75 76 77 78 79 80 Symbol B1R B2R BT1 BT2 BR1 BR2 RESET TIME LML LA Type DI DI DI DI DO DO DI DO DO DO Description B1 Channel Recive Input B2 Channel Recive Input B Channel Selector Transmit Data (1) B Channel Selector Transmit Data (2) B Channel Selector Receive Data (1) B Channel Selector Receive Data (2) Reset Input Timer Output Hold Tone Control Output Data Latch Output (A) 5/43 ¡ Semiconductor MSM6895/6896 PIN AND FUNCTIONAL DESCRIPTIONS LA, LB, LC, LD General latch outputs for external control. Statuses of these outputs are controlled via the processor interface. Refer to the description of the control data for details. SW0, SW1 External control signal inputs for setting the tone combination of the ringing tone. When the external control for setting the tone combination is selected, the tone combination is set by these pins. SW0 0 0 1 1 SW1 0 1 0 1 Tone combination 1 Tone combination 2 Tone combination 3 Tone combination 1 Wambling Cycle 16 Hz 16 Hz 8 Hz 16 Hz f1 1000 Hz 800 Hz 800 Hz 1000 Hz f2 1333 Hz 1000 Hz 1000 Hz 1333 Hz 1 / f1 1 / f2 Wambling Cycle Time VDG Digital Ground. VAG Analog Ground. 6/43 ¡ Semiconductor SA0, SA1 MSM6895/6896 Sounder (ringing tone) driving outputs. The output signal on SA1 is inverted against the signal on SA0. The sounder circuit can be easily configured by connecting a piezo-sounder between SA0 and SA1. Through processor control, the ringing tone volume is selectable from four levels and one of six tone combinations is selectable. Initially, the ringing tone volume is set at a maximum and the tone combination is set externally. If these pins are used with no-load, tone volume cannot be controlled. When tone volume control is required, a load resistor must be connected between SA0 and SA1. RMI, RMO0, RMO1 Receive main amplifier input and outputs. RMI is the main amplifier input and RMO0 and RMO1 are the main amplifier outputs. The output signal on RMO1 is inverted against RMO0, so the earphone of a piezo electric-type handset is directly connected between RMO0 and RMO1. The RMI input pin is connected to the receive preamplifier output pin (RPO). If the adjusting of receive path frequency characteristics is required, insert the following circuit for adjustment. During initial setting, the speech path from RMI to RMO0 and RMO1 is disconnected and the output of RMO0 and RMO1 is at the VSG level (VA/2). The speech path is provided by processor control. A circuit example for adjustment of frequency characteristics RPO R1 C2 RMI VSG C1 R2 SPO Output of preamplifier for speaker. Since the driving capability is 2.4 VPP for the load of 20 kW, SPO can not directly drive a speaker. During initial setting, SPO is in a non-signal state (VSG level), and a speech signal, RTONE0, RTONE1, FTONE, hold acknowledge tone, and PB signal acknowledge tone are output through processor control. 7/43 ¡ Semiconductor R1I, R2I, RPO MSM6895/6896 Receive preamplifier inputs and output. R1I and R2I are for the inputs and RPO is for the output of the receive preamplifier. Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO), and R2I is used as the mixing signal input pin. During initial setting, the RPO output is in non-signal state (VSG level), and speech signal, RTONE1, RTONE2, FTONE, PB acknowledge tone, and side tone signal are output through processor control. And if the three-party speech function is required, the R2I pin is connected to the analog output of the other CODEC. MLDY Hold tone signal input. This pin is connected to the output of external melody IC. Through processor control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path. TPBI Transmit signal input. When the handset is used, TPBI is connected to the transmit preamplifier output pin (TPAO). If adjustment of frequency characteristics on the transmit path is required, insert a circuit for adjustment of characteristic between TPAO and TPBI. Through processor control, the signal applied to this pin is output via the T1O and T2O pins on the transmit path output and its side tone via the RPO pin. A circuit example for adjustment of frequency characteristics TPAO TPBI VSG R3 C4 C3 R4 TMX1I, TMX2I Transmit addition signal inputs. Through processor control, the input signals to TMX1I and TMX2I are added to the transmit signal and are output to T1O and T2O respectively. 8/43 ¡ Semiconductor TPAI, TPAO MSM6895/6896 The transmit preamplifier input and output. TPAI is the input and TPAO is the output. Connect TPAI to the microphone of handset via an ACcoupling capacitor if the DC offset appears at a transmit signal (offset from SGT). The transmit path from TPAI to TPAO is always established regardless of processor control. VSG Signal ground level output. The output level is equal to a half of the power supply voltage. VSGC Bypass capacitor connecting pin for signal ground level. Insert a 0.1 mF capacitor with good higher frequency characteristic, between VSGC and VAG. VA, VD +5 V power supply. VA is for an analog circuit and VD is for digital supply. Connect both VA and VD to the +5 V analog path of the system. CAI CODEC analog output. Connect CAI to T1O. CAO CODEC analog output. Connect CAO to R1I via an AC-Coupling capacitor. 9/43 ¡ Semiconductor TEST, CK1536 MSM6895/6896 External master clock inputs. Since the MSM6895 and MSM6896 contain PLL internally, the external clock signal is eliminated. But the device can operate with the external clock through these pins. When these pins are not used, leave these pins open or at 0 V. Mode Internal PLL External master clock TEST pin 0V Digital "1" CK1536 pin open or 0 V Input the signal of 1536 kHz When the external clock is used, the CK1536 signal is required to be synchronized in phase with the CK8 signal. CK64 CODEC PCM data input and output shift clock input. When the continuous clock is set, the frequency is one of 64 kHz, 128 kHz, and 256 kHz. When the burst clock is used, one of 192, 384, 768, 1536, and 2048 kHz is available. If the BCLOCK signal is not applied, PLL is out of synchronization and goes into the self-running mode. CK8 Synchronous signal input. CODEC PCM data is sent out sequencially from MSB at the rising edge of the CK64 signal in synchronization with the rise of the synchronous signal. PCM data should be entered from MSB in synchronization with the rise of the synchronous signal. PCM data is shifted in at the falling edge of the CK64 signal. Since the CK8 signal is used for a trigger signal for PLL and for a clock signal to the tone generator, if this signal is not applied, not only any tone can not be output, but also PLL goes out of synchronization and goes into self-running mode. This signal has to be synchronous with the CK64 signal and its frequency must be within 8 kHz ± 50 ppm to ensure the CODEC AC characteristics (mainly frequency characteristics). LOSS Signal output for controlling the external circuits. When the howler tone of sounder is selected through processor control, the output is in a digital "1". Initially, this output is set to a digital "0". 10/43 ¡ Semiconductor PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7 MSM6895/6896 Key scanning outputs. These output pins need external pull-up resistors because of their open- drain circuits. Through processor control, these outputs can be set open or to digital "0". Initially, these outputs are set at an opened state. PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7 Key scanning inputs. In the READ mode, data on PI0 to PI7 can be read out of the processor via data bus (DB0 to DB7). INTT Interrupt signal output to the processor. INTT outputs interrupt signals (digital "0") at intervals of 8 ms by the interrupt release control signal from the processor. INTT does not output any signal while no CK8 signal is input. Interrupt release signal from processor t < 8 ms 8 ms < t < 16 ms t < 8 ms INTT output 8 ms 16 ms 8 ms DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7 Data bus inputs and outputs. 11/43 ¡ Semiconductor AD0, AD1 MSM6895/6896 Address data inputs for the internal control registers. Addressing of the internal control registers is executed by AD0 and AD1 and sub address data, DB7 and DB6. AD1 0 0 0 0 Write 0 1 1 1 1 1 Read 1 AD0 0 0 0 0 1 0 1 1 1 1 0 DB7 0 0 1 1 — — 0 0 1 1 — DB6 0 1 0 1 — — 0 1 0 1 — Sounder Control Control of function key acknowledge tone PB tone control Control of the internal control latch and the general-purpose latch, Reset control of the watch dog timer. Control of channel selector Key scanning output control, interrupt release control Volume control and tone combination control of sounder CODEC power down control Level control of transmit path, PB tone, and Hold tone, Gain control of receive path Frequency control of howler tone Read of the key scanning data Function WR Write signal for internal control registers. Data on the data bus is written into the registers at the rising edge of WR under the condition of digital "0" of CE (Chip Enable). While CE is in digital "1" state, WR becomes invalid. The Write cycle is a minimum of 2 ms, but if the CK64 and CK8 signals are silent, the write cycle requires a minimum of 50 ms. A minimum of 2 ms specified as the write cycle is valid 10 ms after CK64 and CK8 signals are input. RD Read signal input to read PI0 to PI7 out of the processor. When CE and RD are in digital "0" state, the digital values on PI0 to PI7 are output onto the data buses DB0 to DB7. While CE is in digital "1" state, the RD signal becomes invalid. 12/43 ¡ Semiconductor CE Chip Enable signal input. When CE is in digital "0" state, WR and RD are valid. MSM6895/6896 B1T, B2T, B1R, B2R B channel interface inputs and outputs. B1T and B2T are outputs, and B1R and B2R are inputs. Through channel control by the processor, various data paths are set. The CODEC input and output signals are input and output via these pins. Initially the B1T and B2T outputs are fixed in a digital "1", and the B1R and B2R inputs are neglected. BR1, BR2, BT1, BT2 External digital inputs and outputs to the B-channel. BR1 and BR2 are outputs, and BT1 and BT2 are inputs. Through channel control by processor, the digital paths are set between these input and output pins and the B channel. These signals are applied to another CODEC interface of three-party the speech path and to the interface of 64 kbps at the rate adaptor circuit. Initially the BR1 and BR2 outputs are fixed in a digital "1", and the BT1 and BT2 inputs are neglected. RESET Reset signal input. Digital "0" input to RESET makes all of internal control registers to be initialized. When powered on, this RESET signal should be input for initializing the system. TIME Watchdog timer output. When the processor does not reset the timer, the 500 ms period (Digital "0" : 4 ms) digital signal is continuously output. When RESET is at digital "0", this timer is reset. And, in about 500 ms after RESET goes to digital "1", the first timer output signal is issued and then the timer signal is output at intervals of a 500 ms. If the CK8 signal is not input, the TIME signal is not output. LML Control signal output for external hold tone generator. LML goes to digital "1" state when the hold tone transmit mode on transmit path or the hold acknowledge tone mode on receive path is selected. During initialized state, LML is in digital "0" state. 13/43 ¡ Semiconductor MSM6895/6896 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition VAG, VDG = 0 V VAG, VDG = 0 V VAG, VDG = 0 V — Rating 0 to 7 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Digital Input Rise Time Digital Input Fall Time Digital Output Load Symbol VD Ta VIH VIL tIr tIf RDL CDL Condition VA, VD (Voltage must be fixed) — All Digital Input Pins All Digital Input Pins All Digital Input Pins All Digital Input Pins PO0 to PO4 Output Min. 4.75 –10 2.2 0 — — 10 — Typ. 5.0 +25 — — — — — — Max. 5.25 +70 VDD 0.8 50 50 — 100 Unit V °C V V ns ns kW pF Recommended Operating Conditions (CODEC Digital Interface) Parameter Clock Frequency Sync Pulse Frequency Clock Duty Ratio Symbol FC FS DC tXS Sync Pulse Setting Time tSX Sync Pulse Width Data Setup Time Data Hold Time Allowable Jitter Width tWS tDS tDH — Condition CK64 CK8 CK64 CK64ÆCK8 See Fig.1 CK8ÆCK64 See Fig.1 — B1R, B2R B1R, B2R CK8 Min. — — 40 — — 1 CK64 100 100 — Typ. 64 128 256 8.0 50 — — — — — — — 60 100 100 100 — — 500 kHz % ns ns ms ns ns ns — kHz Max. Unit 14/43 ¡ Semiconductor Recommended Operating Conditions (Processor Digital Interface) Parameter Write Pulse Period Write Pulse Width Read Pulse Width Address Data Setup Time Address Data Hold Time CE Setup Time CE Hold Time Data Setup Time Data Hold Time Reset Pulse Width Symbol PW TW TR tAW1 tAR1 tAW2 tAR2 tCW1 tCR1 tCW2 tCR2 tDW1 tDW2 tWRES WR WR RD AD0, AD1ÆWR AD0, AD1ÆRD WRÆAD0, AD1 RDÆAD0, AD1 CEÆWR CEÆRD WRÆCE RDÆCE DB0 to 7ÆWR WRÆDB0 to 7 RESET See Fig.2 Condition Min. 2000 100 200 10 80 50 10 10 80 50 10 110 20 100 Typ. — — — — — — — — — — — — — — MSM6895/6896 Max. — — — — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Recommend Operating Conditions (Analog Interface) Parameter Symbol TPAI TPBI TMX1I, TMX2I (Transmit Gain: Typ.) Analog Input Voltage VAIN MLDYI (Transmit Gain: Typ.) R1I, R2I (Transmit Gain: Typ.) RMI CAI TPAO, T1O, T2O, Analog Load Resistance RAL RPO, SPO, CAO RMO0, RMO1 Analog Load Capacitance CAL TPAO, T1O, T2O, RPO, SPO, CAO RMO0, RMO1 TPAI, TPBI, RMI Allowable Analog Input Offset Voltage Voff MLDYI, TMX1I, TMX2I R1I, R2I CAI Condition Min. — — — — — — — 20 3 — — –10 –50 –25 –100 Typ. — — — — — — — — — — — — — — — Max. 0.24 0.31 2.40 1.90 1.20 0.51 2.40 — — 100 55 +10 +50 +25 +100 mV pF nF kW VPP Unit 15/43 ¡ Semiconductor MSM6895/6896 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 IDD4 Input High Voltage Input Low Voltage High Input Leakage Current Low Input Leakage Current Digital Output High Voltage Digital Output Low Voltage Digital Output Leakage Current Analog Output Offset Voltage Input Capacitance Analog Input Resistance VIH VIL IIH IIL VOH VOL IO Voff CIN RIN Condition Operating Mode (No Signal, Sounder OFF) CODEC Receive Power Down CODEC Transmit Power Down CODEC Transmit/Receive Power Down — — — — IOH = 0.4 mA IOH = 1 mA IOL = –1.6 mA — TPAO, T1O, T2O, CAO, RPO, RMO1, RMO2, SPO — TPAI, TPBI, MLDYI, RMI TMX1I, TMX2I, R1I, R2I CAI (fin : < 4 kHz) VSG Voltage VSG Drive Current — ISGF ISGS — FORCE Current SINK Current Min. — — — — 2.2 0.0 — — 2.4 3.8 0.0 — –100 — — 10 — VA/2 –0.05 1.0 0.3 Typ. 3.9 3.3 2.8 2.2 — — — — — — — — — 5 10 — 1 VA/2 1.5 0.5 Max. 10.0 8.0 7.0 4.0 VDD 0.8 2.0 0.5 VDD VDD 0.4 10 +100 — — — — VA/2 +0.05 — — Unit mA mA mA mA V V mA mA V V mA mV pF MW kW MW V mA 16/43 ¡ Semiconductor AC Characteristics 1 (CODEC) MSM6895/6896 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Freq. Level (Hz) (dBm0) Loss T1 Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Loss R3 Loss R4 Loss R5 SD T1 SD T2 SD T3 SD T4 SD T5 SD R1 SD R2 SD R3 SD R4 SD R5 GT T1 GT T2 GT T3 GT T4 GT T5 GT R1 GT R2 GT R3 GT R4 GT R5 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 Condition Min. 20 –0.15 0 –0.15 –0.15 0.0 –0.15 –0.15 –0.15 0.0 35 35 35 29 28 24 23 37 37 37 31 30 26 25 –0.3 –0.3 –0.6 –1.5 –0.2 –0.2 –0.4 –0.8 Typ. 27 +0.07 Reference –0.03 +0.06 0.38 –0.03 Reference –0.02 +0.15 0.56 43.0 41.0 38.0 31.0 26.5 43.0 41.0 40.0 34.0 31.0 +0.01 Reference +0.13 +0.32 +0.64 0.0 Reference –0.06 –0.20 –0.27 Max. — +0.20 +0.20 +0.20 0.80 +0.20 +0.20 +0.20 0.80 — — — — — — — — — — +0.3 +0.3 +0.6 +1.5 +0.2 +0.2 +0.4 +0.8 dB dB Unit Transmit Frequency Response Receive Frequency Response 0 dB Transmit Signal to Distortion Ratio 1020 3 0 –30 –40 –45 3 0 –30 –40 –45 3 –10 –40 –50 –55 3 –10 –40 –50 –55 *1 *2 *2 dB Receive Signal to Distortion Ratio 1020 *1 *2 *2 dB Transmit Gain Tracking 1020 Receive Gain Tracking 1020 dB Notes: *1 Psophometric filter is used *2 Upper is specified for the MSM6895, lower for the MSM6896 17/43 ¡ Semiconductor AC Characteristics 1 (CODEC) (Continued) MSM6895/6896 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Freq. Level (Hz) (dBm0) Nidle T Idle Channel Noise Nidle R Absolute Amplitude Absolute Delay Time AV T AV R Td tgd T1 tgd T2 tgd T3 tgd T4 tgd T5 tgd R1 tgd R2 tgd R3 tgd R4 tgd R5 CR T CR R DIS S IMD PSR T PSR R — 1020 1020 500 600 1000 2600 2800 500 600 1000 2600 2800 1020 4.6 kHz to 72 kHz Condition AIN = SG *1 *1 *3 Transmit CODEC Receive CODEC A to A CK64 = 64 kHz *2 Min. — — 0.5671 0.5671 — — — — — — — — — — — 66 70 30 — — — Typ. –73.5 –71 –77.8 0.6007 0.6007 0.58 0.19 0.12 0.02 0.05 0.08 0.0 0.0 0.0 0.09 0.12 86 78 32.0 –37.5 –52 30 Max. –70 –69 Unit — — — 0 0 dBmOp –74 0.6363 0.6363 0.60 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 — — — –35 –35 — Vrms ms Transmit Group Delay 0 *4 ms Receive Group Delay 0 *4 ms Crosstalk Attenuation Discrimination Out-of-band Signal Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio 0 –25 0 –4 100 mVpp Transmit Æ Receive Receive Æ Transmit 0 to 4000 Hz 4.6 kHz to 100 kHz 2fa–fb *5 dB dB dBmO dBmO dB 300 to 3400 fa = 470 fb = 320 0 to 50 kHz Notes: *1 Psophometric filter is used *2 Upper is specified for the MSM6895, lower for the MSM6896 *3 PCM data for MSM6895: All "1" PCM data for MSM6896: "11010101" *4 Minimum value of the group delay distortion *5 The measurement under idle channel noise 18/43 ¡ Semiconductor AC Characteristics 2 (Transmit Path) MSM6895/6896 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Pre-Amp Gain Transmit Path 1 Gain Transmit Path 2 Gain Transmit Addition Signal 1 Gain Transmit Addition Signal 2 Gain Symbol GTPA Freq. (Hz) 1020 1020 1020 — — Level (dBV) –24.4 –22.1 –4.4 — — Condition TPAI-TPAO TPBI-T1O TPBI-T2O TMX1I-T1O TMX1I-T2O T1O T2O For Set at typical gain Set at typical gain – 3 dB – 6 dB Min. 18.0 15.7 15.7 –2.0 –2.0 Typ. Max. 20.0 17.7 17.7 0.0 0.0 22.0 19.7 19.7 +2.0 +2.0 Unit dB dB dB dB dB dBV dBV dB dB % dB GTPB1 GTPB2 GTMX1 GTMX2 VPBT1 –17.4 –15.4 –13.4 –17.4 –15.4 –13.4 –5.0 –8.0 –0.9 — –4.0 –4.0 –5.0 –8.0 — — 2.4 –3.0 –6.0 — –35 –2.0 –2.0 –3.0 –6.0 –93 –91 — –1.0 –4.0 +0.9 –30 0.0 In-Channel PB Signal Output Level VPBT2 GPBT1 In-Channel PB Signal Output Level Setting In-Channel PB Signal Frequency Deviation In-Channel PB Signal Distortion — — typical setting GPBT2 DfPBT THDPBT GPAT1 — — — — T1O, T2O In-Band Distortion MLDYI-T1O Set at Hold Tone Path Gain 1020 –22.4 typical MLDYI-T2O gain For –3 dB –6 dB 0.0 –1.0 –4.0 — — — dB GPAT2 RG1 PAT Hold Tone Path Gain Setting 1020 –22.4 dB dB dBV dBV VPP typical setting RG2 PAT Ni TPA Idle Channel Noise — — — — — — TPAI: 510 W at termination Meature at TPAO *6 T1O, T2O TPAO, T1O, *6 Ni TPB Maximum Output Voltage Swing VOT T2O, RL = 20 kW Note: *6 Noise band width: 0.3 kHz to 3.4 kHz, non-weighted 19/43 ¡ Semiconductor AC Characteristics 3 (Receive Path) MSM6895/6896 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Receive Main Amp. Gain Receive Main Amp. Output Gain Difference Receive Main Amp. Output Phase Difference Receive Signal Path Gain Symbol GRMO0 GRMO1 DGRMO DPRMO GRPA RG RPA1 Receive Signal Path Gain Setting RG RPA2 RG RPA3 Receive Addition Signal Path Gain Receive Addition Signal Path Gain Setting GRPB RG RPB1 RG RPB2 RG RPB3 1020 –14.4 1020 –14.4 1020 –23.4 Freq. (Hz) 1020 1020 1020 1020 Level (dBV) –19.4 –19.4 –19.4 –19.4 –14.4 Condition RMI-RMO0 RMI-RMO1 RMO0/RMO1 RMO0/RMO1 R1I-RPO For typical setting R2I-RPO For typical setting R1I-SPO Speaker Preamp. Gain GSP 1020 –4.4 R2I-SPO Hold Acknowledge Tone Path Gain GPAS PB Acknowledge Tone Output Level PB Acknowledge Tone Frequency Difference PB Acknowledge Tone Distortion Side Tone Path Gain VPBRP VPBRP DfPBR THD PBR GSIDE Ni RPO Idle Channel Noise Ni SPO Ni RMO 1020 — — — 1020 — — — –7.4 — — — –21.4 — — — Set at typical +3 dB +6 dB +9 dB Set at typical +3 dB +6 dB +9 dB Set at typical Set at typical Min. 13.2 13.2 — — –8.0 1.0 4.0 7.0 –8.0 1.0 4.0 7.0 –8.0 –8.0 –5.0 Typ. Max. 15.3 15.3 –0.01 –179.6 –6.0 3.0 6.0 9.0 –6.0 3.0 6.0 9.0 –6.0 –6.0 –3.0 17.3 17.3 — — –4.0 5.0 8.0 11.0 –4.0 5.0 8.0 11.0 –4.0 dB –4.0 –1.0 dB dBV dBV % dB dB dBV dBV dBV dB dB dB Unit dB dB dB deg dB MLDYI-SPO RPO SPO RPO, SPO RPO, SPO TPBI-RPO RPO SPO RMI, VSG RMO0, RMO1 *6 *6 *6 –32.1 –30.1 –28.1 –30.2 –28.2 –26.2 –0.9 — 8.9 — — — — –35 10.9 –86 –86 –95 +0.9 –30 12.9 — — — Note: *6 Noise band width: 0.3 kHz to 3.4 kHz, non-weighted 20/43 ¡ Semiconductor AC Characteristics 3 (Receive Path) (Continued) MSM6895/6896 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol VOR Maximum Output Amplitude VOM RTONE0 Output Amplitude RTONE1 Output Amplitude FTONE Output Amplitude *7 VRT0 *8 VRT1 VFTRP VFTSP — — — — — — — — Freq. (Hz) — Level (dBV) — Condition RPO, SPO RL = 20 kW RMO0, RMO1 RL = 3 kW +55 nF RPO RPO RPO SPO Min. 2.4 3.0 77.2 Typ. Max. — — 91.7 — — Unit VPP VPP 109.0 mVPP 132.0 157.0 187.0 mVPP 135.5 161.0 191.5 159.0 189.0 224.6 mVPP Notes: *7 DT, PDT, SDT, CRBT, IIT *8 RBT, DT, T250 21/43 ¡ Semiconductor AC Characteristics 4 (Ringing Tone Output Circuit) MSM6895/6896 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol VST1 Calling Tone Output Amplitude *9 VST2 VST3 VST4 Howler Tone Output Amplitude VHOW — — — — Freq. (Hz) Level (dBV) Condition SA0SA1 to VDG Min. Typ. Max. 4.0 1.28 0.47 0.28 4.0 — 1.98 0.65 0.45 — VPP VPP Unit Volume 1 3.25 Volume 2 0.73 Volume 4 0.13 3.25 730 W Volume 3 0.25 Note: *9. IR-1, IR-2, SIR-1, SIR-2, CR, T1K, HR, SPT Digital Interface Characteristics (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Digital Output (Latch) Delay Time key Scanning Output Delay Time Digital Output (Data) Delay Time Digital Path Delay Time CODEC Data Output Delay Time Symbol Condition WRÆPO0, PO1, PO2, PO3, PO4 Pull-up resistor : 10 kW BT1ÆBR1, BR2 BT2ÆBR1, BR2 Min. 0.5 0.5 20 20 20 Typ. Max. — — 52 52 50 1.9 1.9 150 150 100 Unit ms ms ns ns ns tPDLA WRÆLA, LB, LC, LD, LML, LOSS tPDSCN tPDDATA RDÆDB0 to DB7 tPDPATH tPDCOD CK64ÆB1T, B2T 22/43 ¡ Semiconductor MSM6895/6896 TIMING DIAGRAM CK64 tSX CK8 B1T or B2T B1R or B2R 1 tXS tWS MSB 2 3 4 5 6 7 8 tpd cod B2 tDS B3 tDH B3 B4 B5 B6 B7 B8 B4 B5 B6 B7 B8 MSB B2 Figure 1 CODEC Timing A0, A1 tAW1 CE tCW1 WR TW RD tDW1 tDW2 DB0 to DB7 PO0 to PO4 tPDSCN tPDDATA TR tCW2 tCR1 tCR2 tAW2 tAR1 tAR2 tPDDATA tPDLA Latch Output Figure 2 Processor Interface Timing 23/43 ¡ Semiconductor FUNCTIONAL DESCRIPTION Control Data Description Sounder control WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data DB7 0 DB6 0 DB5 1 DB4 PDC *1 DB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 X DB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 X DB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 X DB0 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 X Output Tone SPT IR-1 IR-2 SIR-1 CR HOW *2 SIR-2 T1K HR DT SDT RBT BT PDT CRBT Frequency (Hz) 1 Wamble Tone Wamble Tone Wamble Tone Wamble Tone 800 or Wamble Tone Wamble Tone 1 1 400 400 400/16 400 400 0.5 0.25 0.125 Continuous 0.125 1 0.5 0.25 0.125 2 0.5 0.25 — — — — — Tone Output: RPO, Refer to Table 2 and 4. 1 0.25 0.125 — — — Make/Break Timing *6 Make (Sec) Break1 (Sec) Break2 (Sec) 0.125 1 0.5 0.25 Continuous Continuous 0.125 2 0.5 0.25 Remarks Tone Output: SA0, SA1 • — — 2.25 400/16 0.5 Suspends the tones above. • MSM6895/6896 *1. *2. *3. PDC: This bit is used for the CODEC power-down control. For making this bit valid, "0"s must be written to the control data bits described in the later section. PDC = 1: CODEC is in power-down mode. PDC = 0: CODEC is in operation mode. When the HOW is indicated, the LOSS output is "1". Otherwise it is "0". In the above specification, the data contents written later are valid. The signal of sounder path (SA0, SA1) and the signal of receive path (RPO) can not be output simultaneously. 24/43 ¡ Semiconductor Control of function key acknowledge tone WRITE Mode Address Data DB7 0 DB6 1 AD1 = 0, AD0 = 0 Control Data DB5 1 DB4 X X NTTC *4 0 0 0 0 DB3 X X X X 0 0 DB2 0 0 0 1 0 0 0 0 DB1 0 1 1 0 0 0 1 1 DB0 1 0 1 0 0 1 0 1 Output Tone IIT T250 FTONE (1) FTONE (2) Frequency (Hz) 400 250 1k 1k 0.25 Continuous Continuous 0.1 Suspends the IIT tone Suspends the T250 tone Suspends the FTONE • — Suspends the all above tones Make/Break Timing *6 Make (Sec) Break1 (Sec) Break2 (Sec) 0.25 2.25 Remarks Tone output: RPO, SPO *4. *5. *6. NTTC = 1 when the initial state is set. NTTC can be set as PBTC when the PB tone is set, but the data written into NTTC in later is valid. When NTTC = 1, the FTONE (1) and FTONE (2) signals are output from SPO. When NTTC = 0, these signals are output from RPO. NTTC = 1 when FTONE and PB tone is stopped. When two or more signals are specified out of IIT, T250 and FTONE, the output signals are compounded by two or three tones. The definition of Make/Break Timing is as follows; Break1 Break2 Make MSM6895/6896 25/43 ¡ Semiconductor PB tone control WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data Output PB Frequency DB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X DB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X DB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X PB 1 2 3 A 4 5 6 B 7 8 9 C * 0 # D Low 697 Hz 697 Hz 697 Hz 697 Hz 770 Hz 770 Hz 770 Hz 770 Hz 852 Hz 852 Hz 852 Hz 852 Hz 941 Hz 941 Hz 941 Hz 941 Hz High 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz When the initial state is set and the PB tone is suspended, the conditions of internal control signals are MUTN = 1 and NTTC = 1. When PBTC = 1, the PB tone is output only from the receive path SPO. The PB signal is not output from the transmit path. The conditions of internal control signals are MUTN = 1 and NTTC = 1. receive path RPO. The conditions of internal control signals are MUTN = 0 and NTTC = 0. Remarks When PBTC = 0, the PB tone is output from the transmit path and the DB7 1 DB6 0 DB5 1 DB4 PBTC DB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 X Suspends the PB tone MSM6895/6896 26/43 ¡ Semiconductor Latch control and timer reset WRITE Mode Address Data DB7 1 DB6 1 AD1 = 0, AD0 = 0 Control data DB5 1 DB4 0 DB3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 DB2 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 DB1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 DB0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 Latch output LT1 = 1 LML1 = 1 LMX1 = 1 LT2 = 1 LML2 = 1 LMX2 = 1 LR = 1 LS = 1 LMN = 1 LMR = 1 LA = 1 LB = 1 LC = 1 LD = 1 Sets the corresponding latches listed above to "0". Sets all latches listed above to "0". Resets the watch dog timer. These general latches are for external control. LA, LB, LC, and LD correspond to the external pin symbols and are set independently. Initially, all latches are set to "0". The output at the LML pin is in "1" when either LML1, LML2, or LMR is in "1". Remarks These latch are for internal control and used for control of speech path. Initially all latch are set to "0". For details of speech path control, refer to Table 1 to 4. Each latch can be specified independently. Latch codes described above 1 1 1 MSM6895/6896 27/43 ¡ Semiconductor Table 1. Transmit speech path setting list Status Symbol TA-1 TA-2 TA-3 TA-4 TA-5 TA-6 TA-7 TB-1 TB-2 TB-3 TB-4 TB-5 TB-6 TB-7 Control Symbol LML1 LT1 LMX1 LML2 LT2 LMX2 LMN MUTN SG 0 0 0 0 0 0 1 — — — — — — — 0 1 1 1 1 1 X — — — — — — — X 0 0 1 1 X X — — — — — — — — — — — — — — 0 0 0 0 0 0 1 — — — — — — — 0 1 1 1 1 1 X — — — — — — — X 0 0 1 1 X X X 0 1 0 1 X X X 0 1 0 1 X X X 1 1 1 1 0 X X 1 1 1 1 0 X 1 — 1 — — — — — — — — — — — Output Signal at T1O T — 1 — 1 — — — — — — — — — — TMX1 PBt — — — 1 1 — — — — — — — — — — — — — — 1 — — — — — — — — Ht — — — — — — 1 — — — — — — — SG — — — — — — — 1 — 1 — — — — Output Signal at T2O T — — — — — — — — 1 — 1 — — — TMX2 PBt — — — — — — — — — — 1 1 — — — — — — — — — — — — — — 1 — Ht — — — — — — — — — — — — — 1 Notes: 1. MUTN of Control Signal is set by PBTC (DB4). MUTN = 1 when the initial state is set. MUTN = 0 when PBTC = 0. MUTN = 1 when PBTC= 1. 2. SG: Signal ground, T: Transmit signal, TMX1: Transmit addition signal 1, TMX2: Transmit addition signal 2, PBt: PB signal, Ht: Hold tone signal 3. The output signals of T1O and T2O are the signals added by the signals indicated in "1"s in each column. MSM6895/6896 28/43 ¡ Semiconductor Table 2. Receive speech path setting list (RPO output) Control Signal LS 0 0 0 0 0 0 0 0 0 0 1 1 1 1 LT1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 LT2 0 0 0 0 1 1 1 1 1 1 0 0 1 1 LMN MUTN NTTC X 0 0 1 0 0 1 0 0 1 X X X X X 1 0 X 1 0 X 1 0 X X X X X 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 X X X X R1 — 1 1 1 — — — 1 1 1 — 1 — 1 R2 — — — — 1 1 1 1 1 1 — — 1 1 Output Signal at RPO Ts — 1 — — 1 — — 1 — — — — — — RT0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RT1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FT 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 — — — — PBr 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 — — — — Table 3. Control of receive main amplifier Control Signal Output signal of LR 0 1 RMO0 and RMO1 SG Input signal to RMI Status Symbol RP-1 RP-2 RP-3 RP-4 RP-5 RP-6 RP-7 RP-8 RP-9 RP-10 RP-11 RP-12 RP-13 RP-14 Notes: 4. R1: Receive signal 1, R2: Receive signal 2, Ts: Side tone signal, RT0: DT, PDT, SDT, CRBT, and IIT, RT1: RBT, BT, and T250, FT: FTONE and PBr: PB acknowledge signal. 5. Output Signal RPO is the signal added by the signal indicated in "1"s in each column. 6. "0"s of Control Signal NTTC are equivalent to "1"s of the Output Signals FT and PBr, and "1"s are equivalent to "0"s of Output Signals. 7. Control Signals MUTN and NTTC are the internal control signals. Initially, both signals are in "1"s. MUTN is controlled by PBTC of controlling the PB tone. MUTN = 0 when PBTC = 0. MUTN = 1 when PBTC = 1. NTTC is controlled by PBTC of controlling the PB tone or NTTC of controlling the function key acknowledge tone, but the NTTC data written later is valid. NTTC = 0 when PBTC = 0. NTTC = 1 when PBTC = 1. MSM6895/6896 29/43 ¡ Semiconductor Table 4. Receive speech path setting list (SPO) Status Symbol RS-1 RS-2 RS-3 RS-4 RS-5 RS-6 RS-7 RS-8 RS-9 RS-10 RS-11 Control Signal LS 0 0 0 1 1 1 1 1 1 1 1 LMR 0 0 1 0 0 0 0 1 1 1 1 LT1 X X X 0 1 0 1 0 1 0 1 LT2 NTTC X X X 0 0 1 1 0 0 1 1 0 1 0/1 X X X X X X X X SG 1 — — — — — — — — — — R1 — — — — 1 — 1 — 1 — 1 Output Signal at SPO R2 — — — — — 1 1 — — 1 1 RT0 — — — 1 1 1 1 1 1 1 1 RT1 — — — 1 1 1 1 1 1 1 1 FT — 1 0/1 1 1 1 1 1 1 1 1 PBr — 1 0/1 1 1 1 1 1 1 1 1 Hr — — 1 — — — — 1 1 1 1 Notes: 8. SG: Signal ground, R1: Receive signal 1, R2: Receive signal 2, Hr: Hold acknowledge tone, PBr: PB acknowledge tone, FT: FTONE, RT0: DT, PDT, SDT, CRBT, and IIT and RT1: RBT, BT, and T250. 9. An Output Signal at SPO is the signal added by the signal indicated in "1"s in each column. 10. The Control Signal NTTC is defined equally to Notes : 7. MSM6895/6896 30/43 ¡ Semiconductor Channel selector control WRITE Mode Address Data DB7 0 DB6 0 AD1 = 0, AD0 = 1 Control Data DB5 0 DB4 0 DB3 0 DB2 0 0 0 0 1 1 1 1 1 X X X X X DB1 0 0 1 1 0 0 1 1 X X X X X DB0 0 1 0 1 0 1 0 1 X X X X X Status Symbol A1 A2 A3 A4 B1 B2 B3 B4 C D1 D2 D3 D4 Main Connection Status B1T¨"1" B1T¨DOUT B1T¨BT1 B1T¨BT2 B2T¨"1" B2T¨DOUT B2T¨BT1 B2T¨BT2 B1T¨B2R B1T¨B1R B2T¨B2R BT1ÆBR1 BT2ÆBR2 Remarks B1RÆNo connection Different groups (A, B, C, and D) are set B1RÆDIN independently. B1RÆBR1 B1RÆBR2 For setting the same group, the data written later is B2RÆNo connection valid. B2RÆDIN B2RÆBR1 Refer to Table 5 and 6 for details. B2RÆBR2 The initial statuses are A1 and B2. B2T¨B1R X X X 1 X X 1 X X 1 X X 1 X X X X X X X MSM6895/6896 31/43 ¡ Semiconductor Table 5. Output pin connection status by channel selector control Status Symbol A1 A2 A3 A4 B1 B2 B3 B4 C D1 D2 D3 D4 Output Pin Connection Status BIT 1 DOUT BT1 BT2 — — — — B2R B1R *2 *2 *2 B2T — — — — 1 DOUT BT1 BT2 B1R *3 B2R *3 *3 DIN *1 B1R *1 *1 *1 B2R *1 *1 — — — — — BR1 *1 *1 B1R *1 *1 *1 B2R *1 — *4 *4 BT1 *4 BR2 *1 *1 *1 B1R *1 *1 *1 B2R — *4 *4 *4 BT2 Initial Setting Remarks Initial Setting Table 6. Output pin status by the combination of A and B Setting of A Setting of B B1 A1 B2 B3 B4 B1 A2 B2 B3 B4 B1 A3 B2 B3 B4 B1 A4 B2 B3 B4 Output Pin Connection Status DIN 1 B2R 1 1 B1R B1R or B2R B1R B1R 1 B2R 1 1 1 B2R 1 1 BR1 1 1 B2R 1 1 1 B2R 1 B1R B1R B1R or B2R B1R 1 1 B2R 1 BR2 1 1 1 B2R 1 1 1 B2R 1 1 1 B2R B1R B1R B1R B1R or B2R BR2 *5 BR1 *5 DIN *5 Remarks Initial Setting Notes: 11. *1. According to the combination of A and B (Table 6). *2. One of statuses A1 to A4 is held. *3. One of statuses B1 to B4 is held. *4. One of statuses A1 to A4 or one of statuses B1 to B4, whichever is written later, is held. When the setting of C is performed before the setting of D group, the setting of D must be performed after the setting of the group A and B. 12. The statuses of the pins indicated by "—" is not affected. 13. DIN is connected to the digital input of CODEC and DOUT is connected to the digital output of CODEC. 32/43 *5. When writing is performed in the sequence of setting of A and setting of B, the output status becomes B2R, and when writing is performed in the sequence of setting of B and setting of A, the output status becomes B1R. MSM6895/6896 ¡ Semiconductor key scanning output control and interrupt WRITE Mode Address Data AD1 = 1, AD0 = 0 Control Data Remarks The data set in DB4 to DB0 is output from output pins PO4 to PO0, respectively. The output statuses are held until the data is rewritten. When the data is "0", the output goes to "0", when the data is "1", the output is left open. Initially, PO4 to PO0 are left open. DB7 0 DB6 0 DB5 0 DB4 DB3 DB2 DB1 DB0 Output Data 1 X X X X X X X Resets the INTT output and sets to "1". This control data is valid only when written, it is not held. MSM6895/6896 33/43 ¡ Semiconductor Sounder, volume, and tone combination WRITE Mode Address Data DB7 0 DB6 0 AD1 = 1, AD0 = 1 Control Data DB4 X DB3 X DB2 X DB1 0 0 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 X DB0 0 1 0 1 X Volume 1 (High) Volume 2 (Medium) Volume 3 (Low1) Volume 4 (Low2) Tone combination setting (Initial setting) by external control (SW0, SW1) Tone combination 1 (1.0 kHz and 1.3 kHz, 16 Hz Wamble period) Tone combination 2 (0.8 kHz and 1.0 kHz, 16 Hz Wamble period) Tone combination 3 (0.8 kHz and 1.0 kHz, 8 Hz Wamble period) Tone combination 4 (0.5 kHz and 0.65 kHz, 16 Hz Wamble period) Tone combination 5 (0.4 kHz and 0.5 kHz, 16 Hz Wamble period) Tone combination 6 (0.4 kHz and 0.5 kHz, 8 Hz Wamble period) Initially the high volume is set, and tone combination is set externally. Control Remarks The setting of volume and tone combination is performed simultaneously, not independently. DB5 X MSM6895/6896 34/43 ¡ Semiconductor CODEC power down control WRITE Mode Address Data DB7 0 DB6 1 AD1 = 1, AD0 = 1 Contorol Data DB5 X DB4 X DB3 X DB2 0 DB1 0 DB0 0 control. (Initial setting) PDC = 0 CODEC power-on PDC = 1 CODEC power-down 1 1 1 1 0 1 1 0 1 0 1 0 CODEC Transmit power-down CODEC Receive power-down CODEC Transmit and Receive power-down CODEC power-down release Control CODEC power-down is controlled by PDC (DB4) during sounder Remarks Data written later is valid. MSM6895/6896 35/43 ¡ Semiconductor Gain control WRITE Mode Address Data DB7 DB7 1 DB6 0 DB5 X DB4 X DB3 X DB2 X DB1 0 0 1 0 0 1 1 0 1 0 1 X X X X DB0 0 1 X X X X X value.(Initial setting) Sets the transmit PB tone and hold tone level by 3 dB below the typical value. Sets the transmit PB tone and hold tone level by 6 dB below the typical value. Sets the receive gain at the typical value. (Initial setting) Sets the receive gain by 3 dB above the typical value. Sets the receive gain by 6 dB above the typical value. Sets the receive gain by 9 dB above the typical value. AD1 = 1, AD0 = 1 Control Sets the transmit PB tone and hold tone level at the typical Remarks The gain setting of the transmit path and the receive path can be performed simultaneously, not independently. MSM6895/6896 36/43 ¡ Semiconductor Howler tone color combination WRITE Mode Address Data DB7 1 DB6 1 AD1 = 1, AD0 = 0 Control Data DB4 X DB3 X DB2 X DB1 X DB0 0 1 Control Howler tone frequency: 0.8 kHz Howler tone frequency: 1.0 kHz and 1.3 kHz, 16 Hz Wamble period Initial setting Remarks DB5 X Key scanning data read out READ Mode Address Data DB7 PI7 DB6 PI6 AD1 = 1, AD0 = 0 DB4 PI4 DB3 PI3 DB2 PI2 DB1 PI1 DB0 PI0 Control The data input to the pins PI7 to PI0 is output from DB7 to DB0, respectively. DB5 PI5 MSM6895/6896 37/43 +5 V analog 100 kW Melody Tone Generation 0.47 mF Swith the sounder tone combination SW0 SW1 DG TPAO TPBI TMX1I TMX2I R2I T1O CAI MLDY LML 100 kW ¥ 2 +5 V 10 mF + 1 mF AG 0.47 mF 100 kW TPAI ¡ Semiconductor Line Interface Line APPLICATION CIRCUIT PO0 PO1 PO2 PO3 PO4 DG +5 V PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 Handset DG AG VSG CAO R1I RPO RMI RMO0 MSM6895 RMO1 Controller AG 1 mF 0-20W 1 mF + 10 mF Speaker VSGC 0.1 mF AG 100 kW ¥ 8 Driver SPO +5 V analog 0 V analog SAO Sounder SA1 LA B1T B1R B2T B2R CK8 CK64 BT1 BT2 TEST CK1536 WR RD CE AD1 AD0 DB7 to DB0 INTT TIME RESET VA VD VAG VDG LB LED SW Matrix MSM6895/6896 38/43 ¡ Semiconductor MSM6895/6896 Application circuit at the PCM Signal Data Rate of 192, 384, 768, 1536 and 2048 kbps. BCLOCK signal When the PCM signal data rate is one of 192, 384, 768, 1536, and 2048 kbps, input the 9-bit burst clock corresponding to the frequency equivalent to each of the data rates, as CK64 signal. 125 mS CK8 12 3 4 5 6 7 8 9 CK64 PCMIN/OUT 12345678 Burst clock generator +5 V 16 11 10 9 Equivalent to the 74LS161 1 Continuous Clock 2 7 8 MSM6895/6896 0V CK64 8 kHz Syncronous Signal CK8 Continuous Clock Syncronous Signal Burst Clock 39/43 ¡ Semiconductor MSM6895/6896 Application Circuit of Three-party Speech Path Speaker A M (A) (A) TPAI TPAO TPBI (A + C) T1O CAI (A + C) (B) (B) (A + B) (C) Handset TMX2I T2O TMX1I CAO R2I R1I RPO RMI RMO0 RMO1 MSM6895 AD DA B1T B1R Speaker B (B) (C) (B) B2T B2R (A + B) (C) Speaker C (B + C) BR2 BT2 Note: (A) indicates the voice signal of the A speaker (A + B) (C) AIN AOUT MSM7508 AD DA PCMOUT PCMIN Speech path setting (Speech through a handset) Transmit: Receive: Channel selector control A2, B4 TA-4 (LT1 = 1, LMX1 = 1, LMN = 0, MUTN = 1) TB-4 (LT2 = 1, LMX2 = 1, LMN = 0, MUTN = 1) RP-8 (LT1 = 1, LT2 = 1, LMN = 0, MUTN = 1, LR = 1) 40/43 SPEECH PATH GAIN ¡ Semiconductor TPAO TPBI MLDY TMX2I TMX1I T1O T2O CAI (Maximum input of 1.2 Vop) 0 dB TPAI +20 dB +17.7 dB –2 dB 0, 3, 6, 9 dB R1I –6 dB 0, 3, 6, 9 dB R2I –6 dB 0, –3, –6 dB +6 dB 0 dB 0, –3, –6dB DA 0 dB 0, –3, –6dB + AD 0 dB – + RPO RMI RMO0 RMO1 +15.3 dB X1 X–1 –6.8 dB SPO –6.8 dB –8.8 dB –2 dB 0, –3, –6 dB +6 dB RTONE1 RTONE2 FTONE 91.7 mVPP (DT, PDT, SDT, CRBT) 157 mVPP (RBT, BT, T250) 161 mVPP PB tone Generator + 0 dB –21.4 dBV (240 mVPP per signal) MSM6895/6896 –3 dB FTONE 189 mVPP CAO (Maximum input of 1.2 Vop) 41/43 ¡ Semiconductor MSM6895/6896 RECOMMENDATIONS FOR ACTUAL DESIGN • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. • Unused analog input pins must be connected to the VSG pin and unused digital pins must be connected to the GND pin. 42/43 ¡ Semiconductor MSM6895/6896 PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1420-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 43/43