74ABT573CSCX

74ABT573 Octal D-Type Latch with 3-STATE Outputs Features General Description ■ Inputs and outputs on opposite sides of package allow The ABT573 is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to ABT373 3-STATE outputs for bus interfacing Output sink capability of 64mA, source capability of 32mA Guaranteed output skew Guaranteed multiple output switching specifications Output switching specified for both 50pF and 250pF loads Guaranteed simultaneous switching, noise level and dynamic threshold performance Guaranteed latchup protection High-impedance, glitch-free bus loading during entire power up and power down Nondestructive, hot insertion capability This device is functionally identical to the ABT373 but has broadside pinouts. Ordering Information Order Number Package Number Package Description 74ABT573CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ABT573CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT573CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT573CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 74ABT573 — Octal D-Type Latch with 3-STATE Outputs December 2007 Functional Description The ABT573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Function Table Inputs Pin Descriptions Pin Names Descriptions D0–D7 Data Inputs LE Latch Enable Input (Active HIGH) OE 3-STATE Output Enable Input (Active LOW) O0–O7 3-STATE Latch Outputs Outputs OE LE D O L H H H L H L L L L X O0 H X X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 2 74ABT573 — Octal D-Type Latch with 3-STATE Outputs Connection Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol TSTG Parameter Rating Storage Temperature –65°C to +150°C TA Ambient Temperature Under Bias –55°C to +125°C TJ Junction Temperature Under Bias –55°C to +150°C VCC VCC Pin Potential to Ground Pin –0.5V to +7.0V VIN Input Voltage(1) –0.5V to +7.0V IIN Input Current(1) –30mA to +5.0mA VO Voltage Applied to Any Output Disabled or Power-Off State –0.5V to 5.5V HIGH State –0.5V to VCC Current Applied to Output in LOW State (Max.) twice the rated IOL (mA) DC Latchup Source Current –500mA Over Voltage Latchup (I/O) 10V Note: 1. Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol TA VCC ∆V / ∆t Parameter Rating Free Air Ambient Temperature –40°C to +85°C Supply Voltage +4.5V to +5.5V Minimum Input Edge Rate Data Input 50mV/ns Enable Input 20mV/ns ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 3 74ABT573 — Octal D-Type Latch with 3-STATE Outputs Absolute Maximum Ratings Symbol Parameter VCC Conditions Min. VIH Input HIGH Voltage Recognized HIGH Signal VIL Input LOW Voltage Recognized LOW Signal VCD Input Clamp Diode Voltage Min. IIN = –18mA VOH Output HIGH Voltage Min. IOH = –3mA 2.5 IOH = –32mA 2.0 VOL IIH IBVI IIL Output LOW Voltage Input HIGH Current Min. IOL = 64mA Max. VIN = Typ. Max. Units 2.0 V 0.8 –1.2 2.7V(3) V V V 0.55 V 1 µA VIN = VCC 1 Input HIGH Current Breakdown Test Max. VIN = 7.0V 7 µA Input LOW Current Max. VIN = 0.5V(3) –1 µA VIN = 0.0V –1 0.0 IID = 1.9 µA, All Other Pins Grounded VID Input Leakage Test 4.75 IOZH Output Leakage Current 0–5.5V VOUT = 2.7V, OE = 2.0V 10 µA IOZL Output Leakage Current 0–5.5V VOUT = 0.5V, OE = 2.0V –10 µA IOS Output Short-Circuit Current Max. VOUT = 0.0V –275 mA ICEX Output HIGH Leakage Current Max. VOUT = VCC 50 µA –100 V VOUT = 5.5V, All Others GND 100 µA ICCH Power Supply Current Max. All Outputs HIGH 50 µA ICCL Power Supply Current Max. All Outputs LOW 30 mA ICCZ Power Supply Current Max. OE = VCC, All Others at VCC or GND 50 µA ICCT Additional ICC/Input Max. VI = VCC – 2.1V 2.5 mA Outputs 3-STATE Enable Input VI = VCC – 2.1V 2.5 mA Outputs 3-STATE Data Input VI = VCC – 2.1V, All Others at VCC or GND 2.5 mA Outputs Open, OE = GND, LE = VCC(2), One-Bit Toggling, 50% Duty Cycle 0.12 mA/ MHz IZZ ICCD Bus Drainage Test Outputs Enabled Dynamic ICC No Load(3) 0.0 Max. Notes: 2. For 8-bits toggling, ICCD < 0.8mA/MHz. 3. Guaranteed but not tested. ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 4 74ABT573 — Octal D-Type Latch with 3-STATE Outputs DC Electrical Characteristics SOIC package. Symbol Parameter Conditions CL = 50pF, RL = 500Ω VCC Min. Typ. Max. Units 0.7 1.0 V VOLP Quiet Output Maximum Dynamic VOL 5.0 TA = VOLV Quiet Output Minimum Dynamic VOL 5.0 TA = 25°C(4) –1.5 –1.2 V VOHV Minimum HIGH Level Dynamic Output Voltage 5.0 TA = 25°C(5) 2.5 3.0 V VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 TA = 25°C(6) 2.2 1.8 V VILD Maximum LOW Level Dynamic Input Voltage 5.0 TA = 25°C(6) 25°C(4) 1.0 0.7 V Notes: 4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. 5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. 6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. AC Electrical Characteristics SOIC and SSOP package. TA = +25°C, VCC = +5.0V, CL = 50pF TA = –40°C to +85°C, VCC = 4.5V to 5.5V, CL = 50pF Symbol Parameter Min. Typ. Max. Min. Max. Units tPLH Propagation Delay, Dn to On 1.9 2.7 4.5 1.9 4.5 ns 1.9 2.8 4.5 1.9 4.5 2.0 3.1 5.0 2.0 5.0 2.0 3.0 5.0 2.0 5.0 1.5 3.1 5.3 1.5 5.3 1.5 3.1 5.3 1.5 5.3 2.0 3.6 5.4 2.0 5.4 2.0 3.4 5.4 2.0 5.4 tPHL tPLH Propagation Delay, LE to On tPHL tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 ns ns ns www.fairchildsemi.com 5 74ABT573 — Octal D-Type Latch with 3-STATE Outputs DC Electrical Characteristics 74ABT573 — Octal D-Type Latch with 3-STATE Outputs AC Operating Requirements SOIC and SSOP package. TA = +25°C, VCC = +5.0V, CL = 50pF Symbol fTOGGLE tS(H) tS(L) tH(H) tH(L) tW(H) Parameter Min. Max Toggle Frequency Typ. TA = –40°C to +85°C, VCC = 4.5V to 5.5V, CL = 50pF Max. Min. Max. Units 100 MHz Set Time, HIGH or LOW Dn to LE 1.5 1.5 1.5 1.5 Hold Time, HIGH or LOW Dn to LE 1.0 1.0 1.0 1.0 Pulse Width, LE HIGH 3.0 3.0 ns ns ns Extended AC Electrical Characteristics SOIC package. TA = –40°C to +85°C, TA = –40°C to +85°C, VCC = 4.5V to 5.5V, VCC = 4.5V to 5.5V, CL = 50pF, TA = –40°C to +85°C, CL = 250pF, 8 Outputs VCC = 4.5V to 5.5V, 8 Outputs Switching(7) CL = 250pF(8) Switching(9) Symbol Parameter Min. Max. Min. Max. Min. Max. Units tPLH Propagation Delay, Dn to On 1.5 5.2 2.0 6.8 2.0 9.0 ns 1.5 5.2 2.0 6.8 2.0 9.0 Propagation Delay, LE to On 1.5 5.5 2.0 7.5 2.0 9.5 1.5 5.5 2.0 7.5 2.0 9.5 Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5 1.5 6.2 2.0 8.0 2.0 tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time 1.0 5.5 1.0 5.5 (10) ns ns 10.5 (10) ns Notes: 7. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). 8. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching only. 9. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50pF load capacitors in the standard AC load. 10. The 3-STATE delay times are dominated by the RC network (500Ω, 250pF) on the output and has been excluded from the datasheet. ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 6 SOIC package. Symbol TA = –40°C to +85°C, VCC = 4.5V to 5.5V, CL = 50pF, 8 Outputs Switching(11) TA = –40°C to +85°C, VCC = 4.5V to 5.5V, CL = 250pF, 8 Outputs Switching(12) Max. Max. Units Parameter tOSHL (13) Pin to Pin Skew, HL Transitions 1.0 1.5 ns tOSLH (13) Pin to Pin Skew, LH Transitions 1.0 1.5 ns Duty Cycle, LH–HL Skew 1.4 3.5 ns Pin to Pin Skew, LH/HL Transitions 1.5 3.9 ns Device to Device Skew LH/HL Transitions 2.0 4.0 ns tPS (14) tOST(13) tPV (15) Notes: 11. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) 12. This specification is guaranteed but not tested. The limits represent propagation delays with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 13. Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). This specification is guaranteed but not tested. 14. This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. 15. Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Symbol CIN COUT (16) Conditions (TA = 25°C) Parameter Typ. Units Input Capacitance VCC = 0V 5 pF Output Capacitance VCC = 5.0V 9 pF Note: 16. COUT is measured at frequency f = 1MHz per MIL-STD-883B, Method 3012. ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 7 74ABT573 — Octal D-Type Latch with 3-STATE Outputs Skew(11) *Includes jig and probe capacitance Figure 2. Test Input Signal Levels Figure 1. Test Load Amplitude Rep. Rate 3.0V 1MHz tW tr tf 500ns 2.5ns 2.5ns Figure 3. Test Input Signal Requirements AC Waveforms Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Figure 6. 3-STATE Output HIGH and LOW Enable and Disable Times Figure 5. Propagation Delay, Pulse Width Waveforms Figure 7. Setup Time, Hold Time and Recovery Time Waveforms ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 8 74ABT573 — Octal D-Type Latch with 3-STATE Outputs AC Loading 13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 10 0.51 0.35 PIN ONE INDICATOR 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 1.27 0.40 SEATING PLANE E) LANDPATTERN STANDARD: SOIC127P1030X265-20L (1.40) DETAIL A F) DRAWING FILENAME: MKT-M20BREV3 SCALE: 2:1 Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 9 74ABT573 — Octal D-Type Latch with 3-STATE Outputs Physical Dimensions 74ABT573 — Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 10 74ABT573 — Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 11 74ABT573 — Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 12 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® µSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ©1993 Fairchild Semiconductor Corporation 74ABT573 Rev. 1.5.0 www.fairchildsemi.com 13 74ABT573 — Octal D-Type Latch with 3-STATE Outputs TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.