74ACT373

MC74AC373, MC74ACT373 Octal Transparent Latch with 3−State Outputs The MC74AC373/74ACT373 consists of eight latches with 3−state outputs for bus organized system applications. The flip−flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Features http://onsemi.com • • • • • Eight Latches in a Single Package 3−State Outputs for Bus Interfacing Outputs Source/Sink 24 mA ′ACT373 Has TTL Compatible Inputs Pb−Free Packages are Available VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 PDIP−20 N SUFFIX CASE 738 1 SOIC−20W DW SUFFIX CASE 751D 1 TSSOP−20 DT SUFFIX CASE 948E 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND SOEIAJ−20 M SUFFIX CASE 967 1 1 Figure 1. Pinout: 20−Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN D0−D7 LE OE O0−O7 FUNCTION Data Inputs Latch Enable Input Output Enable Input 3−State Latch Outputs ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 9 of this data sheet. LE OE D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7 Figure 2. Logic Symbol © Semiconductor Components Industries, LLC, 2006 1 November, 2006 − Rev. 8 Publication Order Number: MC74AC373/D MC74AC373, MC74ACT373 TRUTH TABLE Inputs OE H L L L LE X H H L Dn X L H X Outputs On Z L H O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before LOW-to-HIGH Transition of Clock FUNCTIONAL DESCRIPTION The MC74AC373/74ACT373 contains eight D−type latches with 3−state standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3-state standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2−state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. D3 D4 D5 D6 D7 D0 D1 D2 D G LE O D G O D G O D G O D G O D G O D G O D G O OE NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram http://onsemi.com 2 MC74AC373, MC74ACT373 MAXIMUM RATINGS Symbol VCC VIN VOUT IIN IOUT ICC Tstg Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC VCC or GND Current per Output Pin Storage Temperature Value −0.5 to +7.0 −0.5 to VCC +0.5 −0.5 to VCC +0.5 ±20 ±50 ±50 −65 to +150 Unit V V V mA mA mA °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Supply Voltage DC Input Voltage, Output Voltage (Ref. to GND) VCC @ 3.0 V tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs Junction Temperature (PDIP) Operating Ambient Temperature Range Output Current − High Output Current − Low VCC @ 4.5 V VCC @ 5.5 V tr, tf TJ TA IOH IOL VCC @ 4.5 V VCC @ 5.5 V Parameter ′AC ′ACT Min 2.0 4.5 0 − − − − − − −40 − − Typ 5.0 5.0 − 150 40 25 10 8.0 − 25 − − Max 6.0 5.5 VCC − − − − ns/V − 140 85 −24 24 °C °C mA mA ns/V V V Unit 1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. http://onsemi.com 3 MC74AC373, MC74ACT373 DC CHARACTERISTICS 74AC Symbol Parameter VCC (V) TA = +25°C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOZ Maximum Input Leakage Current Maximum 3−State Current †Minimum Dynamic Output Current 5.5 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 − − − 0.002 0.001 0.001 − − − − 74AC TA = −40°C to +85°C Unit Conditions Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 V VOUT = 0.1 V or VCC − 0.1 V VOUT = 0.1 V or VCC − 0.1 V IOUT = −50 mA V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 mA V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND VIL V VOH V V mA 5.5 − ±0.5 − − 8.0 ±5.0 75 −75 80 mA mA mA mA IOLD IOHD ICC 5.5 5.5 − − − Maximum Quiescent Supply Current 5.5 *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. http://onsemi.com 4 MC74AC373, MC74ACT373 AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com) 74AC Symbol Parameter VCC* (V) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Dn to On Propagation Delay Dn to On Propagation Delay LE to On Propagation Delay LE to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 TA = +25°C CL = 50 pF Typ 10 7.0 9.5 7.0 10 7.5 9.5 7.0 9.0 7.0 8.5 6.5 10 8.0 8.0 6.5 Max 13.5 9.5 13 9.5 13.5 9.5 12.5 9.5 11.5 8.5 11.5 8.5 12.5 11 11.5 8.5 74AC TA = −40°C to +85°C CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 15 10.5 14.5 10.5 15 10.5 14 10.5 13 9.5 13 9.5 14.5 12.5 12.5 10 ns ns ns ns ns ns ns ns 3−5 3−5 3−6 3−6 3−7 3−8 3−7 3−8 Unit Fig. No. *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS 74AC Symbol Parameter VCC* (V) TA = +25°C CL = 50 pF Typ ts th tw Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH 3.3 5.0 3.3 5.0 3.3 5.0 3.5 2.0 −3.0 −1.5 4.0 2.0 74AC TA = −40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum 5.5 4.0 1.0 1.0 5.5 4.0 6.0 4.5 1.0 1.0 6.0 4.5 ns ns ns 3−9 3−9 3−6 *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. http://onsemi.com 5 MC74AC373, MC74ACT373 DC CHARACTERISTICS 74ACT Symbol Parameter VCC (V) TA = +25°C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN DICCT IOZ Maximum Input Leakage Current Additional Max. ICC/Input Maximum 3-State Current †Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 5.5 5.5 1.5 1.5 1.5 1.5 4.49 5.49 − − 0.001 0.001 − − − 0.6 − 74ACT TA = −40°C to +85°C Unit Conditions Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 − ±0.5 − − 8.0 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 1.5 ±5.0 75 −75 80 V V V VOUT = 0.1 V or VCC − 0.1 V VOUT = 0.1 V or VCC − 0.1 V IOUT = −50 mA *VIN = VIL or VIH IOH −24 mA −24 mA IOUT = 50 mA *VIN = VIL or VIH 24 mA IOL 24 mA VI = VCC, GND VI = VCC − 2.1 V VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND V V V mA mA mA mA mA mA IOLD IOHD ICC 5.5 5.5 5.5 − − − *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. http://onsemi.com 6 MC74AC373, MC74ACT373 AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com) 74ACT Symbol Parameter VCC* (V) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ Propagation Delay Dn to On Propagation Delay Dn to On Propagation Delay LE to On Propagation Delay LE to On Output Enable Time Output Enable Time Output Disable Time 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 2.5 2.0 2.5 2.0 2.0 2.0 2.5 1.5 TA = +25°C CL = 50 pF Typ 8.5 8.0 8.5 8.0 8.0 7.5 9.0 7.5 Max 10 10 11 10 9.5 9.0 11 8.5 74ACT TA = −40°C to +85°C CL = 50 pF Min 1.5 1.5 2.0 1.5 1.5 1.5 2.5 1.0 Max 11.5 11.5 11.5 11.5 10.5 10.5 12.5 10 ns ns ns ns ns ns ns ns 3−5 3−5 3−6 3−6 3−7 3−8 3−7 3−8 Unit Fig. No. tPLZ Output Disable Time *Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS (For Figures and Waveforms − See AND8277/D at www.onsemi.com) 74ACT Symbol Parameter VCC* (V) Typ ts th Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE 5.0 5.0 5.0 3.0 0 2.0 TA = +25°C CL = 50 pF 74ACT TA = −40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum 7.0 0 7.0 8.0 1.0 8.0 ns ns ns 3−9 3−9 3−6 tw LE Pulse Width, HIGH *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 40 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V http://onsemi.com 7 MC74AC373, MC74ACT373 ORDERING INFORMATION Device MC74AC373N MC74AC373NG MC74ACT373N MC74ACT373NG MC74AC373DW MC74AC373DWG MC74AC373DWR2 MC74AC373DWR2G MC74ACT373DW MC74ACT373DWG MC74ACT373DWR2 MC74ACT373DWR2G MC74AC373DT MC74AC373DTG MC74AC373DTR2 MC74AC373DTR2G MC74ACT373DT MC74ACT373DTG MC74ACT373DTR2 MC74ACT373DTR2G MC74AC373MEL MC74AC373MELG MC74ACT373MEL MC74ACT373MELG Package PDIP−20 PDIP−20 (Pb−Free) PDIP−20 PDIP−20 (Pb−Free) SOIC−20 SOIC−20 (Pb−Free) SOIC−20 SOIC−20 (Pb−Free) SOIC−20 SOIC−20 (Pb−Free) SOIC−20 SOIC−20 (Pb−Free) TSSOP−20* TSSOP−20* TSSOP−20* TSSOP−20* TSSOP−20* TSSOP−20* TSSOP−20* TSSOP−20* SOEIAJ−20 SOEIAJ−20 (Pb−Free) SOEIAJ−20 SOEIAJ−20 (Pb−Free) 2000 / Tape & Reel 2000 / Tape & Reel 2500 / Tape & Reel 75 Units / Rail 2500 / Tape & Reel 75 Units / Rail 1000 / Tape & Reel 38 Units / Rail 1000 / Tape & Reel 38 Units / Rail 18 Units / Rail Shipping † †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb−Free. http://onsemi.com 8 MC74AC373, MC74ACT373 MARKING DIAGRAMS PDIP−20 SOIC−20W TSSOP−20 SOEIAJ−20 20 20 MC74AC373N AWLYYWWG 1 1 AC373 AWLYYWWG 20 AC 373 ALYWG G 1 20 74AC373 AWLYWWG 1 20 20 MC74ACT373N AWLYYWWG 1 1 ACT373 AWLYYWWG 20 ACT 373 ALYWG G 1 20 74ACT373 AWLYWWG 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) http://onsemi.com 9 MC74AC373, MC74ACT373 PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE E −A− 20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B 10 C L −T− SEATING PLANE K M E G F D 20 PL N J 0.25 (0.010) M 20 PL 0.25 (0.010) TA M M TB M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 SOIC−20W DW SUFFIX CASE 751D−05 ISSUE G D A 11 X 45 _ q H M B M 20 10X 0.25 E NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 1 10 20X B 0.25 M B TA S B S A SEATING PLANE h 18X e A1 T C http://onsemi.com 10 L MC74AC373, MC74ACT373 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C K REF M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 −−− −−− 0.047 C 1.20 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC −W− H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ 20X 2X L/2 20 11 J J1 B −U− N L PIN 1 IDENT 1 10 0.15 (0.006) T U S A −V− N F DETAIL E C D 0.100 (0.004) −T− SEATING PLANE G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 16X 0.36 16X 1.26 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 11 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ SECTION N−N 0.25 (0.010) M 0.15 (0.006) T U S 0.10 (0.004) TU S V S K K1 0.65 PITCH DIMENSIONS: MILLIMETERS MC74AC373, MC74ACT373 PACKAGE DIMENSIONS SOEIAJ−20 M SUFFIX CASE 967−01 ISSUE A 20 11 LE Q1 M_ L DETAIL P E HE 1 10 Z D e VIEW P A c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.81 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.032 b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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