74ACTQ841SCX

Revised September 2000 74ACTQ841 Quiet Series 10-Bit Transparent Latch with 3-STATE Outputs General Description Features The ACTQ841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 841 is a 10-bit transparent latch, a 10-bit version of the 373. The ACTQ841 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Inputs and outputs on opposite sides of package allow easy interface with microprocessors ■ Improved latch-up immunity ■ Outputs source/sink 24 mA ■ Has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ841SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ841SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Descriptions Pin Names Description D0–D9 Data Inputs O0–O9 3-STATE Outputs OE Output Enable LE Latch Enable FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010688 www.fairchildsemi.com 74ACTQ841 Quiet Series 10-Bit Transparent Latch with 3-STATE Outputs March 1990 74ACTQ841 Functional Description Function Table The ACTQ841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. Inputs Internal Output Function OE On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. LE D Q O X X X X Z High Z H H L L Z High Z H H H H Z High Z H L X NC Z Latched L H L L L Transparent L H H H H Transparent L L X NC NC Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions − 0.5V to + 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = − 0.5V − 20 mA VI = VCC + 0.5V + 20 mA Supply Voltage (VCC) 0V to VCC Output Voltage (VO) − 0.5V to VCC + 0.5V DC Input Voltage (VI) 4.5V to 5.5V Input Voltage (VI) 0V to VCC − 40°C to + 85°C Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t DC Output Diode Current (IOK) VO = − 0.5V − 20 mA VO = VCC + 0.5V + 20 mA VCC @ 4.5V, 5.5V − 0.5V to VCC + 0.5V DC Output Voltage (VO) 125 mV/ns VIN from 0.8V to 2.0V DC Output Source ± 50 mA or Sink Current (IO) DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. − 65°C to + 150°C Storage Temperature (TSTG) DC Latch-Up Source ± 300 mA or Sink Current Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level VCC TA = +25°C (V) Typ 4.5 1.5 TA = − 40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = − 50 µA VIN = VIL or VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 V IOH = − 24 mA IOH = − 24 mA (Note 2) Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA 5.5 ± 0.5 ± 5.0 µA V IOUT = 50 µA V IOL = − 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current IOL = − 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND ICCT Maximum 1.5 mA IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min 80.0 µA ICC/Input ICC Maximum Quiescent Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Minimum HIGH Level Dynamic Input Voltage 5.5 0.6 5.5 8.0 5.0 1.1 1.5 V 5.0 −0.6 −1.2 V 5.0 1.9 2.2 V 3 VI = VCC − 2.1V VIN = VCC or GND Figures 1, 2 (Note 4)(Note 5) Figures 1, 2 (Note 4)(Note 5) (Note 4)(Note 6) www.fairchildsemi.com 74ACTQ841 Absolute Maximum Ratings(Note 1) 74ACTQ841 DC Electrical Characteristics Symbol Maximum LOW Level VILD TA = +25°C VCC Parameter Dynamic Input Voltage (Continued) (V) Typ 5.0 1.2 TA = − 40°C to +85°C Units Conditions Guaranteed Limits 0.8 V (Note 4)(Note 6) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: PDIP package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 6: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL Dn to On tPLH Propagation Delay tPHL LE to On tPZH Output Enable Time tPZL OE to On tPHZ Output Disable Time tPLZ OE to On tOSLH Output to Output tOSHL Skew Dn to On (Note 8) VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 7) Min Typ Max Min Max 5.0 2.5 7.0 9.5 2.0 10.0 ns 5.0 2.5 7.0 9.5 2.0 10.0 ns 5.0 2.5 8.5 11.0 2.0 12.0 ns 5.0 1.0 6.0 9.0 1.0 9.5 ns 0.5 1.0 1.0 ns 5.0 Note 7: Voltage Range 5.0 is 5.0V ± 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements Symbol Parameter VCC TA = + 25 (V) CL = 50 pF °C (Note 9) tS Setup Time, HIGH or LOW Dn to LE tH Hold Time, HIGH or LOW Dn to LE tW LE Pulse Width, HIGH TA = − 40°C to + 85°C Typ CL = 50 pF 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 4.0 4.0 ns Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 85.0 pF VCC = 5.0V www.fairchildsemi.com Units Guaranteed Minimum 4 Conditions The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out of a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Note A: VOHV and VOLP are measured with respect to ground reference. Note B: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit 5 www.fairchildsemi.com 74ACTQ841 FACT Noise Characteristics 74ACTQ841 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 74ACTQ841 Quiet Series 10-Bit Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com