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74LCX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop with 5V Tolerant Inputs
Features
General Description
■ 5V tolerant inputs
■ Latch-up performance exceeds JEDEC 78 conditions
The LCX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
■ ESD performance:
Asynchronous Inputs:
■ 2.3V–3.6V VCC specifications provided
■ 7.0ns tPD max. (VCC = 3.3V), 10µA ICC max.
■ Power down high impedance inputs and outputs
■ ±24mA output drive (VCC = 3.0V)
■ Implements proprietary noise/EMI reduction circuitry
– Human body model > 2000V
– Machine model > 200V
■ Leadless Pb-Free DQFN package
■ LOW input to SD (Set) sets Q to HIGH level
■ LOW input to CD (Clear) sets Q to LOW level
■ Clear and Set are independent of clock
■ Simultaneous LOW on CD and SD makes both Q
and Q HIGH
Ordering Information
Order Number
Package
Number
Package Description
74LCX74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
74LCX74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX74BQX(1)
MLP14A
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 3.0mm
74LCX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
December 2013
Pin Assignments for SOIC, SOP, and TSSOP
IEEE/IEC
Pad Assignment for DQFN
Truth Table
(Each Half)
(Bottom View)
(Top View)
Inputs
Pin Description
Pin Names
Description
Outputs
SD
CD
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
X
X
H
H
L
L
D1, D2
Data Inputs
H
H
H
H
L
CP1, CP2
Clock Pulse Inputs
H
H
L
L
H
CD1, CD2
Direct Clear Inputs
H
H
X
Q0
Q0
SD1, SD2
Direct Set Inputs
H = HIGH Voltage Level
Q1, Q1, Q2, Q2
Outputs
L = LOW Voltage Level
DAP
No Connect
X = Immaterial
L
= LOW-to-HIGH Clock Transition
Note: DAP (Die Attach Pad)
Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition
of Clock
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
2
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Logic Symbols
Connection Diagrams
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
VI
Parameter
Rating
Supply Voltage
–0.5V to +7.0V
DC Input Voltage
–0.5V to +7.0V
VO
DC Output Voltage, Output in HIGH or LOW
IIK
DC Input Diode Current, VI < GND
IOK
DC Output Diode Current
State(2)
–0.5V to VCC + 0.5V
–50mA
VO < GND
–50mA
VO > VCC
+50mA
IO
DC Output Source/Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
±50mA
±100mA
±100mA
–65°C to +150°C
Note:
2. IO Absolute Maximum Rating must be observed.
Recommended Operating Conditions(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
Parameter
Min.
Max.
Units
Operating
2.0
3.6
V
Data Retention
1.5
3.6
Supply Voltage
VI
Input Voltage
0
5.5
V
VO
Output Voltage, HIGH or LOW State
0
VCC
V
VCC = 3.0V–3.6V
±24
mA
VCC = 2.7V–3.0V
±12
VCC = 2.3V–2.7V
±8
IOH / IOL
TA
∆t / ∆V
Output Current
Free-Air Operating Temperature
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
–40
85
°C
0
10
ns / V
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
3
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Absolute Maximum Ratings
TA = –40°C to +85°C
Symbol
VIH
VIL
VOH
VOL
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Leakage Current
II
VCC (V)
Min.
2.3–2.7
1.7
2.7–3.6
2.0
Max.
2.3–2.7
0.7
0.8
IOH = –100µA
2.3–3.6
V
VCC – 0.2
2.3
IOH = –8mA
1.8
2.7
IOH = –12mA
2.2
3.0
IOH = –18mA
2.4
IOH = –24mA
2.2
V
IOL = 100µA
0.2
2.3
IOL = 8mA
0.6
2.7
IOL = 12mA
0.4
3.0
IOL = 16mA
0.4
IOL = 24mA
0.55
0 ≤ VI ≤ 5.5V
2.3–3.6
2.3–3.6
Power-Off Leakage Current
0
ICC
Quiescent Supply Current
2.3–3.6
Increase in ICC per Input
2.3–3.6
Units
V
2.7–3.6
IOFF
∆ICC
Conditions
V
±5.0
µA
VI or VO = 5.5V
10
µA
VI = VCC or GND
10
µA
3.6V ≤ VI ≤ 5.5V
±10
VIH = VCC – 0.6V
500
µA
AC Electrical Characteristics
TA = –40°C to +85°C, RL = 500Ω
VCC = 3.3V ± 0.3V,
CL = 50pF
VCC = 2.7V,
CL = 50pF
VCC = 2.5V ± 0.2V,
CL = 30pF
Units
Symbol
Parameter
Min.
fMAX
Maximum Clock Frequency
150
tPHL, tPLH
Propagation Delay,
CPn to Qn or Qn
1.5
7.0
1.5
8.0
1.5
8.4
ns
tPHL, tPLH
Propagation Delay,
CDn or SDn to Qn or Qn
1.5
7.0
1.5
8.0
1.5
8.4
ns
tS
Setup Time
2.5
2.5
4.0
ns
tH
Hold Time
1.5
1.5
2.0
ns
tW
Pulse Width CP
3.3
3.3
4.0
ns
tW
Pulse Width and CD, SD
3.3
3.6
4.0
ns
Recovery Time
2.5
3.0
4.5
ns
tREC
tOSHL, tOSLH Output to Output
Max.
Min.
Max.
150
Skew(4)
1.0
Min.
Max.
150
MHz
ns
Note:
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
4
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
DC Electrical Characteristics
TA = 25°C
Symbol
Parameter
VCC (V)
VOLP
Quiet Output Dynamic Peak VOL
3.3
VOLV
Quiet Output Dynamic Valley VOL
Conditions
Typical
Unit
CL = 50pF, VIH = 3.3V, VIL = 0V
0.8
V
2.5
CL = 30pF, VIH = 2.5V, VIL = 0V
0.6
3.3
CL = 50pF, VIH = 3.3V, VIL = 0V
–0.8
2.5
CL = 30pF, VIH = 2.5V, VIL = 0V
–0.6
V
Capacitance
Symbol
Typical
Units
Input Capacitance
VCC = Open, VI = 0V or VCC
7
pF
COUT
Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8
pF
CPD
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10MHz
25
pF
CIN
Parameter
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
Conditions
www.fairchildsemi.com
5
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Dynamic Switching Characteristics
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH, tPHZ
GND
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output High Enable and
Disable Times for Logic
trise and tfall
VCC
Symbol
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
Vmi
1.5V
1.5V
VCC / 2
Vmo
1.5V
1.5V
VCC / 2
Vx
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
Vy
VOH – 0.3V
VOH – 0.3V
VOH – 0.15V
Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
6
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
AC Loading and Waveforms (Generic for LCX Family)
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Schematic Diagram (Generic for LCX Family)
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
7
Tape Format for DQFN
Package Designator
Tape Section
Number of Cavities
Cavity Status
Cover Tape Status
BQX
Leader (Start End)
125 (Typ.)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typ.)
Empty
Sealed
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12mm
13.0 (330.0)
0.059 (1.50)
0.512 (13.00)
0.795 (20.20)
2.165 (55.00)
0.488 (12.4)
0.724 (18.4)
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.1
www.fairchildsemi.com
8
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Tape and Reel Specification
0.65
A
0.43TYP
14
8
B
6.4
6.10
3.2
1
PIN#1 IDENT
0.2 C B A
7
TOP VIEW
1.65
ALL LEAD TIPS
0.45
RECOMMENDED LAND PATTERN
1.2 MAX
0.30
0.19
ALL LEAD TIPS
0.1 C
0.65
SEE DETAIL A
0.90+0.15
-0.10
0.13
A B
0.20
0.09
C
C
FRONT VIEW
0.09 MIN
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
E. LANDPATTERN STANDARD: SOP65P640X110-14M.
F. DRAWING FILE NAME: MKT-MTC14rev7.
GAGE PLANE
0.09 MIN
1.00
0.25
SEATING PLANE
DETAIL A
8.75
8.50
A
7.62
14
8
14
B
0.65
8
4.00
3.80
6.00
1
PIN #1
IDENT.
1.27
(0.33)
TOP VIEW
5.60
7
0.51
0.35
0.25 M C B A
1.75 MAX
1.70
1
1.27
LAND PATTERN RECOMMENDATION
A
C
1.50
1.25
FRONT VIEW
0.25
0.10
0.50
0.25 x 45
R0.10
GAGE
PLANE
R0.10
0.36
8°
0°
0.90
0.50
(1.04)
0.10 C
0.25
0.19
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS-012,
VARIATION AB, ISSUE C
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS
D. LAND PATTERN STANDARD:
SOIC127P600X145-14M
E. CONFORMS TO ASME Y14.5M, 2009
D. DRAWING FILENAME: MKT-M14Arev14
SEATING PLANE
DETAIL A
SCALE 16 : 1
7
0.05 C
4.00 MAX
2.20 MAX
1.40 MAX
B
3.00
A
2X
1.00
MAX
2.50
1.70
MAX
0.50 TYP
3.50
MAX
0.05 C
PIN #1 QUADRANT
TOP VIEW
(0.90)
2X
0.50 TYP
0.24 TYP
RECOMMENDED LAND PATTERN
0.10 C
0.08 C
SEATING
PLANE
C
SIDE VIEW
A. CONFORMS TO JEDEC REGISTRATION
MO-241, VARIATION AA
B. DIMENSIONS ARE IN MILLIMETERS.
(14X)
PIN #1 IDENT
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP14Arev2.
0.50
0.50
(14X)
2.00
BOTTOM VIEW
0.10
0.05
C A B
C
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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