74LVX163SJX

Revised October 2003 74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear General Description The LVX163 is a synchronous modulo-16 binary counter. This device is synchronously presettable for application in programmable dividers and has two types of Count Enable inputs plus a Terminal Count output for versatility in forming multistage counters. The CLK input is active on the rising edge. Both PE and MR inputs are active on low logic levels. Presetting is synchronous to rising edge of the CLK and the Clear function of the LVX163 is synchronous to the CLK. Two enable inputs (CEP and CET) and Carry Output are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. Features ■ Input voltage level translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise and dynamic threshold performance Ordering Code: Order Number 74LVX163M 74LVX163SJ 74LVX163MTC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Description Names CEP © 2003 Fairchild Semiconductor Corporation DS012157 Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input MR Synchronous Master Reset Input P0–P3 Parallel Data Inputs PE Parallel Enable Inputs Q0–Q3 Flip-Flop Outputs TC Terminal Count Output www.fairchildsemi.com 74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear October 1996 74LVX163 Functional Description The LVX163 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: synchronous reset, parallel load, count-up and hold. Four control inputs—Synchronous Reset (MR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)—determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. When the Parallel Enable (PE) is LOW, the parallel data outputs O0–O3 are active and follow the flip-flop Q outputs. A HIGH signal on PE forces O0–O3 to the High impedance state but does not prevent counting, loading or resetting. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET The LVX163 uses D-type edge-triggered flip-flops and changing the MR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Mode Select Table PE CET CEP L X X X Action on the Rising  Clock Edge ( The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 www.fairchildsemi.com MR H L X X Load (Pn → Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition  2 Reset (Clear) ) 74LVX163 State Diagram FIGURE 1. FIGURE 2. Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVX163 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA −0.5V to 7V DC Input Voltage (VI) 2.0V to 3.6V Input Voltage (VI) 0V to 5.5V Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC −40°C to +85°C Operating Temperature (TA) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA Input Rise and Fall Time (∆t/∆v) −0.5V to VCC + 0.5V DC Output Voltage (VO) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC Output Source ±25 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA (ICC or IGND) 0 ns/V to 100 ns/V Note 2: Unused inputs must be held HIGH or LOW. They may not float. −65°C to +150°C Storage Temperature (TSTG) Power Dissipation 180 mW DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter VCC TA = +25°C Min TA = −40°C to +85°C Typ Max Min HIGH Level Input 2.0 1.5 1.5 Voltage 3.0 2.0 2.0 3.6 2.4 2.4 Max 2.0 0.5 0.5 Voltage 3.0 0.8 0.8 3.6 0.8 0.8 HIGH Level Output 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 3.0 2.58 Conditions V LOW Level Input Voltage Units V VIN = VIL or VIH IOH = −50 µA IOH = −50 µA V IOH = −4 mA 2.48 LOW Level Output 2.0 0.0 Voltage 3.0 0.0 0.1 VIN = VIL or VIH IOL = 50 µA 0.1 0.1 0.1 3.0 0.36 0.44 IOL = 50 µA V IOL = 4 mA IIN Input Leakage Current 3.6 ±0.1 ±1.0 µA VIN = 5.5V or GND ICC Quiescent Supply Current 3.6 2.0 20.0 µA VIN = VCC or GND Noise Characteristics Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) Parameter Quiet Output Maximum TA = 25°C VCC Units CL (pF) 0.5 V 50 −0.5 V 50 3.3 2.0 V 50 3.3 0.8 V 50 (V) Typ Limits 3.3 0.2 3.3 −0.2 Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage VILD Maximum LOW Level (Note 3) Dynamic Input Voltage Note 3: Parameter guaranteed by design. www.fairchildsemi.com 4 Symbol Parameter tPLH Propagation Delay tPHL Time (CP–Qn) TA = 25°C VCC (V) Min 2.7 3.3 ± 0.3 tPLH Propagation Delay tPHL Time (CP–TC, Count) 2.7 3.3 ± 0.3 tPLH Propagation Delay tPHL Time (CP–TC, Load) 2.7 3.3 ± 0.3 tPLH Propagation Delay tPHL Time (CET–TC) 2.7 3.3 ± 0.3 fMAX Maximum Clock 2.7 Frequency 3.3 ± 0.3 TA = −40°C to +85°C Typ Max Min Max 9.0 14.0 1.0 16.0 11.3 17.0 1.0 19.0 8.3 12.8 1.0 15.0 10.8 16.3 1.0 18.5 9.5 14.3 1.0 16.7 12.5 18.5 1.0 20.5 8.7 13.6 1.0 16.0 11.2 17.1 1.0 19.5 11.4 18.0 1.0 21.0 14.0 21.0 1.0 24.0 11.0 17.2 1.0 20.0 13.5 20.7 1.0 23.5 8.6 13.5 1.0 15.0 11.0 16.5 1.0 18.5 7.5 12.3 1.0 14.5 10.5 15.8 1.0 18.0 75 115 65 50 80 45 80 130 70 55 85 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 23 ns ns ns ns ns ns ns ns MHz MHz 50 10 Units 10 Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF pF VCC = Open pF (Note 4) Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fIN + ICC. When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ∆ICC which is obtained from the following formula: CQ0–C Q3 and CTC are the capacitances at Q0–Q3 and TC, respectively. F CP is the input frequency of the CP. 5 www.fairchildsemi.com 74LVX163 AC Electrical Characteristics 74LVX163 AC Operating Requirements Symbol tS 6.5 8.0 9.5 3.3 ± 0.3 8.0 9.5 2.7 7.5 9.0 3.3 ± 0.3 7.5 9.0 2.7 4.0 4.0 3.3 ± 0.3 4.0 4.0 2.7 1.0 1.0 3.3 ± 0.3 1.0 1.0 2.7 1.0 1.0 3.3 ± 0.3 1.0 1.0 2.7 1.0 1.0 3.3 ± 0.3 1.0 1.0 2.7 1.5 1.5 3.3 ± 0.3 1.5 1.5 2.7 5.0 5.0 3.3 ± 0.3 5.0 5.0 Minimum Hold Time (CEP or CET–CP) tH 5.5 2.7 Minimum Hold Time (PE –CP) tH 3.3 ± 0.3 Minimum Hold Time (Pn–CP) tH 6.5 Minimum Setup Time (MR –CP) tH Minimum Hold Time (MR –CP) tW(L) Minimum Pulse Width tW(H) CP (Count) www.fairchildsemi.com TA = −40°C to +85°C Guaranteed Minimum 5.5 Minimum Setup Time (CEP or CET–CP) tS TA = 25°C 2.7 Minimum Setup Time (PE –CP) tS (V) Minimum Setup Time (Pn–CP) tS VCC Parameter 6 Units ns ns ns ns ns ns ns ns ns 74LVX163 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7 www.fairchildsemi.com 74LVX163 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued)