74VHC08MTC

74VHC08 Quad 2-Input AND Gate General Description The VHC08 is an advanced high speed CMOS 2 Input AND Gate fabricated with silicon gate CMOS technology. It achieves the high−speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 4 stages including buffer output, which provide high noise immunity and stable output. An input protection circuit insures that 0 V to 7 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. www.onsemi.com MARKING DIAGRAMS Order Number: 74VHC08M Features • • • • • • High Speed: tPD = 4.3 ns (Typ.) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC (Min.) Power Down Protection is Provided on All Inputs Low Power Dissipation: ICC = 2 mA (Max.) @ TA = 25°C Low Noise: VOLP = 0.8 V (Max.) Pin and Function Compatible with 74HC08 SOIC14 CASE 751EF A WL Y WW = Assembly Location = Wafer Lot = Year = Work Week Order Number: 74VHC08MTCX 14 14 AXYKK V08 1 TSSOP−14 WB CASE 948G A XY KK 1 = Assembly Location = 2−digit 2 Weekly Date Code = 2−digit Lot Run Code Order Number: 74VHC08SJX 14 SOP14 CASE 565BE AXYKK VHC08 1 A XY KK = Assembly Location = 2−digit 2 Weekly Date Code = 2−digit Lot Run Code ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2017 June, 2019 − Rev. 3 1 Publication Order Number: 74VHC08/D 74VHC08 IEEE/IEC Figure 1. Connection Diagram Figure 2. Logic Symbol PIN DESCRIPTION Pin Names TRUTH TABLE Description An, Bn Inputs A B O On Outputs L L L L H L H L L H H H ORDERING INFORMATION Part Number Package Number Package Packing Method† 74VHC08M M14A SOIC14 (Pb−Free) 55 / Tube 74VHC08SJ M14D SOP14 (Pb−Free) 2000 / Tape & Reel 74VHC08MTC MTC14 TSSOP−14 WB (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D www.onsemi.com 2 74VHC08 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating VCC Supply Voltage –0.5 V to +7.0 V VIN DC Input Voltage –0.5 V to +7.0 V VOUT DC Output Voltage –0.5 V to VCC + 0.5 V IIK Input Diode Current –20 mA IOK Output Diode Current ±20 mA IOUT DC Output Current ±25 mA ICC DC VCC / GND Current ±50 mA TSTG TL Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS (Note 1) Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Output Voltage TOPR Operating Temperature tr, tf Rating 2.0 V to +5.5 V 0 V to +5.5 V 0 V to VCC –40°C to +85°C Input Rise and Fall Time, VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V 0 ns/V ∼ 100 ns/V 0 ns/V ∼ 20 ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 1. Unused inputs must be held HIGH or LOW. They may not float. www.onsemi.com 3 74VHC08 DC ELECTRICAL CHARACTERISTICS TA = 255C Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage VCC (V) Min Conditions 1.50 3.0–5.5 0.7 x VCC 0.7 x VCC ICC Max Units V V 2.0 0.50 0.50 3.0–5.5 0.3 x VCC 0.3 x VCC 2.0 HIGH Level Output Voltage 3.0 VIN = VIH or VIL IOH = –50 mA 1.9 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 3.0 IOH = –4 mA 2.58 2.48 4.5 IOH = –8 mA 3.94 3.80 2.0 LOW Level Output Voltage Input Leakage Current Min 1.50 3.0 VIN = VIH or VIL IOL = 50 mA 4.5 IIN Max 2.0 4.5 VOL Typ TA = –405C to +855C V 0.0 0.1 0.1 0.0 0.1 0.1 0.0 0.1 0.1 3.0 IOL = 4 mA 0.36 0.44 4.5 IOL = 8 mA 0.36 0.44 V 0–5.5 VIN = 5.5 V or GND ±0.1 ±1.0 mA 5.5 VIN = VCC or GND 2.0 20.0 mA Quiescent Supply Current NOISE CHARACTERISTICS TA = 255C Symbol VOLP(2) VOLV(2) VIHD(2) VILD(2) Parameter VCC (V) Conditions Typ Limits Units 5.0 CL = 50 pF 0.3 0.8 V Quiet Output Minimum Dynamic VOL 5.0 CL = 50 pF –0.3 –0.8 V Minimum HIGH Level Dynamic Input Voltage 5.0 CL = 50 pF 3.5 V Maximum LOW Level Dynamic Input Voltage 5.0 CL = 50 pF 1.5 V Quiet Output Maximum Dynamic VOL 2. Parameter guaranteed by design. www.onsemi.com 4 74VHC08 AC ELECTRICAL CHARACTERISTICS TA = 255C Symbol tPHL, tPLH Parameter Propagation Delay CPD Input Capacitance Power Dissipation Capacitance TA = –405C to +855C Typ Max Min Max Units ns VCC (V) Conditions 3.3 ± 0.3 CL = 15 pF 6.2 8.8 1.0 10.5 CL = 50 pF 8.7 12.3 1.0 14.0 CL = 15 pF 4.3 5.9 1.0 7.0 CL = 50 pF 5.8 7.9 1.0 9.0 VCC = Open 4 10 (Note 3) 18 5.0 ± 0.5 CIN Min 10 ns pF pF 3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 4 (per gate). www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC14 CASE 751EF ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13739G SOIC14 DATE 30 SEP 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G ISSUE C 14 DATE 17 FEB 2016 1 SCALE 2:1 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− K1 J J1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX ALYWG G 7.06 1 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: 98ASH70246A DESCRIPTION: TSSOP−14 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 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