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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
74VHCT00A
Quad 2-Input NAND Gate
Features
General Description
■ High speed: tPD = 5.0ns (Typ.) at TA = 25°C
■ High noise immunity: VIH = 2.0V, VIL = 0.8V
The VHCT00A is an advanced high-speed CMOS
2-Input NAND Gate fabricated with silicon gate CMOS
technology. It achieves the high-speed operation similar
to equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The internal circuit is
composed of 3 stages, including buffer output, which
provide high noise immunity and stable output.
■ Power down protection is provided on all inputs and
outputs
Low
noise: VOLP = 0.8V (Max.)
■
■ Low power dissipation: ICC = 2A (Max.) at TA = 25°C
■ Pin and function compatible with 74HCT00
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with VCC = 0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V
to 5V systems and two supply systems such as battery
backup.
Ordering Information
Order Number
Package
Number
Package Description
74VHCT00AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012,
0.150" Narrow
74VHCT00ASJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT00AMTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
www.fairchildsemi.com
74VHCT00A — Quad 2-Input NAND Gate
December 2007
Logic Symbol
Pin Description
Truth Table
Pin Names
Description
An, Bn
Inputs
On
Outputs
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
A
B
O
L
L
H
L
H
H
H
L
H
H
H
L
www.fairchildsemi.com
2
74VHCT00A — Quad 2-Input NAND Gate
Connection Diagram
Symbol
Parameter
Rating
VCC
Supply Voltage
–0.5V to +7.0V
VIN
DC Input Voltage
–0.5V to +7.0V
VOUT
DC Output Voltage
Note 1
–0.5V to VCC + 0.5V
Note 2
–0.5V to 7.0V
IIK
Input Diode Current
–20mA
IOK
Output Diode Current(3)
±20mA
IOUT
DC Output Current
±25mA
ICC
DC VCC / GND Current
TSTG
TL
±50mA
Storage Temperature
–65°C to +150°C
Lead Temperature (Soldering, 10 seconds)
260°C
Recommended Operating Conditions(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VCC
Supply Voltage
VIN
Input Voltage
VOUT
Rating
4.5V to +5.5V
0V to +5.5V
Output Voltage
Note 1
0V to VCC
Note 2
0V to 5.5V
TOPR
Operating Temperature
–40°C to +85°C
t r, t f
Input Rise and Fall Time, VCC = 5.0V ±0.5V
0ns/V ∼ 20ns/V
Notes:
1. HIGH or LOW state. IOUT absolute maximum rating must be observed.
2. VCC = 0V.
3. VOUT < GND, VOUT > VCC (Outputs Active).
4. Unused inputs must be held HIGH or LOW. They may not float.
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
www.fairchildsemi.com
3
74VHCT00A — Quad 2-Input NAND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
TA = –40°C
to +85°C
TA = 25°C
Symbol
Parameter
VCC (V)
Conditions
Min.
Typ.
Max.
Min.
Max. Units
VIH
HIGH Level Input
Voltage
4.5
2.0
5.5
2.0
VIL
LOW Level Input
Voltage
4.5
0.8
0.8
5.5
0.8
0.8
HIGH Level Output
Voltage
4.5
LOW Level Output
Voltage
4.5
VOH
VOL
VIN = VIH
or VIL
IOH = –50µA
4.40
IOH = –8mA
3.94
VIN = VIH
or VIL
IOL = 50µA
2.0
V
2.0
4.50
4.40
V
V
3.80
0.0
0.1
IOL = 8mA
0.1
V
0.36
0.44
0 – 5.5
VIN = 5.5V or GND
±0.1
±1.0
µA
Quiescent Supply
Current
5.5
VIN = VCC or GND
2.0
20.0
µA
ICCT
Maximum ICC / Input
5.5
VIN = 3.4V, Other
Inputs = VCC or GND
1.35
1.50
mA
IOFF
Output Leakage
Current (Power
Down State)
0.0
VOUT = 5.5V
0.5
5.0
µA
IIN
Input Leakage
Current
ICC
Noise Characteristics
TA = 25°C
Symbol
Parameter
Conditions
VCC (V)
Typ.
Limit
Units
CL = 50pF
5.0
0.4
0.8
V
CL = 50pF
5.0
–0.4
–0.8
V
Minimum HIGH Level Dynamic Input Voltage
CL = 50pF
5.0
2.0
V
Maximum LOW Level Dynamic Input Voltage
CL = 50pF
5.0
0.8
V
(5)
Quiet Output Maximum Dynamic VOL
(5)
Quiet Output Minimum Dynamic VOL
(5)
VILD(5)
VOLP
VOLV
VIHD
Note:
5. Parameter guaranteed by design.
AC Electrical Characteristics
TA = –40°C
to +85°C
TA = 25°C
Symbol
Parameter
VCC (V)
Max.
Min.
Max.
Units
CL = 15pF
5.0
6.9
1.0
8.0
ns
CL = 50pF
5.5
7.9
1.0
9.0
4
10
tPLH, tPHL
Propagation Delay
CIN
Input Capacitance
VCC = Open
Power Dissipation
Capacitance
(6)
CPD
5.0 ± 0.5
Typ.
Conditions
Min.
10
17
pF
pF
Note:
6. CPD is defined as the value of the internal equivalent capacitance, which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
ICC (Opr.) = CPD • VCC • fIN + ICC / 4 (per gate)
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
www.fairchildsemi.com
4
74VHCT00A — Quad 2-Input NAND Gate
DC Electrical Characteristics
0.65
A
0.43TYP
14
8
B
6.4
6.10
3.2
1
PIN#1 IDENT
0.2 C B A
7
TOP VIEW
1.65
ALL LEAD TIPS
0.45
RECOMMENDED LAND PATTERN
1.2 MAX
0.30
0.19
ALL LEAD TIPS
0.1 C
0.65
SEE DETAIL A
0.90+0.15
-0.10
0.13
A B
0.20
0.09
C
C
FRONT VIEW
0.09 MIN
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
E. LANDPATTERN STANDARD: SOP65P640X110-14M.
F. DRAWING FILE NAME: MKT-MTC14rev7.
GAGE PLANE
0.09 MIN
1.00
0.25
SEATING PLANE
DETAIL A
8.75
8.50
A
7.62
14
8
14
B
0.65
8
4.00
3.80
6.00
1
PIN #1
IDENT.
1.27
(0.33)
TOP VIEW
5.60
7
0.51
0.35
0.25 M C B A
1.75 MAX
1.70
1
1.27
LAND PATTERN RECOMMENDATION
A
C
1.50
1.25
FRONT VIEW
0.25
0.10
0.50
0.25 x 45
R0.10
GAGE
PLANE
R0.10
0.36
8°
0°
0.90
0.50
(1.04)
0.10 C
0.25
0.19
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS-012,
VARIATION AB, ISSUE C
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS
D. LAND PATTERN STANDARD:
SOIC127P600X145-14M
E. CONFORMS TO ASME Y14.5M, 2009
D. DRAWING FILENAME: MKT-M14Arev14
SEATING PLANE
DETAIL A
SCALE 16 : 1
7
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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