a
FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors
Complies with VRM 8.5 with Lowest System Cost
Active Current Balancing Between Both Output Phases
5-Bit Digitally Programmable 1.05 V to 1.825 V Output
Dual Logic-Level PWM Outputs for Interface to
External High-Power Drivers
Total Output Accuracy ⴞ0.8% Over Temperature
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
5-Bit Programmable 2-Phase
Synchronous Buck Controller
ADP3162
FUNCTIONAL BLOCK DIAGRAM
VCC
SET
UVLO
& BIAS
CROWBAR
REF
2-PHASE
DRIVER
LOGIC
PWM2
3.0V
REFERENCE
CMP3
GND
DAC+24%
PWRGD
CT
OSCILLATOR
CMP
CMP2
DAC–18%
CS–
ADP3162
APPLICATIONS
Desktop PC Power Supplies for:
Intel Tualatin Processors
VRM Modules
PWM1
RESET
CMP
CS+
CMP1
COMP
FB
gm
VID
DAC
VID3
GENERAL DESCRIPTION
The ADP3162 is a highly efficient dual output synchronous
buck switching regulator controller optimized for converting a
5 V or 12 V main supply into the core supply voltage required by
high-performance processors such as Tualatin. The ADP3162
uses an internal 5-bit DAC to read a voltage identification (VID)
code directly from the processor, which is used to set the output
voltage between 1.05 V and 1.825 V. The ADP3162 uses a
current mode PWM architecture to drive two logic-level outputs
at a programmable switching frequency that can be optimized
for VRM size and efficiency. The output signals are 180 degrees
out of phase, allowing for the construction of two complementary
buck switching stages. These two stages share the dc output
current to reduce overall output voltage ripple. An active current balancing function ensures that both phases carry equal
portions of the total load current, even under large transient
loads, to minimize the size of the inductors.
VID2
VID1
VID0
VID25
The ADP3162 also uses a unique supplemental regulation technique called active voltage positioning to enhance load transient
performance. Active voltage positioning results in a dc/dc converter
that meets the stringent output voltage specifications for high
performance processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a system transient. The
ADP3162 also provides accurate and reliable short circuit protection and adjustable current limiting.
The ADP3162 is specified over the commercial temperature
range of 0°C to 70°C and is available in a 16-lead narrow body
SOIC package.
ADOPT is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADP3162–SPECIFICATIONS1 (V
Parameter
Symbol
FEEDBACK INPUT
Accuracy
1.05 V Output
1.5 V Output
1.825 V Output
Line Regulation
Input Bias Current
Crowbar Trip Threshold
Crowbar Reset Threshold
Crowbar Response Time
FB Low Foldback Threshold
tCROWBAR
VFB(LOW)
REFERENCE
Output Voltage
Output Current
VREF
IREF
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current
Pull-Up Resistance
Internal Pull-Up Voltage
∆VFB
IFB
VCROWBAR
VIL(VID)
VIH(VID)
IVID
RVID
fCT(MAX)
fCT
ICT
ERROR AMPLIFIER
Output Resistance
Transconductance
Output Current
Maximum Output Voltage
Output Disable Threshold
–3 dB Bandwidth
RO(ERR)
gm(ERR)
IO(ERR)
VCOMP(MAX)
VCOMP(OFF)
BWERR
CURRENT SENSE
Threshold Voltage
VCS(TH)
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Voltage Low
Response Time
PWM OUTPUTS
Output Voltage Low
Output Voltage High
Output Current
Duty Cycle Limit2
= 12 V, IREF = 150 A, TA = 0ⴗC to 70ⴗC, unless otherwise noted.)
Conditions
Min
Typ
Max
Unit
Figure 1
Figure 1
Figure 1
VCC = 10 V to 14 V
1.042 1.050 1.058
1.488 1.500 1.512
1.811 1.825 1.839
0.05
5
50
114 124
134
50
60
70
300
425 500
575
V
V
V
%
nA
%
%
ns
mV
2.952 3.0
300
3.048
V
µA
0.6
3.3
V
V
µA
kΩ
V
570
170
46
kHz
kHz
µA
µA
VFB
OSCILLATOR
Maximum Frequency2
Frequency Accuracy
CT Charge Current
∆VCOMP /∆VCS
Input Bias Current
Response Time
CC
Percent of Nominal DAC Voltage
Percent of Nominal DAC Voltage
Overvoltage to PWM Going Low
0 ≤ IREF ≤ 300 µA
2.2
VID(x) = 0 V
12
2.7
TA = 25°C, CT = 91 pF
TA = 25°C, VFB in Regulation
TA = 25°C, VFB = 0 V
2000
430 500
130 150
26
36
2.0
FB = 0 V
FB Forced to VOUT – 3%
640
COMP = Open
CS+ = VCC,
FB Forced to VOUT – 3%
0.8 V ≤ COMP ≤ 1 V
FB ≤ 375 mV
1 V ≤ VCOMP ≤ 3 V
CS+ = CS– = VCC
CS+ – (CS–) ≥ 89 mV
to PWM Going Low
69
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Percent of Nominal Output
Percent of Nominal Output
IPWRGD(SINK) = 100 µA
76
114
VOL(PWM)
VOH(PWM)
IPWM
DC
IPWM(SINK) = 400 µA
IPWM(SOURCE) = 400 µA
VCS(FOLD)
ni
ICS+, ICS–
tCS
Per Phase, Relative to fCT
–2–
280
17
3
37
4.5
0.4
200
2.2
1
3.0
800
500
400
2.45
880
kΩ
mmho
mA
V
mV
kHz
79
89
mV
0
47
25
0.5
50
15
58
mV
mV
V/V
µA
ns
5
82
124
30
200
88
134
200
%
%
mV
ns
100
5.0
1
500
5.5
mV
V
mA
%
50
REV. A
ADP3162
Parameter
SUPPLY
DC Supply Current
Normal Mode
UVLO Mode
UVLO Threshold Voltage
UVLO Hysteresis
Symbol
Conditions
ICC
ICC(UVLO)
VUVLO
VCC ≤ VUVLO, VCC Rising
Min
Typ
Max
Unit
5.9
0.1
3.8
220
6.4
0.4
5.5
400
6.9
0.6
mA
µA
V
V
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Guaranteed by design, not tested in production.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
All Other Inputs and Outputs . . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
θJA
Two-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to GND.
ORDERING GUIDE
Model
Temperature Package
Range
Description
ADP3162JR 0°C to 70°C
Narrow Body SOIC
PIN CONFIGURATION
VID3 1
16 VCC
VID2 2
15 REF
VID1 3
VID0 4
14 CS–
ADP3162
13 PWM1
TOP VIEW
VID25 5 (Not to Scale) 12 PWM2
COMP 6
11 CS+
FB 7
10 PWRGD
CT 8
9
Package
Option
R-16A (SO-16)
Pin Mnemonic
Function
1–4, VID3 –VID0, Voltage Identification DAC Inputs.
5
VID25
These pins are pulled up to an internal
reference, providing a Logic 1 if left open.
The DAC output programs the FB regulation voltage from 1.05 V to 1.825 V.
6
COMP
Error Amplifier Output and Compensation
Point. The voltage at this output programs
the output current control level between
CS+ and CS–.
7
FB
Feedback Input. Error amplifier input for
remote sensing of the output voltage.
8
CT
External capacitor CT connection to ground
sets the frequency of the device.
9
GND
Ground. All internal signals of the ADP3162
are referenced to this ground.
10 PWRGD
Open drain output that signals when the output voltage is in the proper operating range.
11 CS+
Current Sense Positive Node. Positive input
for the current comparator. The output
current is sensed as a voltage at this pin with
respect to CS–.
12 PWM2
Logic-level output for the Phase 2 driver.
13 PWM1
Logic-level output for the Phase 1 driver.
14 CS–
Current Sense Negative Node. Negative
input for the current comparator.
15 REF
3.0 V Reference Output.
16 VCC
Supply Voltage for the ADP3162.
GND
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3162 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
ADP3162 –Typical Performance Characteristics
10000
30
25
NUMBER OF PARTS – %
OSCILLATOR FREQUENCY – kHz
TA = 25⬚C
VOUT = 1.6V
1000
20
15
10
5
100
0
100
200
300
CT CAPACITOR – pF
400
0
–0.5
500
TPC 1. Oscillator Frequency vs. Timing Capacitor
0
OUTPUT ACCURACY – % OF NOMINAL
0.5
TPC 3. Output Accuracy Distribution
4.10
SUPPLY CURRENT – mA
4.05
4.00
3.95
3.90
3.85
0
250
1000
500
750
1250
1500
OSCILLATOR FREQUENCY – kHz
1750
2000
TPC 2. Supply Current vs. Oscillator Frequency
–4–
REV. A
ADP3162
THEORY OF OPERATION
ADP3162
5-BIT CODE
1k
4.7nF
1
VID3
VCC 16
2
VID2
REF 15
3
VID1
CS– 14
4
VID0
PWM1 13
5
VID25
PWM2 12
6
COMP
7
FB
PWRGD 10
8
CT
GND 9
12V
+
1 F
100nF
CS+ 11
VFB
AD820
1.2V
Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit
Table I. Output Voltage vs. VID Code
VID25
VID3
VID2
VID1
VID0
VOUT(NOM)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1.050 V
1.075 V
1.100 V
1.125 V
1.150 V
1.175 V
1.200 V
1.225 V
1.250 V
1.275 V
1.300 V
1.325 V
1.350 V
1.375 V
1.400 V
1.425 V
1.450 V
1.475 V
1.500 V
1.525 V
1.550 V
1.575 V
1.600 V
1.625 V
1.650 V
1.675 V
1.700 V
1.725 V
1.750 V
1.775 V
1.800 V
1.825 V
REV. A
The ADP3162 combines a current-mode, fixed frequency PWM
controller with antiphase logic outputs in a controller for a twophase synchronous buck power converter. Two-phase operation
is important for switching the high currents required by high
performance microprocessors. Handling the high current in a
single-phase converter would place difficult requirements on the
power components such as inductor wire size, MOSFET ONresistance and thermal dissipation. The ADP3162’s high side
current sensing topology ensures that the load currents are balanced in each phase, such that neither phase has to carry more
than half of the power. An additional benefit of high side current
sensing over output current sensing is that the average current
through the sense resistor is reduced by the duty cycle of the
converter allowing the use of a lower power, lower cost resistor.
The outputs of the ADP3162 are logic drivers only and are
not intended to directly drive external power MOSFETs.
Instead, the ADP3162 should be paired with drivers such as
the ADP3412, ADP3413, or ADP3414.
The frequency of the ADP3162 is set by an external capacitor
connected to the CT pin. Each output phase of the ADP3162
operates at half of the frequency set by the CT pin. The error
amplifier and current sense comparator control the duty cycle of
the PWM outputs to maintain regulation. The maximum duty
cycle per phase is inherently limited to 50% because the PWM
outputs toggle in two-phase operation. While one phase is on,
the other phase is off. In no case can both outputs be high at the
same time.
Output Voltage Sensing
The output voltage is sensed at the FB pin allowing for remote
sensing. To maintain the accuracy of the remote sensing, the
GND pin should also be connected close to the load. A voltage
error amplifier (gm) amplifies the difference between the output
voltage and a programmable reference voltage. The reference
voltage is programmed between 1.05 V and 1.825 V by an internal
5-bit DAC, which reads the code at the voltage identification
(VID) pins. (Refer to Table I for the output voltage versus VID pin
code information.)
Active Voltage Positioning
The ADP3162 uses Analog Devices Optimal Positioning Technology (ADOPT), a unique supplemental regulation technique
that uses active voltage positioning and provides optimal compensation for load transients. When implemented, ADOPT adjusts
the output voltage as a function of the load current, so that it is
always optimally positioned for a load transient. Standard (passive)
voltage positioning has poor dynamic performance, rendering
it ineffective under the stringent repetitive transient conditions
required by high performance processors. ADOPT, however,
provides optimal bandwidth for transient response that yields
optimal load transient response with the minimum number of
output capacitors.
Reference Output
A 3.0 V reference is available on the ADP3162. This reference
is normally used to set the voltage positioning accurately using a
resistor divider to the COMP pin. In addition, the reference can
be used for other functions such as generating a regulated voltage
with an external amplifier. The reference is bypassed with a 1 nF
capacitor to ground. It is not intended to supply current to large
capacitive loads, and it should not be used to provide more than
1 mA of output current.
–5–
ADP3162
If for some reason one of the phases fails, the other phase will still
be limited to its maximum output current (one-half of the short
circuit current limit). If this is not sufficient to supply the load,
the output voltage will droop and cause the PWRGD output to
signal that the output voltage has fallen out of its specified range.
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage-error amplifier and the current comparator are the
main control elements. The voltage at the CT pin of the oscillator ramps between 0 V and 3 V. When that voltage reaches 3 V,
the oscillator sets the driver logic, which sets PWM1 high. During the ON time of Phase 1, the driver IC turns on the high-side
MOSFET. The CS+ and CS– pins monitor the current through
the sense resistor that feeds both high-side MOSFETs. When
the voltage between the two pins exceeds the threshold level
set by the voltage error amplifier (gm), the driver logic is reset
and the PWM output goes low. This signals the driver IC to turn
off the high-side MOSFET and turn on the low-side MOSFET.
On the next cycle of the oscillator, the driver logic toggles and
sets PWM2 high. On each following cycle of the oscillator, the
outputs toggle between PWM1 and PWM2. In each case, the
current comparator resets the PWM output low when the current
comparator threshold is reached. As the load current increases,
the output voltage starts to decrease. This causes an increase in
the output of the gm amplifier, which in turn leads to an increase
in the current comparator threshold, thus programming more
current to be delivered to the output so that voltage regulation is
maintained.
Short Circuit Protection
The ADP3162 has multiple levels of short circuit protection to
ensure fail-safe operation. The sense resistor and the maximum
current sense threshold voltage given in the specifications set the
peak current limit.
When the load current exceeds the current limit, the excess current
discharges the output capacitor. When the output voltage is below
the foldback threshold VFB(LOW), the maximum deliverable output
current is cut by reducing the current sense threshold from the
current limit threshold, VCS(CL), to the foldback threshold,
VCS(FOLD). Along with the resulting current foldback, the oscillator frequency is reduced by a factor of five when the output is
0 V. This further reduces the average current in short circuit.
Power-Good Monitoring
The Power-Good comparator monitors the output voltage of the
supply via the FB pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the specified range of
the nominal output voltage requested by the VID DAC. PWRGD
will go low if the output is outside this range.
Active Current Sharing
The ADP3162 ensures current balance in the two phases by
actively sensing the current through a single sense resistor. During
one phase’s ON time, the current through the respective high-side
MOSFET and inductor is measured through the sense resistor
(R4 in Figure 2). When the comparator (CMP1 in the Functional
Block Diagram) threshold programmed by the gm amplifier is
reached, the high-side MOSFET turns off. In the next cycle the
ADP3162 switches to the second phase. The current is measured
with the same sense resistor and the same internal comparator,
ensuring accurate matching. This scheme is immune to imbalances
in the MOSFETs’ RDS(ON) and inductors’ parasitic resistances.
VIN 5V
+
+
C12
+
C13
C14
+
Output Crowbar
The ADP3162 includes a crowbar comparator that senses when
the output voltage rises higher than the specified trip threshold, VCROWBAR. This comparator overrides the control loop and
sets both PWM outputs low. The driver ICs turn off the high side
MOSFETs and turn on the low-side MOSFETs, thus pulling the
output down as the reversed current builds up in the inductors. If
the output overvoltage is due to a short of the high side MOSFET,
this action will current limit the input supply or blow its fuse,
R7
20⍀
C15
VIN RTN
1000F ⴛ 4
12V VCC
R6
10⍀
U1
ADP3162
1 VID3
VCC 16
2 VID2
REF 15
3 VID1
CS– 14
C21
15nF
C26
4.7F
R4
4m⍀
C9
1F
U2
ADP3412
Q5
FMMT18
R8
330⍀
C4
4.7F
D1
MBR052LTI
R5
2.4k⍀
Z1
ZMM5236BCT
1 BST
C23
330pF
2 IN
DRVH 8
SW 7
Q1
IRL3803
L1
1H
C22 1nF
RA
10.1k⍀
1%
RB
19.1k⍀
1%
FROM
CPU
COC
3.3nF
4 VID0
PWM1 13
5 VID25
PWM2 12
6 COMP
CS+ 11
7 FB
PWRGD 10
8 CT
GND 9
C5
1F
U3
ADP3412
1 BST
2 IN
3 DLY
C2
100pF
R1
1k⍀
C6
1F
C8
15pF
PGND 6
4 VCC
DRVL 5
C7
15pF
Q2
IRL3803
C10
1F
D2
MBR052LTI
C1
91pF
3 DLY
4 VCC
DRVH 8
SW 7
1000F ⴛ 8
RUBYCON ZA SERIES
24m⍀ ESR (EACH)
Q3
IRL3803
L2
1H
VCC(CORE)RTN
PGND 6
DRVL 5
VCC(CORE)
1.7V
30A
Q4
IRL3803
C16 C17 C18 C19 C20 C27 C28 C29
Figure 2. 23 A Pentium® III CPU Supply Circuit
Pentium is a registered trademark of Intel Corporation.
–6–
REV. A
ADP3162
protecting the microprocessor from destruction. The crowbar
comparator releases when the output drops below the specified
reset threshold, and the controller returns to normal operation if
the cause of the overvoltage failure does not persist.
equation shows the relationship between the inductance, oscillator frequency, peak-to-peak ripple current in an inductor, and
input and output voltages:
Output Disable
The ADP3162 includes an output disable function that turns off
the control loop to bring the output voltage to 0 V. Because an
extra pin is not available, the disable feature is accomplished by
pulling the COMP pin to ground. When the COMP pin drops
below 0.64 V, the oscillator stops and both PWM signals are
driven low. This function does not place the part in a low quiescent
current shutdown state, and the reference voltage is still available.
The COMP pin should be pulled down with an open collector
or open drain type of output capable of sinking at least 2 mA.
APPLICATION INFORMATION
A VRM 8.5-Compliant Design Example
The design parameters for a typical high-performance Intel
Tualatin CPU application designed to meet Intel’s VRM 8.5
specification are as follows:
Input voltage (VIN) = 5 V
VID setting voltage (VOUT) = 1.8 V
Nominal output voltage at no load (VONL) = 1.845 V
Nominal output voltage at full load (VOFL) = 1.755 V
Static output voltage drop based on a 3.2 mΩ load line
(ROUT) from no load to full load (V∆) = (VONL) – (VOFL) =
1.845 V – 1.755 V = 90 mV
Maximum output current (IO) = 28 A
CT Selection—Choosing the Clock Frequency
The ADP3162 uses a fixed-frequency control architecture that is
set by an external timing capacitor, CT. The value of CT for a given
clock frequency can be selected using the graph in TPC 1.
The clock frequency determines the switching frequency, which
relates directly to switching losses and the sizes of the inductors
and input and output capacitors. A clock frequency of 400 kHz
sets the switching frequency of each phase, fSW, to 200 kHz,
which represents a practical trade-off between the switching
losses and the sizes of the output filter components. From TPC
1, for 400 kHz the required timing capacitor value is 150 pF. For
good frequency stability and initial accuracy, it is recommended to
use a capacitor with low temperature coefficient and tight tolerance, e.g., an MLC capacitor with NPO dielectric and with 5%
or less tolerance.
Inductance Selection
The choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFETs, but allows using smaller-size inductors and, for
a specified peak-to-peak transient deviation, output capacitors
with less total capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger-size inductors and more output capacitance for
the same peak-to-peak transient deviation. In a two-phase converter a practical value for the peak-to-peak inductor ripple
current is under 50% of the dc current in the same inductor.
With that choice, in this design example, under 50% ripple
current per inductor yields a total peak-to-peak output ripple current of about 20% of the total dc output current. The following
REV. A
L=
(VIN – VOUT ) × VOUT
VIN × fSW × IL ( RIPPLE )
(1)
For 7 A peak-to-peak ripple current, which is 50% of the 14 A
full-load dc current in an inductor, Equation 1 yields an inductance of:
L=
(5V – 1.8 V ) × 1.8 V
5V × (400 kHz / 2 ) × 7 A
= 823 nH
A 1 µH inductor can be used, which gives a calculated ripple
current of 5.8 A at no load. The inductor should not saturate at
the peak current of 20 A and should be able to handle the sum
of the power dissipation caused by the average current of 15 A
in the winding and the core loss.
The output ripple current is smaller than the inductor ripple
current due to the two phases partially canceling. This can be
calculated as follows:
IO∆ =
IO∆
VOUT × (VIN – 2 × VOUT )
VIN × L × fSW
1.8 V × (5V – 2 × 1.8 V )
=
= 2.5 A
5V × 1 µH × (400 kHz / 2 )
(2)
Designing an Inductor
Once the inductance is known, the next step is either to design an
inductor or find a standard inductor that comes as close as possible
to meeting the overall design goals. The first decision in designing the inductor is to choose the core material. There are several
possibilities for providing low core loss at high frequencies. Two
examples are the powder cores (e.g., Kool-Mµ® from Magnetics)
and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips).
Low frequency powdered iron cores should be avoided due to
their high core loss, especially when the inductor value is relatively
low and the ripple current is high.
Two main core types can be used in this application. Open
magnetic loop types, such as beads, beads on leads, and rods
and slugs, provide lower cost but do not have a focused magnetic field in the core. The radiated EMI from the distributed
magnetic field may create problems with noise interference in
the circuitry surrounding the inductor. Closed-loop types, such
as pot cores, PQ, U, and E cores, or toroids, cost more, but
have much better EMI/RFI performance. A good compromise
between price and performance are cores with a toroidal shape.
There are many useful references for quickly designing a power
inductor. Table II gives some examples.
Table II. Magnetics Design References
Magnetic Designer Software
Intusoft (http://www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-DC
Converters
McLyman, Kg Magnetics
ISBN 1-883107-00-08
–7–
ADP3162
In this formula, n is the number of phases, and η is the converter efficiency, in this case assumed to be 85%. Combining
Equations 6 and 7 yields:
Selecting a Standard Inductor
The companies listed in Table III can provide design consultation and deliver power inductors optimized for high power
applications upon request.
2
PRSENSE =
Table III. Power Inductor Manufacturers
28 A
1.8 V
×
× 4 mΩ = 664 mW
2
0.85 × 5V
Output Resistance
Intel’s VRM 8.5 specification requires that the regulator
output voltage measured at the CPU pins drops when the
output current increases. The specified voltage drop corresponds to a dc output resistance of:
Coilcraft
(847) 639-6400; (800) 322-2645
http://www.coilcraft.com
Coiltronics
(561) 752-5000
http://www.coiltronics.com
ROUT =
Sumida Electric Company
(408) 982-9660
http://www.sumida.com
RT =
The value of RSENSE is based on the required maximum output
current. The current comparator of the ADP3162 has a minimum current limit threshold of 69 mV. Note that the 69 mV
value cannot be used for the maximum specified nominal current, as headroom is needed for ripple current and tolerances.
VCS ( CL )( MIN )
69 mV
=
= 4.08 mΩ
IO IL ( RIPPLE ) 14 A + 2 A
+
2
2
Intel’s VRM 8.5 specification requires that at no load the output
voltage of the regulator module be offset to a higher value than
the nominal voltage corresponding to the VID code. The offset
is introduced by realizing the total termination resistance of the
gm amplifier with a divider connected between the REF pin and
ground. The resistive divider introduces an offset to the output
of the gm amplifier that, when reflected back through the gain
of the gm stage, accurately positions the output voltage near its
allowed maximum at light load. Furthermore, the output of the
gm amplifier sets the current sense threshold voltage. At no
load, the current sense threshold is increased by the peak of the
ripple current in the inductor and reduced by the delay between
sensing when the current threshold has been reached and when
the high side MOSFET actually turns off. These two factors are
combined with the inherent voltage (VGNL0), at the output of the
gm amplifier that commands a current sense threshold of 0 mV:
(3)
Once RSENSE has been chosen, the maximum output current can
be calculated at the point where current limit is reached, using
the maximum current sense threshold of 89 mV:
RSENSE
− IL ( RIPPLE ) = 2 ×
89 mV
− 5.8 A = 38.7 A
4 mΩ
(4)
At output voltages below 375 mV, the current sense threshold is
reduced to 58 mV maximum, and the ripple current is negligible. Therefore, at dead short the maximum output current is
reduced to:
IOUT ( SC ) = 2 ×
58 mV
= 29 A
4 mΩ
VGNL = VGNL 0 +
2
IL ( RIPPLE ) × ROUT × nI
2
−
VIN − VOUT
×
L
tD × nφ × RSENSE × nI
(5)
5.8 A × 3.2 mΩ × 25 5V − 1.8 V
−
×
2
1 µH
60 ns × 2 × 4 mΩ × 25 = 1.194 V
VGNL = 1V +
The capability of the resistor’s power rating should be checked
at maximum load current:
PRSENSE = ISENSE ( RMS ) × RSENSE
(9)
Output Offset
In this design example, 4 mΩ was chosen as the closest standard
value.
VCS ( CL )( MAX )
nI × RSENSE
25 × 4 mΩ
=
= 7.1 kΩ
gm × ROUT × 2 2.2 mmho × 3.2 mΩ × 2
where nI is the division ratio from the output voltage signal of
the g m amplifier to the PWM comparator CMP1, gm is the
transconductance of the gm amplifier itself, and the factor of 2
is the result of the two-phase configuration.
The current comparator threshold sets the peak of the inductor
current yielding a maximum output current, IO, which equals
twice the peak inductor current value less half of the peak-topeak inductor ripple current. From this the maximum value of
RSENSE is calculated as:
IOUT ( CL ) = 2 ×
(8)
The required dc output resistance can be achieved by terminating
the gm amplifier with a resistor. The value of the total termination resistance that will yield the correct dc output resistance:
RSENSE
RSENSE ≤
VONL − VOFL 1.845V − 1.755V
=
= 3.2 mΩ
∆IO
28 A
(10)
The divider resistors (RA for the upper, and RB for the lower)
can now be calculated assuming that the internal resistance of
the gm amplifier (ROGM) is 200 kΩ:
(6)
where:
2
2
ISENSE ( RMS ) =
IO
V
× OUT
η × VIN
n
(7)
–8–
REV. A
ADP3162
RB =
RB =
larger than the critical value defined by Equation 14, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
VREF
VREF − VGNL
− g m × (VONL − VOUT )
RT
3V
= 19.31 kΩ
3V − 1.194 V
− 2.2 mmho × 45 mV
7.1 kΩ
(11)
Choosing the nearest 1% resistor gives RB = 19.1 kΩ. Finally,
RA is calculated:
RA =
1
1
1
−
RT ROGM
1
=
= 11.98 kΩ
1
1
1
1
(12)
−
−
−
7.1 kΩ 200 kΩ 19.1 kΩ
RB
Choosing the nearest 1% resistor gives RA = 12.1 kΩ.
COUT Selection
The required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capacitors. The ESR of the output filter capacitor bank must be equal
to or less than the specified output resistance (3.2 mΩ) of the
voltage regulator. The capacitance must be large enough that
the voltage across the capacitor, which is the sum of the resistive
and capacitive voltage drops, does not moves below or above the
initial resistive step while the inductor current ramps up or
down to the value corresponding to the new load current.
One can use, for example, four SP-Type OS-CON capacitors
from Sanyo, with 820 µF capacitance, a 4 V voltage rating,
and 12 mΩ ESR. The four capacitors have a maximum total
ESR of 3 mΩ when connected in parallel. Another possibility is
the ZA series from Rubycon. The trade-off is size versus cost.
Eight 1000 µF capacitors would give an ESR of 3 mΩ. These
eight capacitors take up more space than four OS-CON capacitors, but are significantly less expensive.
As long as the capacitance of the output capacitor is above a
critical value and the regulating loop is compensated with
Analog Devices’ proprietary compensation technique, ADOPT,
the actual value has no influence on the peak-to-peak deviation
of the output voltage to a full step change in the load current.
The critical capacitance can be calculated as follows:
COUT ( CRIT ) =
(13)
The equivalent capacitance of the four OS-CON capacitors is
4 × 820 µF = 3.28 mF, and the equivalent capacitance of the
eight ZA series Rubycon capacitors is 8 mF. With both choices,
the total capacitance is safely above the critical value.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3162 allows the best possible containment of the peak-to-peak output voltage deviation.
The output current slew rate of any practical switching power
converter is inherently limited by the inductor to a value much
less than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and assuming that the capacitance of the output capacitor is
REV. A
With an ideal current-mode controlled converter, where the
inductor current would respond without delay to the command
signal, the resistive output impedance could be achieved by having
a single-pole roll-off of the voltage gain of the voltage-error
amplifier. The pole frequency must coincide with the ESR zero
of the output capacitor. The ADP3162 uses constant-frequency
peak-current control, which is known to have a nonideal, frequency
dependent command-signal-to-inductor-current transfer function. The frequency dependence manifests in the form of a pair
of complex conjugate poles at one-half of the switching frequency.
A purely resistive output impedance could be achieved by canceling the complex conjugate with zeros at the same complex
frequencies and adding a third pole equal to the ESR zero of the
output capacitor. Such a compensating network would be quite
complicated. Fortunately, in practice it is sufficient to cancel the
pair of complex conjugate poles with a single real zero placed at
one-half of the switching frequency. Although the end result is
not a perfectly resistive output impedance, the remaining frequency dependence causes only a few percentage of deviation
from the ideal resistive response. The single-pole and single-zero
compensation can be easily implemented by terminating the gm
error amplifier with the parallel combination of a resistor (RT)
and a series RC network. The value of the terminating resistor
RT was determined previously; the capacitance and resistance of
the series RC network are calculated as follows:
COC =
COUT × ROUT
2
−
π × fOSC × RT
RT
(14)
For the Rubycon output capacitors, the compensating capacitor is:
COC =
IO
L
×
ROUT × VOFL 2
28 A
1 µH
×
= 2.49 mF
3.2 mΩ × 1.755V
2
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range—
including dc—and equal to the specified dc output resistance.
With the wide-band resistive output impedance the output
voltage will droop in proportion with the load current at any
load current slew rate; this ensures the optimal positioning and
allows the minimization of the output capacitor.
8 mF × 3 mΩ
2
−
= 3.16 nF
7.1 kΩ
π × 400 kHz × 7.1 kΩ
The closest standard value is 3.3 nF.
RZ =
COC
2
2
=
= 483 Ω (15)
× π × fOSC 3.3 nF × π × 400 kHz
The nearest standard 5% resistor value is 470 Ω. Note that this
resistor is only required when COUT approaches CCRIT (within
25% or less). In this example COUT >> CCRIT, and RZ can therefore be omitted.
Power MOSFETs
In the standard two-phase application two pairs of N-channel
power MOSFETs must be used with the ADP3162 and ADP3412,
one pair as the main (control) switches, and the other pair as
the synchronous rectifier switches. The main selection parameters
for the power MOSFETs are VGS(TH) and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3412)
–9–
ADP3162
dictates whether standard threshold or logic-level threshold
MOSFETs must be used. Since VGATE < 8 V, logic-level threshold
MOSFETs (VGS(TH) < 2.5 V) are strongly recommended.
The maximum output current IO determines the RDS(ON) requirement for the power MOSFETs. When the ADP3162 is operating
in continuous mode, the simplifying assumption can be made
that in each phase one of the two MOSFETs is always conducting the average inductor current. For VIN = 12 V and VOUT =
1.7 V, the duty ratio of the high-side MOSFET is:
DHSF =
VOUT 1.8 V
=
= 36%
VIN
5V
(16)
The duty ratio of the low-side (synchronous rectifier) MOSFET is:
DLSF ( MAX ) = 1 − DHSF ( MAX ) = 64%
(17)
The maximum rms current of the high-side MOSFET during
normal operation is:
IHSF ( MAX )
I
= O
2
DHSF
where the second term represents the turn-off loss of the
MOSFET and the third term represents the turn-on loss due to
the stored charge in the body diode of the low-side MOSFET.
(In the second term, QG is the gate charge to be removed from
the gate for turn-off and IG is the gate turn-off current. From the
data sheet, for the IRL3803 the value of QG is about 140 nC
and the peak gate drive current (IG) provided by the ADP3412
is about 1 A. In the third term Qrr is the charge stored in the
body diode of the low-side MOSFET at the valley of the inductor current. The data sheet of the IRL3803 gives 450 nC for the
stored charge at 71 A. That value corresponds to a stored charge of
80 nC at the valley of the inductor current. In both terms fSW is
the actual switching frequency of the MOSFETs, or 200 kHz.
IL(PK) is the peak current in the inductor, or 17.8 A.)
Substituting the above data in Equation 23 and using the worstcase value for the MOSFET resistance yields a conduction loss
of 0.7 W, a turn-off loss of 1.2 W, and a turn-on loss of 0.08 W.
Thus the worst-case total loss in a high-side MOSFET is 1.98 W.
The worst-case low-side MOSFET dissipation is:
2
I ( RIPPLE )
× 1 + L
=
2
3 × IO
PLSF = RDS (ON )LS × I 2 LSF ( MAX ) = 9 mΩ × 11.3 A2 = 1.15 W (24)
(Note that there are no switching losses in the low-side MOSFET.)
28 A
5.8 A2
0.36 × 1 +
= 8.5 A
2
3 × 28 A2
(18)
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to VOUT/VIN and an amplitude of one-half of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
The maximum rms current of the low-side MOSFET is:
DLSF
= 11.3 A
DHSF
ILSF ( MAX ) = IHFS ( MAX ) ×
(19)
IC ( RMS ) =
The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the maximum output power is
allowed for MOSFET dissipation, the total dissipation in the
four MOSFETs of the two-phase converter will be:
PMOSFET (TOTAL ) = 0.1 × VOUT × IO = 0.1 × 1.8 V × 28 A = 5.0 W
CIN Selection and Input Current di/dt Reduction
IO
2
2 × DHFS − (2 × DHFS )2 =
(25)
28 A
2 × 0.36 − (2 × 0.36 )2 = 6.3 A
2
(20)
Allocating half of the total dissipation for the pair of high-side
MOSFETs and half for the pair of low-side MOSFETs, and
assuming that the resistive and switching losses of the high-side
MOSFET are equal, the required maximum MOSFET resistances will be:
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2000 hours of life. This makes it advisable
to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
four 1000 µF, 16 V Rubycon capacitors.
The ripple voltage across the three paralleled capacitors is:
RDS ( ON )HS ( MAX ) =
RDS ( ON )LS ( MAX ) =
PMOSFET (TOTAL )
8 × I 2HSF ( MAX )
PMOSFET (TOTAL )
4 × I 2LSF ( MAX )
=
5.0 W
=
= 8.6 mΩ (21)
8 × (8.5 A )2
5.0 W
= 9.8 mΩ
4 × (11.3 A )2
+ VIN × Qrr × fSW
(26)
To reduce the input-current di/dt to below the recommended
maximum of 0.1 A/µs, an additional small inductor (L > 1 µH
@ 5 A) should be inserted between the converter and the supply
bus. That inductor also acts as a filter between the converter
and the primary power source.
PHSF = RDS ( ON )HS × I 2HSF ( MAX ) +
2 × IG
IO ESRC
DHSF
×
+
=
n nC
nC × CIN × fSW
28 A 24 mΩ
0.36
×
+
= 90 mV
2
4 × 1000 µF × 200 kHz
4
(22)
An IRL3803 MOSFET from International Rectifier (RDS(ON) =
6 mΩ nominal, 9 mΩ worst-case) is a good choice for both the
high-side and low-side. The high-side MOSFET dissipation is:
VIN × IL ( PK ) × QG × fSW
VC ( RIPPLE ) =
(23)
–10–
REV. A
ADP3162
PC system as well as noise-related operational problems in
the power converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors, the power MOSFETs, and the power
Schottky diode, if used (see next), including all interconnecting PCB traces and planes. The use of short and wide
interconnection traces is especially critical in this path for two
reasons: it minimizes the inductance in the switching loop,
which can cause high-energy ringing, and it accommodates
the high current demand with minimal voltage loss.
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
General Recommendations
1.
For good results, at least a four-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, a signal ground
plane, power planes for both power ground and the input
power (e.g., 5 V), and wide interconnection traces in the
rest of the power delivery current paths. Keep in mind that
each square unit of 1 ounce copper trace has a resistance
of ~ 0.53 mΩ at room temperature.
2.
Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance introduced by these current paths is minimized and the via
current rating is not exceeded.
3.
If critical signal lines (including the voltage and current
sense lines of the ADP3162) must cross through power
circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
4.
The power ground plane should not extend under signal
components, including the ADP3162 itself. If necessary,
follow the preceding guideline to use the signal ground
plane as a shield between the power ground plane and the
signal circuitry.
5.
The GND pin of the ADP3162 should be connected first
to the timing capacitor (on the CT pin), and then into the
signal ground plane. In cases where no signal ground plane
can be used, short interconnections to other signal ground
circuitry in the power converter should be used.
6.
The output capacitors of the power converter should be
connected to the signal ground plane even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections
(e.g., the signal circuitry of the power converter) in the
signal ground plane between the input and output capacitors. It is also advised to keep the planar interconnection
path short (i.e., have input and output capacitors close
together).
7.
The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors also should be distributed, and generally in proportion to where the load tends to be more dynamic.
8.
Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
Power Circuitry
9.
The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the entire
REV. A
10. An optional power Schottky diode (3 A–5 A dc rating) from
each lower MOSFET’s source (anode) to drain (cathode)
will help to minimize switching power dissipation in the
upper MOSFETs. In the absence of an effective Schottky
diode, this dissipation occurs through the following sequence
of switching events. The lower MOSFET turns off in advance
of the upper MOSFET turning on (necessary to prevent
cross-conduction). The circulating current in the power
converter, no longer finding a path for current through the
channel of the lower MOSFET, draws current through the
inherent body diode of the MOSFET. The upper MOSFET
turns on, and the reverse recovery characteristic of the
lower MOSFET’s body diode prevents the drain voltage
from being pulled high quickly. The upper MOSFET then
conducts very large current while it momentarily has a high
voltage forced across it, which translates into added power
dissipation in the upper MOSFET. The Schottky diode
minimizes this problem by carrying a majority of the circulating current when the lower MOSFET is turned off, and
by virtue of its essentially nonexistent reverse recovery time.
The Schottky diode has to be connected with very short
copper traces to the MOSFET to be effective.
11. A small ferrite bead inductor placed in series with the drain
of the lower MOSFET can also help to reduce this previously described source of switching power loss.
12. Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for
this are: improved current rating through the vias, and
improved thermal performance from vias extended to the
opposite side of the PCB where a plane can more readily
transfer the heat to the air.
13. The output power path, though not as critical as the switching power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the output capacitors, and back to the input capacitors.
14. For best EMI containment, the power ground plane should
extend fully under all the power components except the
output capacitors. These components are: the input capacitors, the power MOSFETs and Schottky diodes, the
inductors, the current sense resistor, and any snubbing
element that might be added to dampen ringing. Avoid
extending the power ground under any other circuitry or
signal lines, including the voltage and current sense lines.
–11–
ADP3162
16. The CS+ and CS– traces should be Kelvin-connected to
the current sense resistor so that the additional voltage drop
due to current flow on the PCB at the current sense resistor
connections does not affect the sensed voltage.
Signal Circuitry
C02193–0–10/01(A)
15. The output voltage is sensed and regulated between the FB
pin and the GND pin (which connects to the signal ground
plane). The output current is sensed (as a voltage) by the
CS+ and CS– pins. In order to avoid differential mode
noise pickup in the sensed signal, the loop area should be
small. Thus the FB trace should be routed atop the signal
ground plane, and the CS+ and CS– pins should be routed
as a closely coupled pair (the CS+ pin should be over the
signal ground plane as well).
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC
(R-16A/SO-16)
0.3937 (10.00)
0.3859 (9.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
16
9
1
8
0.050 (1.27)
BSC
0.0098 (0.25)
0.0040 (0.10)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
8ⴗ
0.0192 (0.49) SEATING
0ⴗ 0.0500 (1.27)
0.0099 (0.25)
0.0138 (0.35) PLANE
0.0160 (0.41)
0.0075 (0.19)
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Change to Output Voltage and Output Current Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PRINTED IN U.S.A.
Changes to APPLICATION INFORMATION section, including equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
–12–
REV. A
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