ADP3208DJCPZ-RL

ADP3208D 7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller The ADP3208D is a highly efficient, multiphase, synchronous buck switching regulator controller. With its integrated drivers, the ADP3208D is optimized for converting the notebook battery voltage into the core supply voltage required by high performance Intel processors. An internal 7−bit DAC is used to read a VID code directly from the processor and to set the CPU core voltage to a value within the range of 0.3 V to 1.5 V. The phase relationship of the output signals ensures interleaved 2−phase operation. The ADP3208D uses a multi−mode architecture run at a programmable switching frequency and optimized for efficiency depending on the output current requirement. The ADP3208D switches between single− and dual−phase operation to maximize efficiency with all load conditions. The chip includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. The ADP3208D also provides accurate and reliable short−circuit protection, adjustable current limiting, and a delayed power−good output. The IC supports On−The−Fly (OTF) output voltage changes requested by the CPU. The ADP3208D is specified over the extended commercial temperature range of −10°C to 100°C and is available in a 48−lead LFCSP. Features http://onsemi.com LFCSP48 CASE 932AD MARKING DIAGRAM ADP3208D AWLYYWWG A WL YYWW G = Assembly Location = Wafer Lot = Date Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 36 of this data sheet. • Single−Chip Solution • Fully Compatible with the Intel® IMVP−6+t • Short−Circuit Protection with Latchoff Delay • Clock Enable Output Delays the CPU Clock Until the • Integrated MOSFET Drivers • Input Voltage Range of 3.3 V to 22 V • Selectable 1− or 2−Phase Operation with Up to 1 MHz • Output Load Current Monitor • This is a Pb−Free Device Specifications • • • • • • • Core Voltage is Stable Applications per Phase Switching Frequency Guaranteed ±8 mV Worst−Case Differentially Sensed Core Voltage Error Overtemperature Automatic Power−Saving Mode Maximizes Efficiency with Light Load During Deeper Sleep Operation Soft Transient Control Reduces Inrush Current and Audio Noise Active Current Balancing Between Output Phases Independent Current Limit and Load Line Setting Inputs for Additional Design Flexibility Built−In Power−Good Blanking Supports Voltage Identification (VID) OTF Transients 7−Bit, Digitally Programmable DAC with 0.3 V to 1.5 V Output © Semiconductor Components Industries, LLC, 2010 February, 2010 − Rev. 0 • Notebook Power Supplies for Next Generation Intel® Processors 1 Publication Order Number: ADP3208D/D ADP3208D GND VCC EN RPM RT RAMP BST1 UVLO Shutdown and Bias COMP + Σ REF LLINE + VEA − + CSREF + Σ Oscillator _ 1.7V DRVH1 Driver Logic Current Balancing Circuit − + FB VARFREQ SP SW1 PVCC1 DRVL1 PGND1 OVP BST2 DRVH2 PSI SW2 Thermal Throttle Control TTSNS VRTT PVCC2 DRVL2 PGND2 DAC − 200mV DAC − 300mV CLKEN FBRTN − + PWRGD Startup Delay PWRGD Open Drain Precision Reference VID0 + − IMON CSREF CSSUM CSCOMP ILIMN ILIMP DAC VID2 VID1 VID3 VID4 DPRSLP Delay Disable CLKEN Startup Delay VID DAC DPRSTP Current Monitor Soft Transient Delay CLKEN Open Drain VID6 VID5 Current Limit Circuit DPRSTP DPRSLP Logic REF Soft−Start Soft Transient IREF CSREF PWRGD OCP Shutdown Delay − + Figure 1. Functional Block Diagram ABSOLUTE MAXIMUM RATINGS Rating Unit VCC, PVCC1, PVCC2 Parameter −0.3 to +6.0 V FBRTN, PGND1, PGND2 −0.3 to +0.3 V BST1, BST2 DC t < 200 ns −0.3 to +28 −0.3 to +33 BST1 to SW1, BST2 to SW2 −0.3 to +6.0 SW1, SW2 DC t < 200 ns −5.0 to +22 −10 to +28 DRVH1 to SW1, DRVH2 to SW2 −0.3 to +6.0 DRVL1 to PGND1, DRVL2 to PGND2 DC t < 200 ns −0.3 to +6.0 −5.0 to +6.0 V V V V V RAMP (In Shutdown) DC −0.3 to +22 All Other Inputs and Outputs −0.3 to +6.0 V V Storage Temperature −65 to +150 °C Operating Ambient Temperature Range −10 to 100 °C Operating Junction Temperature 125 °C Thermal Impedance (qJA) 2−Layer Board 40 °C/W Lead Temperature Soldering (10 sec) Infrared (15 sec) 300 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. http://onsemi.com 2 ADP3208D TEST CIRCUITS 7-BIT CODE 5.0 V ADP3208D PWRGD SP VCC VID6 VID4 VID5 VID3 VID1 VID2 PSI VID0 EN DPRSLP 1 1.05 V DPRSTP 48 37 VCC DRVH1 SW1 NC CLKEN# PVCC1 FB DRVL1 FBRTN DRVL2 NC PVCC2 1 kW 18 CSSUM CSREF + GND ILIMP RT ILIMN RAMP CSSUM 1.0 V 24 GND 80 kW - BST2 CSREF LLINE IREF TTSNS CSCOMP VRTT CSCOMP 100 nF 19 SW2 DRVH2 VARFREQ IMON 39 k W PGND2 NC RPM 17 PGND1 ADP3208D COMP 1 kW 5.0 V BST1 Vos = CSCOMP - 1.0 V 40 V 20 kW 100 nF Figure 2. Closed−Loop Output Voltage Accuracy Figure 3. Current Sense Amplifier, VOS ADP3208D 5.0 V 37 VCC 7 10 k W 6 COMP FB + 16 ΔV 18 LLINE CSREF VID DAC 1.0 V 24 GND D VFB = FBDV = V − FBDV=0mV Figure 4. Positioning Accuracy http://onsemi.com 3 ADP3208D PIN FUNCTION DESCRIPTIONS Pin No Mnemonic 1 EN 2 PWRGD Description Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTT low, and pulls CLKEN high. Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the VID DAC defined range. 3 NC 4 CLKEN Not Connected. Clock Enable Output. Open−drain output. A low logic state enables the CPU internal PLL clock to lock to the external clock. 5 FBRTN Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the ground return for the VID DAC and the voltage error amplifier blocks. 6 FB 7 COMP Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier. Voltage Error Amplifier Output and Frequency Compensation Point. 8 NC 9 IRPM/NC Not Connected. RPM Mode Timing Control Input. A resistor between this pin or RPM pin to ground sets the RPM mode turn−on threshold voltage. If a resistor is connected between this pin to ground, RPM pin must remain floating and not connected. 10 VARFREQ Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code. 11 VRTT 12 TTSNS 13 IMON Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to FBRTN sets the current monitor gain. 14 RPM RPM Mode Timing Control Input. A resistor between this pin or IRPM pin to ground sets the RPM mode turn−on threshold voltage. If a resistor is connected between this pin to ground, IRPM pin must remain floating. 15 IREF This pin sets the internal bias currents. A 80 kW resistor is connected from this pin to ground. 16 LLINE Load Line Programming Input. The center point of a resistor divider connected between CSREF and CSCOMP can be tied to this pin to set the load line slope. 17 CSCOMP 18 CSREF Current Sense Reference Input. This pin must be connected to the common point of the output inductors. The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop transient control of the converter output voltage. 19 CSSUM Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor currents to provide total current information. 20 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets the slope of the internal PWM stabilizing ramp used for phase−current balancing. 21 ILIMN Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter. 22 ILIMP Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter. 23 RT PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator frequency. 24 GND Analog and Digital Signal Ground. 25 BST2 High−Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage while the high−side MOSFET is on. 26 DRVH2 27 SW2 28 PVCC2 Power Supply Input/Output of Low−Side Gate Driver for Phase 2. 29 DRVL2 Low−Side Gate Drive Output for Phase 2. 30 PGND2 Low−Side Driver Power Ground for Phase 2. Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator temperature at the remote sensing point exceeded a set alarm threshold level. Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip. Current Sense Amplifier Output and Frequency Compensation Point. High−Side Gate Drive Output for Phase 2. Current Balance Input for Phase 2 and Current Return for High−Side Gate Drive. http://onsemi.com 4 ADP3208D Pin No Mnemonic 31 PGND1 Low−Side Driver Power Ground for Phase 1. Description 32 DRVL1 Low−Side Gate Drive Output for Phase 1. 33 PVCC1 Power Supply Input/Output of Low−Side Gate Driver for Phase 1. 34 SW1 35 DRVH1 36 BST1 High−Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage while the high−side MOSFET is on. 37 VCC Power Supply Input/Output of the Controller. Current Balance Input for Phase 1 and Current Return For High−Side Gate Drive. High−Side Gate Drive Output for Phase 1. SP VID6 to VID0 Single−Phase Select Input. Logic high state sets single−phase configuration. Voltage Identification DAC Inputs. A 7−bit word (the VID code) programs the DAC output voltage, the reference voltage of the voltage error amplifier without a load (see the VID code Table 3). 46 PSI Power State Indicator Input. Driving this pin low forces the controller to operate in single−phase mode. 47 DPRSTP Deeper Stop Control Input. The logic state of this pin is usually complementary to the state of the DPRSLP pin; however, during slow deeper sleep exit, both pins are logic low. 48 DPRSLP Deeper Sleep Control Input. DPRSLP DPRSTP PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 SP VCC 38 39 to 45 1 ADP3208D IMON RPM IREF LLINE CSCOMP CSREF CSSUM RAMP ILIMIN ILIMP RT GND EN PWRGD NC CLKEN FBRTN FB COMP NC IRPM/NC VARFREQ VRTT TTSNS Figure 5. Pin Configuration (Top View) http://onsemi.com 5 BST1 DRVH1 SW1 PVCC1 DRVL1 PGND1 PGND2 DRVL2 PVCC2 SW2 DRVH2 BST2 ADP3208D ELECTRICAL CHARACTERISTICS VCC = PVCC1 = PVCC2 = BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW. Symbol Parameter Conditions Min Typ Max Unit VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP) FB, LLINE Voltage Range (Note 2) VFB, VLLINE Relative to CSREF = VDAC −200 +200 mV FB, LLINE Offset Voltage (Note 2) VOSVEA Relative to CSREF = VDAC −0.5 +0.5 mV −100 100 A −82 mV FB LLINE Bias Current (Note 2) LLINE Positioning Accuracy IFB VFB − VVID Measured on FB relative to VVID, LLINE forced 80 mV below CSREF −78 0.85 COMP Voltage Range VCOMP Operating Range COMP Current ICOMP COMP = 2.0 V, CSREF = VDAC FB forced 200 mV below CSREF FB forced 200 mV above CSREF SRCOMP CCOMP = 10 pF, CSREF = VDAC, Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF COMP Slew Rate Gain Bandwidth (Note 2) GBW −80 4.0 V mA −0.75 6.0 V/ms 15 −20 Non−inverting unit gain configuration, RFB = 1 kW 20 MHz VID DAC VOLTAGE REFERENCE VDAC Voltage Range (Note 3) VDAC Accuracy See VID Code Table VFB − VVID 0 Measured on FB (includes offset), relative to VVID, for VID table see Table 3, VVID = 1.2125 V to 1.5000 V VVID = 0.3000 V to 1.2000 V VDAC Differential Non−linearity (Note 2) VDAC Line Regulation VDAC Boot Voltage (Note 2) DVFB VBOOTFB 1.5 V mV −9.0 −7.5 +9.0 +7.5 −1.0 +1.0 LSB VCC = 4.75 V to 5.25 V 0.05 % Measured during boot delay period 1.200 V Soft−Start Delay (Note 2) tDSS Measured from EN pos edge to FB = 50 mV 200 ms Soft−Start Time tSS Measured from EN pos edge to FB settles to VBOOT = 1.2 V within −5% 1.7 ms tBOOT Measured from FB settling to VBOOT = 1.2 V within −5% to CLKEN neg edge 150 ms 0.0625 0.25 LSB/ms Boot Delay VDAC Slew Rate FBRTN Current Soft−Start Non−LSB VID step, DPRSLP = H, Slow C4 Entry/Exit Non−LSB VID step, DPRSLP = L, Fast C4 Exit 1.0 IFBRTN 90 200 −360 −360 −300 −300 −240 −160 mA VOLTAGE MONITORING AND PROTECTION − Power Good CSREF Undervoltage Threshold VUVCSREF Relative to DAC Voltage: CSREF Overvoltage Threshold VOVCSREF Relative to nominal DAC Voltage 150 200 250 mV CSREF Crowbar Voltage Threshold VCBCSREF Relative to FBRTN 1.57 1.7 1.78 V CSREF Reverse Voltage Threshold VRVCSREF Relative to FBRTN, Latchoff mode: CSREF Falling CSREF Rising −350 −300 −70 = 0.5 V to 1.5 V = 0.3 V to 0.4875 V 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. 3. Timing is referenced to the 90% and 10% points, unless otherwise noted. http://onsemi.com 6 mV mV −5.0 ADP3208D ELECTRICAL CHARACTERISTICS VCC = PVCC1 = PVCC2 = BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW. Parameter Symbol Conditions Min Typ Max Unit 50 150 mV 0.1 mA VOLTAGE MONITORING AND PROTECTION − Power Good PWRGD Low Voltage VPWRGD IPWRGD(SINK) = 4 mA PWRGD High, Leakage Current IPWRGD VPWRDG = 5.0 V PWRGD Startup Delay TSSPWRGD PWRGD Latchoff Delay Measured from CLKEN neg edge to PWRGD Pos Edge 8.0 ms TLOFFPWRGD Measured from Out−off−Good−Window event to Latchoff (switching stops) 8.0 ms TPDPWRGD Measured from Out−off−Good−Window event to PWRGD neg edge 200 ns Measured from Crowbar event to Latchoff (switching stops) 200 ns PWRGD Masking Time Triggered by any VID change or OCP event 100 ms CSREF Soft−Stop Resistance EN = L or Latchoff condition 70 W PWRGD Propagation Delay (Note 3) Crowbar Latchoff Delay (Note 2) TLOFFCB CURRENT CONTROL − Current Sense Amplifier (CSAMP) CSSUM, CSREF Common−Mode Range (Note 2) Voltage range of interest CSSUM, CSREF Offset Voltage VOSCSA TA = 25°C CSREF − CSSUM, TA = −10°C to 85°C CSREF − CSSUM, TA = −40°C to 85°C CSSUM Bias Current IBCSSUM CSREF Bias Current IBCSREF 0 2.0 V −0.5 −1.7 −1.8 +0.5 +1.7 +1.8 mV −50 +50 nA −120 +120 nA 0.05 2.0 V CSCOMP Voltage Range (Note 2) Operating Range CSCOMP Current CSCOMP = 2.0 V CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF −750 1.0 CCSCOMP = 10 pF, Open Loop Configuration CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF 10 −10 ICSCOMPsource ICSCOMPsink CSCOMP Slew Rate Gain Bandwidth (Note 2) GBWCSA Non−inverting unit gain configuration RFB = 1 kW mA mA V/ms 20 MHz CURRENT MONITORING AND PROTECTION Current Reference IREF Voltage Current Limiter (OCP) Current Limit Threshold Current Limit Latchoff Delay VREF VLIMTH RREF = 80 kW to set IREF = 20 mA Measured from CSCOMP to CSREF, RLIM = 4.5 kW, 2−ph configuration, PSI = H 2−ph configuration, PSI = L 1−ph configuration Measured from CSCOMP to CSREF, RLIM = 4.5 kW, 3−ph configuration, PSI = H 3−ph configuration, PSI = L 1−ph configuration Measured from OCP event to PWRGD deassertion 1.55 1.6 7 V mV −70 −32 −70 −95 −47.5 −95 −115 −65 −115 −70 −15 −70 −90 −30 −90 −115 −50 −115 8.0 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. 3. Timing is referenced to the 90% and 10% points, unless otherwise noted. http://onsemi.com 1.65 ms ADP3208D ELECTRICAL CHARACTERISTICS VCC = PVCC1 = PVCC2 = BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW. Parameter Symbol Conditions Min Typ Max Current Gain Accuracy IMON/ILIM Measured from ILIMP to IMON ILIM = −20 mA ILIM = −10 mA ILIM = −5 mA 9.5 9.3 9.0 10 10 10 10.5 10.7 11.0 IMON Clamp Voltage VMAXMON Relative to FBRTN, ILIMP = −30 mA 1.0 Unit CURRENT MONITOR 1.05 V V PULSE WIDTH MODULATOR − Clock Oscillator RT Voltage VRT VARFREQ = High, RT = 125 kW, VVID = 1.5000 V VARFREQ = Low, See also VRT(VVID) formula 1.22 1.25 1.27 0.98 1.0 1.02 PWM Clock Frequency Range (Note 2) fCLK Operating Range 0.3 PWM Clock Frequency fCLK TA = 25°C, VVID = 1.2000 V RT = 73 kW RT = 125 kW RT = 180 kW 3.0 MHz kHz 1200 680 400 1470 920 640 1720 1120 840 1.0 VIN 1.1 V RAMP GENERATOR RAMP Voltage VRAMP EN = high, IRAMP = 30 mA EN = low 0.9 RAMP Current Range (Note 2) IRAMP EN = high EN = low, RAMP = 19 V 1.0 −0.5 100 +0.5 mA VRAMP − VCOMP −3.0 3.0 mV PWM COMPARATOR PWM Comparator Offset (Note 2) VOSRPM RPM COMPARATOR RPM Current RPM Comparator Offset (Note 2) IRPM VOSRPM −8.8 VVID = 1.2 V, RT = 125 kW, VARFREQ = High, See also IRPM(RT) formula VCOMP − (1 +VRPM) −3.0 mA 3.0 mV EPWM CLOCK SYNC Relative to COMP sampled TCLK earlier 2−phase configuration 1−phase configuration Trigger Threshold (Note 2) mV 400 450 SWITCH AMPLIFIER SW Common Mode Range (Note 2) SW Resistance VSW(X)CM RSW_PGND(X) Operating Range for current sensing −600 +200 mV Measured from SW to PGND 3.0 kW ZERO CURRENT SWITCHING COMPARATOR SW ZCS Threshold VDCM(SW1) DCM mode, DPRSLP = 3.3 V −6.0 mV Masked Off Time tOFFMSKD Measured from DRVH neg edge to DRVH pos edge at max frequency of operation 700 ns SYSTEM I/O BUFFERS VID[6:0], PSI INPUTS Input Voltage Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v −5 mA Input Current V = 0.2 V VID[6:0], DPRSLP (active pulldown to GND) PSI (active pullup to VCC) VID Delay Time (Note 2) Any VID edge to FB change 10% 0.3 0.7 −1.0 +1.0 200 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. 3. Timing is referenced to the 90% and 10% points, unless otherwise noted. http://onsemi.com 8 V mA ns ADP3208D ELECTRICAL CHARACTERISTICS VCC = PVCC1 = PVCC2 = BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW. Parameter Symbol Conditions Min Typ Max Unit DPRSLP Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v −5 mA Input Voltage Input Current 1.0 2.3 DPRSLP = low DPRSLP = high −1.0 +2.0 V mA DPRSTP Input Voltage Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v −5 mA 0.3 0.7 Input Current 1.0 V mA VARFREQ, SP Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v −5 mA Input Voltage 0.7 4.0 Input Current 1.0 V mA EN INPUT Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v −5 mA Input Voltage Input Current 1.0 2.3 EN = L or EN = H (Static) 0.8 V < EN < 1.6 V (During Transition) 10 70 Output Low Voltage Logic low, Isink = 4 mA 50 Output High, Leakage Current Logic high, VCLKEN = VCC V nA mA CLKEN OUTPUT 100 mV 1.0 mA 5.0 V 2.55 V THERMAL MONITORING AND PROTECTION 0 TTSNS Voltage Range (Note 2) TTSNS Threshold VCC = 5.0 V, TTSNS is falling TTSNS Hysteresis TTSNS Bias Current VRTT Output Voltage TTSNS = 2.6 V VVRTT 2.45 2.5 50 110 −2.0 Logic low, IVRTT(SINK) = 400 mA Logic high, IVRTT(SOURCE) = −400 mA 4.0 10 5.0 mV 2.0 mA 100 mV V SUPPLY Supply Voltage Range VCC 5.5 V EN = H EN = 0 V 6.0 15 10 50 mA mA VCCOK VCC is Rising 4.3 4.5 V VCCUVLO VCC is Falling Supply Current VCC OK Threshold VCC UVLO Threshold 4.5 4.0 VCC Hysteresis (Note 2) 4.1 V 210 mV HIGH−SIDE MOSFET DRIVER Pullup Resistance, Sourcing Current BST = PVCC 1.8 3.3 W Pulldown Resistance, Sinking Current BST = PVCC 1.0 3.0 W 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. 3. Timing is referenced to the 90% and 10% points, unless otherwise noted. http://onsemi.com 9 ADP3208D ELECTRICAL CHARACTERISTICS VCC = PVCC1 = PVCC2 = BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW. Parameter Symbol Conditions Min Typ Max Unit BST = PVCC, CL = 3 nF, Figure 6 BST = PVCC, CL = 3 nF, Figure 6 15 13 35 31 ns BST = PVCC, Figure 6 39 50 ns EN = L (Shutdown) EN = H, no switching 0.6 15 5.0 mA Pullup Resistance, Sourcing Current BST = PVCC 1.6 3.3 W Pulldown Resistance, Sinking Current BST = PVCC 0.8 2.5 W trDRVL tfDRVL CL = 3 nF, Figure 6 CL = 3 nF, Figure 6 15 14 35 35 ns tpdhDRVL CL = 3 nF, Figure 6 10 45 ns 250 450 ns 1.0 240 15 mA 6.0 1.0 W HIGH−SIDE MOSFET DRIVER trDRVH tfDRVH Transition Times Dead Delay Times tpdhDRVH BST Quiescent Current LOW−SIDE MOSFET DRIVER Transition Times Progation Delay Times SW Transition Times tTOSW SW Off Threshold DRVH = L, SW = 2.5 V 210 VOFFSW 1.6 PVCC Quiescent Current EN = L (Shutdown) EN = H, no switching V BOOTSTRAP RECTIFIER SWITCH EN = L or EN = H and DRVL = H On Resistance 3.0 1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested. 3. Timing is referenced to the 90% and 10% points, unless otherwise noted. IN tpdlDRVL tfDRVL tpdlDRVH trDRVL DRVL tfDRVH tpdhDRVH DRVH (WITH RESPECT TO SW) trDRVH VTH VTH tpdhDRVL 1.0 V SW Figure 6. Timing Diagram (Note 3) http://onsemi.com 10 ADP3208D TYPICAL PERFORMANCE CHARACTERISTICS VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted. 95 VIN = 9.0 V 90 SW2 EFFICIENCY (%) 85 80 SW1 VIN = 9.0 V 75 70 65 60 VOUT = 1.2 V OUTPUT VOLTAGE 55 fSW = 305 kHz Input = 12 V, Output = 1.0 V 44 A to 9 A Load Step 50 0 5 10 15 20 25 30 35 40 45 LOAD CURRENT (A) Figure 7. PWM Mode Efficiency vs. Load Current Figure 8. Load Transient with 2−Phases OUTPUT RIPPLE SW2 SW1 CSREF to CSCOMP SW1 OUTPUT VOLTAGE SW2 Input = 12 V, Output = 1.0 V 9 A to 44 A Load Step Input = 12 V, Output = 1.1 V No Load Figure 9. Load Transient with 2 Phases Figure 10. Switching Waveforms in 2 Phase 400 PER PHASE SWITCHING FREQUENCY (kHz) OUTPUT RIPPLE COMP SW1 SW2 350 300 250 VARFREQ = 5.0 V 200 150 100 50 0 0.25 Input = 12 V, Output = 1.1 V No Load VARFREQ = 0 V RT = 187 kΩ 2−Phase Mode 0.5 0.75 1 1.25 1.5 VID OUTPUT VOLTAGE (V) Figure 11. Switching Waveforms in 2−Phase Figure 12. Switching Frequency vs. VID Output Voltage in PWM Mode http://onsemi.com 11 ADP3208D TYPICAL PERFORMANCE CHARACTERISTICS VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted. 350 1200 SWITCHING FREQUENCY (kHz) 300 1000 PMON VOLTAGE (mV) 250 200 150 100 600 400 200 50 0 800 RT = 237 kW RPM = 80.5 kW 0 0.5 0 1.5 1.0 0 20 40 OUTPUT VOLTAGE (V) 60 80 OUTPUT POWER (W) Figure 13. Switching Frequency vs. Output Voltage in RPM Mode Figure 14. IMON Voltage vs. Output Current 1.05 1000 1-Phase PSI = Low Switching Frequency (kHz) VID = 1.4125 V 1 2-Phase PSI = High Output (V) +2% VID = 1.2125 V 0.95 -2% VID = 1.1 V 0.9 VID = 0.8125 VID = 0.6125 2−Phase Configuration 100 10 0.85 100 1000 0 Rt RESISTANCE (kW ) 20 30 40 Load (A) Figure 15. Per Phase Switching Frequency vs. RT Resistance Figure 16. Load Line Accuracy OUTPUT VOLTAGE 0.8 VCC CURRENT (mA) 10 0.6 PWRGND 0.4 CLKEN 0.2 VDC = 12 V EN = LOW EN 0 0 1 2 3 4 5 6 VCC VOLTAGE (V) Figure 17. VCC Current vs. VCC Voltage with Enable Low Figure 18. Startup Waveforms http://onsemi.com 12 50 ADP3208D TYPICAL PERFORMANCE CHARACTERISTICS VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted. OUTPUT VOLTAGE 4 L1 CURRENT L2 CURRENT 2 R1 SWITCH NODE 1 1 SWITCH NODE 2 CH1 10.0V CH2 5.00A CH3 5.00A CH4 20.0mV REF1 10.0V 1.00ms M1.00ms A CH3 8.00A T 20.00% Figure 19. Dual−Phase, Interleaved PWM Waveform, 20 A Load SWITCH NODE 2 SWITCH NODE 1 SWITCH NODE 1 PSI SWITCH NODE 2 OUTPUT VOLTAGE OUTPUT VOLTAGE Figure 20. PSI Transition Figure 21. PSI Transition http://onsemi.com 13 ADP3208D TYPICAL PERFORMANCE CHARACTERISTICS VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted. OUTPUT VOLTAGE OUTPUT VOLTAGE DPRSLP SWITCH NODE 1 DPRSLP SWITCH NODE 1 SWITCH NODE 2 SWITCH NODE 2 PSI = HIGH LOAD = 2 A PSI = HIGH LOAD = 2 A Figure 22. DPRSLP Transition Figure 23. DPRSLP Transition OUTPUT VOLTAGE OUTPUT VOLTAGE DPRSLP DPRSLP SWITCH NODE 2 SWITCH NODE 2 SWITCH NODE 1 SWITCH NODE 1 PSI = LOW LOAD = 2 A PSI = LOW LOAD = 2 A Figure 24. DPRSLP Transition Figure 25. DPRSLP Transition http://onsemi.com 14 ADP3208D Theory of Operation than one output can be active at a time, permitting overlapping phases. The ADP3208D combines multi−mode Pulse Width Modulated (PWM) control and Ramp Pulse Modulated (RPM) control with multi−phase logic outputs for use in single− and dual−phase synchronous buck CPU core supply power converters. The internal 7−bit VID DAC conforms to the Intel IMVP−6+ specifications. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling high currents in a single−phase converter would put too high of a thermal stress on system components such as the inductors and MOSFETs. The multi−mode control of the ADP3208D is a stable, high performance architecture that includes • Current and thermal balance between phases • High speed response at the lowest possible switching frequency and minimal count of output decoupling capacitors • Minimized thermal switching losses due to lower frequency operation • High accuracy load line regulation • High current output by supporting 2−phase operation • Reduced output ripple due to multiphase ripple cancellation • High power conversion efficiency with heavy and light loads • Increased immunity from noise introduced by PC board layout constraints • Ease of use due to independent component selection • Flexibility in design by allowing optimization for either low cost or high performance Operation Modes The number of phases can be static (see the Number of Phases section) or dynamically controlled by system signals to optimize the power conversion efficiency with heavy and light loads. If SP is set low (user−selected dual−phase mode) during a VID transient or with a heavy load condition (indicated by DPRSLP being low and PSI being high), the ADP3208D runs in 2−phase, interleaved PWM mode to achieve minimal VCORE output voltage ripple and the best transient performance possible. If the load becomes light (indicated by PSI being low or DPRSLP being high), ADP3208D switches to single−phase mode to maximize the power conversion efficiency. In addition to changing the number of phases, the ADP3208D is also capable of dynamically changing the control method. In dual−phase operation, the ADP3208D runs in PWM mode, where the switching frequency is controlled by the master clock. In single−phase operation (commanded by the PSI low state), the ADP3208D runs in RPM mode, where the switching frequency is controlled by the ripple voltage appearing on the COMP pin. In RPM mode, the DRVH1 pin is driven high each time the COMP pin voltage rises to a voltage limit set by the VID voltage and an external resistor connected from the RPM to GND. If the device is in single−phase mode and the system signal DPRSLP is asserted high during the deeper sleep mode of CPU operation, the ADP3208D continues running in RPM mode but offers the option of turning off the low−side (synchronous rectifier) MOSFET when the inductor current drops to 0. Turning off the low−side MOSFETs at the zero current crossing prevents reversed inductor current build up and breaks synchronous operation of high− and low−side switches. Due to the asynchronous operation, the switching frequency becomes slower as the load current decreases, resulting in good power conversion efficiency with very light loads. Table 1 summarizes how the ADP3208D dynamically changes the number of active phases and transitions the operation mode based on system signals and operating conditions. Number of Phases The number of operational phases can be set by the user. Tying the SP pin to the VCC pin forces the chip into single−phase operation. Otherwise, dual−phase operation is automatically selected, and the chip switches between single− and dual−phase modes as the load changes to optimize power conversion efficiency. In dual−phase configuration, SP is low and the timing relationship between the two phases is determined by internal circuitry that monitors the PWM outputs. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more Table 1. Phase Number and Operation Modes PSI DPRSLP VID Transient (Note 1) Current Limit No. of Phases Selected by User No. of Phases in Operation Operation Mode (Note 2) * * Yes * N [2 or 1] N PWM, CCM only 1 0 No * N [2 or 1] N PWM, CCM only 0 0 No No * 1 RPM, CCM only 0 0 No Yes * 1 PWM, CCM only * 1 No No * 1 RPM, automatic CCM/DCM * 1 No Yes * 1 PWM, CCM only * = Don’t Care 1. VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient period is the same as that of PWRGD masking time. 2. CCM stands for continuous current mode, and DCM stands for discontinuous current mode. http://onsemi.com 15 ADP3208D VRMP 5V FLIP−FLOP IR = AR y IRAMP S Q BST1 GATE DRIVER BST DRVH RD CR FLIP−FLOP 400ns 1V IN SW DCM DRVL Q S Q Q VCC RI DRVH1 L SW1 LOAD DRVL1 5V RD R2 BST2 R1 VCC DRVH2 R1 R2 30mV RI L SW2 1V DRVL2 VDC +– + CSREF – VCS + COMP CA RA CFB + FBRTN FB LLINE CSCOMP CB CSSUM RCS RPH CCS RPH RB 6 2 -0 4 7 3 Figure 26. Single−Phase RPM Mode Operation http://onsemi.com 16 ADP3208D 5V BST1 GATE DRIVER IR = A R y I RAMP BST DRVH FLIP−FLOP CLOCK OSCILLATOR S Q IN SW DRVL RD CR DRVH1 RI L SW1 DRVL1 LOAD 5V AD BST2 VCC GATE DRIVER 0.2V IR = A R y I RAMP BST DRVH FLIP−FLOP CLOCK OSCILLATOR S SW Q DRVL RD CR VCC VCC DRVH2 RI L SW2 DRVL2 AD VDC +– 0.2V CSREF – + V CS RAMP + COMP CA RA CFB + FBRTN FB CSCOMP LLINE CB CSSUM R CS RPH C CS RPH RB 7 3 6 5 2 -0 4 Figure 27. Dual−Phase PWM Mode Operation Setting Switch Frequency capacitor (5 pF typical) and creates a ramp. When the internal ramp signal intercepts the COMP voltage, the DRVH1 pin is reset low. In continuous current mode, the switching frequency of RPM operation is almost constant. While in discontinuous current conduction mode, the switching frequency is reduced as a function of the load current. Master Clock Frequency in PWM Mode When the ADP3208D runs in PWM, an external resistor connected from the RT pin to GND sets the clock frequency. The frequency is constant at a given VID code but varies with the VID voltage: the lower the VID voltage, the lower the clock frequency. The variation of clock frequency with VID voltage maintains constant VCORE ripple and improves power conversion efficiency at lower VID voltages. Figure 15 shows the relationship between clock frequency and VID voltage, parametrized by RT resistance. To determine the switching frequency per phase, divide the clock by the number of phases in use. Differential Sensing of Output Voltage The ADP3208D combines differential sensing with a high accuracy VID DAC, referenced by a precision band gap source and a low offset error amplifier, to meet the rigorous accuracy requirement of the Intel IMVP−6+ specification. In steady−state mode, the combination of the VID DAC and error amplifier maintain the output voltage for a worst−case scenario within ±8 mV of the full operating output voltage and temperature range. The CPU core output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the positive regulation point; the VCC remote sensing pin of the microprocessor. FBRTN should be connected directly to the negative remote sensing point; the VSS sensing point of the CPU. The internal VID DAC and precision voltage reference are referenced to FBRTN and have a maximum current of 200 mA for guaranteed accurate remote sensing. Switching Frequency in RPM Mode — Single−Phase Operation In single−phase RPM mode, the switching frequency is controlled by the ripple voltage on the COMP pin, rather than by the master clock. Each time the COMP pin voltage exceeds the RPM pin voltage threshold level determined by the VID voltage and the external resistor connected from RPM to GND, an internal ramp signal is started and DRVH1 is driven high. The slew rate of the internal ramp is programmed by the current entering the RAMP pin. One−third of the RAMP current charges an internal ramp http://onsemi.com 17 ADP3208D Output Current Sensing used as the voltage positioning setpoint. The arrangement results in an enhanced feed−forward response. The ADP3208D includes a dedicated Current Sense Amplifier (CSA) to monitor the total output current of the converter for proper voltage positioning vs. load current and for over current detection. Sensing the current delivered to the load is an inherently more accurate method than detecting peak current or sampling the current across a sense element, such as the low−side MOSFET. The CSA can be configured several ways, depending on system optimization objectives, and the current information can be obtained by: • Output inductor ESR sensing without the use of a thermistor for the lowest cost • Output inductor ESR sensing with the use of a thermistor that tracks inductor temperature to improve accuracy • Discrete resistor sensing for the highest accuracy At the positive input of the CSA, the CSREF pin is connected to the output voltage. At the negative input (that is, the CSSUM pin of the CSA), signals from the sensing element (in the case of inductor DCR sensing, signals from the switch node side of the output inductors) are summed together by series summing resistors. The feedback resistor between the CSCOMP and CSSUM pins sets the gain of the CSA, and a filter capacitor is placed in parallel with this resistor. The current information is then given as the voltage difference between the CSCOMP and CSREF pins. This signal is used internally as a differential input for the current limit comparator. An additional resistor divider connected between the CSCOMP and CSREF pins with the midpoint connected to the LLINE pin can be used to set the load line required by the microprocessor specification. The current information to set the load line is then given as the voltage difference between the LLINE and CSREF pins. This configuration allows the load line slope to be set independent from the current limit threshold. If the current limit threshold and load line do not have to be set independently, the resistor divider between the CSCOMP and CSREF pins can be omitted and the CSCOMP pin can be connected directly to LLINE. To disable voltage positioning entirely (that is, to set no load line), LLINE should be tied to CSREF. To provide the best accuracy for current sensing, the CSA has a low offset input voltage and the sensing gain is set by an external resistor ratio. Current Control Mode and Thermal Balance The ADP3208D has individual inputs for monitoring the current of each phase. The phase current information is combined with an internal ramp to create a current−balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. The current balance information is independent from the total inductor current information used for voltage positioning described in the Active Impedance Control Mode section. The magnitude of the internal ramp can be set so that the transient response of the system is optimal. The ADP3208D monitors the supply voltage to achieve feed forward control whenever the supply voltage changes. A resistor connected from the power input voltage rail to the RAMP pin determines the slope of the internal PWM ramp. More detail about programming the ramp is provided in the Application Information section. The ADP3208D should not require external thermal balance circuitry if a good layout is used. However, if mismatch is desired due to uneven cooling in phase, external resistors can be added to individually control phase currents as long as the phase currents are mismatched by less than 30%. If unwanted mismatch exceeds 30%, a new layout that improves phase symmetry should be considered. RAMP ADP3208D 20 SWITCH NODE 1 VDC C R1 R2 R SW1 SWITCH NODE 2 R SW2 Reserved for Thermal Balance Tune Figure 28. Optional Current Balance Resistors In 2−phase operation, alternate cycles of the internal ramp control the duty cycle of the separate phases. Figure 28 shows the addition of two resistors from each switch node to the RAMP pin; this modifies the ramp−charging current individually for each phase. During Phase 1, SW Node 1 is high (practically at the input voltage potential) and SW Node 2 is low (practically at the ground potential). As a consequence, the RAMP pin, through the R2 resistor, sees the tap point of a divider connected to the input voltage, where RSW1 is the upper element and RSW2 is the lower element of the divider. During Phase 2, the voltages on SW Node 1 and SW Node 2 switch and the resistors swap functions. Tuning RSW1 and RSW2 allows the current to be optimally set for each phase. To increase the current for a given phase, decrease RSW for that phase. Active Impedance Control Mode To control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between LLINE and CSREF, can be scaled to be equal to the required droop voltage. This droop voltage is calculated by multiplying the droop impedance of the regulator by the output current. This value is used as the control voltage of the PWM regulator. The droop voltage is subtracted from the DAC reference output voltage, and the resulting voltage is Voltage Control Mode A high−gain bandwidth error amplifier is used for the voltage mode control loop. The noninverting input voltage http://onsemi.com 18 ADP3208D is set via the 7−bit VID DAC. The VID codes are listed in the VID Code table. The noninverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. The output of the error amplifier is the COMP pin, which sets the termination voltage of the internal PWM ramps. At the negative input, the FB pin is tied to the output sense location using RB, a resistor for sensing and controlling the output voltage at the remote sensing point. The main loop compensation is incorporated in the feedback network connected between the FB and COMP pins. VCC EN VCORE t BOOT CLKEN Power−Good Monitoring PWRGD The power−good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open−drain output that can be pulled up through an external resistor to a voltage rail, not necessarily the same VCC voltage rail that is running the controller. A logic high level indicates that the output voltage is within the voltage limits defined by a range around the VID voltage setting. PWRGD goes low when the output voltage is outside of this range. Following the IMVP−6+ specification, the PWRGD range is defined to be 300 mV less than and 200 mV greater than the actual VID DAC output voltage. For any DAC voltage less than 300 mV, only the upper limit of the PWRGD range is monitored. To prevent a false alarm, the power−good circuit is masked during various system transitions, including a VID change and entrance into or exit out of deeper sleep. The duration of the PWRGD mask is set to approximately 130 ms by an internal timer. If the voltage drop is greater than 200 mV during deeper sleep entry or slow deeper sleep exit, the duration of PWRGD masking is extended by the internal logic circuit. t CPU _PWRGD Figure 29. Powerup Sequence of ADP3208D If EN is taken low or VCC drops below the VCC UVLO threshold, both the SS capacitor and the PGDELAY capacitor are reset to ground to prepare the chip for a subsequent soft−start cycle. Soft Transient When a VID input changes, the ADP3208D detects the change but ignores new code for a minimum of 400 ns. This delay is required to prevent the device from reacting to digital signal skew while the 7−bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and retriggers the internal PWRGD masking timer. The ADP3208D provides a soft transient function to reduce inrush current during VID transitions. Reducing the inrush current helps decrease the acoustic noise generated by the MLCC input capacitors and inductors. The soft transient feature is implemented internally. When a new VID code is detected, the ADP3208D steps sequentially through each VID voltage to the final VID voltage. There is a PWRGD masking time of 100ms after the last VID code is changed internally. Table 2 lists the soft transient slew rate. Powerup Sequence and Soft−Start The power−on ramp−up time of the output voltage is set internally. The powerup sequence, including the soft−start is illustrated in Figure 29. After EN is asserted high, the soft−start sequence starts. The core voltage ramps up linearly to the boot voltage. The ADP3208D regulates at the boot voltage for 100 ms. After the boot time is completed, CLKEN is asserted low. After CLKEN is asserted low for 9ms, PWRGD is asserted high. In VCC UVLO or in shutdown, a small MOSFET turns on connecting the CSREF to GND. The MOSFET on the CSREF pin has a resistance of approximately 100W. When VCC ramps above the upper UVLO threshold and EN is asserted high, the ADP3208D enables internal bias and starts a reset cycle that lasts about 50 ms to 60 ms. Next, when initial reset is over, the chip detects the number of phases set by the user, and gives a go signal to start soft−start. The ADP3208D reads the VID codes provided by the CPU on VID0 to VID6 input pins after CLKEN is asserted low. The PWRGD signal is asserted after a tCPU_PWRGD delay of about 9 ms, as specified by IMVP−6+. The power−good delay is programmed internally. Table 2. Soft Transient Slew Rate DPRSLP Slew Rate Entrance to Deeper Sleep VID Transient HIGH −3.125mV/ms Fast Exit from Deeper Sleep LOW +12.5mV/ms Slow Exit from Deeper Sleep HIGH +3.125mV/ms Transient from VBOOT to VID DNC1 ±3.125mV/ms 1. DNC = Do Not Care. Current Limit The ADP3208D compares the differential output of a current sense amplifier to a programmable current limit setpoint to provide current limiting function. The current limit set point is set with a resistor connected from ILIM pin to CSCOMP pin. This is the Rlim resistor. During normal http://onsemi.com 19 ADP3208D Changing VID OTF operation, the voltage on the ILIM pin is equal to the CSREF pin. The voltage across RLIM is equal to the voltage across the CSA (from CSREF pin to CSCOMP pin). This voltage is proportional to output current. The current through RLIM is proportional to the output inductor current. The current through RLIM is compared with an internal reference current. When the RLIM current goes above the internal reference current, the ADP3208D goes into current limit. The current limit circuit is shown in Figure 30. The ADP3208D is designed to track dynamically changing VID code. As a consequence, the CPU VCC voltage can change without the need to reset the controller or the CPU. This concept is commonly referred to as VID OTF transient. A VID OTF can occur with either light or heavy load conditions. The processor alerts the controller that a VID change is occurring by changing the VID inputs in LSB incremental steps from the start code to the finish code. The change can be either upwards or downwards steps. When a VID input changes, the ADP3208D detects the change but ignores new code for a minimum of 400 ns. This delay is required to prevent the device from reacting to digital signal skew while the 7−bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and retriggers the internal PWRGD masking timer. As listed in Table 3, during a VID transient, the ADP3208D forces PWM mode regardless of the state of the system input signals. For example, this means that if the chip is configured as a dual−phase controller but is running in single−phase mode due to a light load condition, a current overload event causes the chip to switch to dual−phase mode to share the excessive load until the delayed current limit latchoff cycle terminates. In user−set single−phase mode, the ADP3208D usually runs in RPM mode. When a VID transition occurs, however, the ADP3208D switches to dual−phase PWM mode. 20 μA CLA VI CONV I LIM I LIM + - + R R CSREF CSA + CSCOMP ILIM CSSUM L R LIM R CS DCR C BULK R PH C CS Figure 30. Current Limit Circuit During startup when the output voltage is below 200 mV, a secondary current limit is activated. This is necessary because the voltage swing on CSCOMP cannot extend below ground. The secondary current limit circuit clamps the internal COMP voltage and sets the internal compensation ramp termination voltage at 1.5 V level. The clamp actually limits voltage drop across the low side MOSFETs through the current balance circuitry. An inherent per phase current limit protects individual phases in case one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. After 9 ms in current limit, the ADP3208D will latchoff. The latchoff can be reset by removing and reapplying VCC, or by recycling the EN pin low and high for a short time. The latchoff can be reset by removing and reapplying VCC, or by recycling the EN pin low and high for a short time. Light Load RPM DCM Operation In single−phase normal mode, DPRSLP is pulled low and the APD3208 operates in Continuous Conduction Mode (CCM) over the entire load range. The upper and lower MOSFETs run synchronously and in complementary phase. See Figure 32 for the typical waveforms of the ADP3208D running in CCM with a 7 A load current. OUTPUT VOLTAGE 20 mV/DIV 4 INDUCTOR CURRENT 5 A/DIV PWRGD 2.0 V/DIV 2 SWITCH NODE 5.0 V/DIV LOW−SIDE GATE 5.0 V/DIV 3 1 OUTPUT 0.5 V/DIV 400 ns/DIV Figure 32. Single−Phase Waveforms in CCM 2 ms/DIV CURRENT LIMIT APPLIED LATCHED OFF Figure 31. Current Overload http://onsemi.com 20 ADP3208D If DPRSLP is pulled high, the ADP3208D operates in RPM mode. If the load condition is light, the chip enters Discontinuous Conduction Mode (DCM). Figure 33 shows a typical single−phase buck with one upper FET, one lower FET, an output inductor, an output capacitor, and a load resistor. Figure 34 shows the path of the inductor current with the upper FET on and the lower FET off. In Figure 35 the high−side FET is off and the low−side FET is on. In CCM, if one FET is on, its complementary FET must be off; however, in DCM, both high− and low−side FETs are off and no current flows into the inductor (see Figure 36). Figure 37 shows the inductor current and switch node voltage in DCM. In DCM with a light load, the ADP3208D monitors the switch node voltage to determine when to turn off the low−side FET. Figure 38 shows a typical waveform in DCM with a 1 A load current. Between t1 and t2, the inductor current ramps down. The current flows through the source drain of the low−side FET and creates a voltage drop across the FET with a slightly negative switch node. As the inductor current ramps down to 0 A, the switch voltage approaches 0 V, as seen just before t2. When the switch voltage is approximately −6 mV, the low−side FET is turned off. Figure 37 shows a small, dampened ringing at t2. This is caused by the LC created from capacitance on the switch node, including the CDS of the FETs and the output inductor. This ringing is normal. The ADP3208D automatically goes into DCM with a light load. Figure 38 shows the typical DCM waveform of the ADP3208D. As the load increases, the ADP3208D enters into CCM. In DCM, frequency decreases with load current. Figure 39 shows switching frequency vs. load current for a typical design. In DCM, switching frequency is a function of the inductor, load current, input voltage, and output voltage. OFF L C ON LOAD Figure 35. Buck Topology Inductor Current During t1 and t2 OFF L OFF C LOAD Figure 36. Buck Topology Inductor Current During t2 and t3 INDUCTOR CURRENT SWITCH NODE VOLTAGE Q1 INPUT VOLTAGE DRVH t0 OUTPUT VOLTAGE SWITCH L NODE C t2 t3 t4 Figure 37. Inductor Current and Switch Node in DCM Q2 DRVL t1 LOAD 4 OUTPUT VOLTAGE 20 mV/DIV Figure 33. Buck Topology SWITCH NODE 5.0 V/DIV 2 ON L 3 OFF C LOAD INDUCTOR CURRENT 5 A/DIV 1 LOW−SIDE GATE DRIVE 5.0 V/DIV 2 ms/DIV Figure 34. Buck Topology Inductor Current During t0 and t1 Figure 38. Single−Phase Waveforms in DCM with 1 A Load Current http://onsemi.com 21 ADP3208D prevent damage to the CPU caused from negative voltage, the ADP3208D maintains its RVP monitoring function even after OVP latchoff. During OVP latchoff, if the CSREF pin voltage drops to less than −300 mV, the low−side MOSFETs is turned off. DRVL outputs are allowed to turn back on when the CSREF voltage recovers to greater than −100 mV. Figure 40 shows a typical OVP test. FB pin is shorted to ground causing the control to command a large duty cycle. The output voltage climbs up. When the output voltage is climbs 200 mV above the DAC voltage, the PWRGD signal de−asserts. When the output voltage climbs to 1.7V, OVP is enabled. In OVP, the phase 1 and phase 2 low side drive turns on the low side power MOSFETs. The low side MOSFETs pull the output voltage low through the power inductor. When the output voltage falls below −300 mV, Reverse Voltage Protection is enabled. In Reverse Voltage Protection, all power MOSFETs are turned off. This protects the CPU from seeing a large negative voltage. 400 350 FREQUENCY (kHz) 300 9.0 V INPUT 250 19 V INPUT 200 150 100 50 0 0 2 4 6 8 10 12 14 LOAD CURRENT (A) Figure 39. Single−Phase CCM/DCM Frequency vs. Load Current Output Crowbar To prevent the CPU and other external components from damage due to overvoltage, the ADP3208D turns off the DRVH1 and DRVH2 outputs and turns on the DRVL1 and DRVL2 outputs when the output voltage exceeds the OVP threshold (1.7 V typical). Turning on the low−side MOSFETs forces the output capacitor to discharge and the current to reverse due to current build up in the inductors. If the output overvoltage is due to a drain−source short of the high−side MOSFET, turning on the low−side MOSFET results in a crowbar across the input voltage rail. The crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the microprocessor from destruction. When the OVP feature is triggered, the ADP3208D is latched off. The latchoff function can be reset by removing and reapplying VCC to the ADP3208D or by briefly pulling the EN pin low. Pulling TTSNS to less than 1.0 V disables the overvoltage protection function. In this configuration, VRTT should be tied to ground. OUTPUT VOLTAGE PWRGD PHASE 2 LOW SIDE GATE PHASE 1 LOW SIDE GATE Figure 40. Overvoltage Protection and Reverse Voltage Protection Output Enable and UVLO For the ADP3208D to begin switching the VCC supply voltage to the controller must be greater than the VCCO threshold and the EN pin must be driven high. If the VCC voltage is less than the VCCUVLO threshold or the EN pin is a logic low, the ADP3208D shuts off. In shutdown mode, the controller holds the PWM outputs low, shorts the capacitors of the SS and PGDELAY pins to ground, and drives the DRVH and DRVL outputs low. The user must adhere to proper power supply sequencing during startup and shutdown of the ADP3208D. All input pins must be at ground prior to removing or applying VCC, and all output pins should be left in high impedance state while VCC is off. Reverse Voltage Protection Very large reverse current in inductors can cause negative VCORE voltage, which is harmful to the CPU and other output components. The ADP3208D provides a reverse voltage protection (RVP) function without additional system cost. The VCORE voltage is monitored through the CSREF pin. When the CSREF pin voltage drops to less than −300 mV, the ADP3208D triggers the RVP function by disabling all PWM outputs and driving DRVL1 and DRVL2 low, thus turning off all MOSFETs. The reverse inductor currents can be quickly reset to 0 by discharging the built−up energy in the inductor into the input dc voltage source via the forward−biased body diode of the high−side MOSFETs. The RVP function is terminated when the CSREF pin voltage returns to greater than −100 mV. Sometimes the crowbar feature inadvertently causes output reverse voltage because turning on the low−side MOSFETs results in a very large reverse inductor current. To Thermal Throttling Control The ADP3208D includes a thermal monitoring circuit to detect whether the temperature of the VR has exceeded a user−defined thermal throttling threshold. The thermal monitoring circuit requires an external resistor divider connected between the VCC pin and GND. The divider consists of an NTC thermistor and a resistor. To generate a http://onsemi.com 22 ADP3208D 100 mV to prevent high frequency oscillation of VRTT when the temperature approaches the set alarm point. voltage that is proportional to temperature, the midpoint of the divider is connected to the TTSNS pin. An internal comparator circuit compares the TTSNS voltage to half the VCC threshold and outputs a logic level signal at the VRTT output when the temperature trips the user−set alarm threshold. The VRTT output is designed to drive an external transistor that in turn provides the high current, open−drain VRTT signal required by the IMVP−6+ specification. The internal VRTT comparator has a hysteresis of approximately Current Monitor Function The ADP3208D has an output current monitor. The IMON pin sources a current proportional to the inductor current. A resistor from IMON pin to FBRTN sets the gain. A 0.1 mF is added in parallel with RMON to filter the inductor ripple. The IMON pin is clamped to prevent it from going above 1.15V Table 3. VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V) 0 0 0 0 0 0 0 1.5000 0 0 0 0 0 0 1 1.4875 0 0 0 0 0 1 0 1.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 0 0 0 0 1 0 1 1.4375 0 0 0 0 1 1 0 1.4250 0 0 0 0 1 1 1 1.4125 0 0 0 1 0 0 0 1.4000 0 0 0 1 0 0 1 1.3875 0 0 0 1 0 1 0 1.3750 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.3500 0 0 0 1 1 0 1 1.3375 0 0 0 1 1 1 0 1.3250 0 0 0 1 1 1 1 1.3125 0 0 1 0 0 0 0 1.3000 0 0 1 0 0 0 1 1.2875 0 0 1 0 0 1 0 1.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 0 0 1 0 1 0 1 1.2375 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.0500 0 1 0 0 1 0 1 1.0375 http://onsemi.com 23 ADP3208D Table 3. VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V) 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 http://onsemi.com 24 ADP3208D Table 3. VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V) 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.4250 1 0 1 0 1 1 1 0.4125 1 0 1 1 0 0 0 0.4000 1 0 1 1 0 0 1 0.3875 1 0 1 1 0 1 0 0.3750 1 0 1 1 0 1 1 0.3625 1 0 1 1 1 0 0 0.3500 1 0 1 1 1 0 1 0.3375 1 0 1 1 1 1 0 0.3250 1 0 1 1 1 1 1 0.3125 1 1 0 0 0 0 0 0.3000 1 1 0 0 0 0 1 0.2875 1 1 0 0 0 1 0 0.2750 1 1 0 0 0 1 1 0.2625 1 1 0 0 1 0 0 0.2500 1 1 0 0 1 0 1 0.2375 1 1 0 0 1 1 0 0.2250 1 1 0 0 1 1 1 0.2125 1 1 0 1 0 0 0 0.2000 1 1 0 1 0 0 1 0.1875 1 1 0 1 0 1 0 0.1750 1 1 0 1 0 1 1 0.1625 1 1 0 1 1 0 0 0.1500 1 1 0 1 1 0 1 0.1375 1 1 0 1 1 1 0 0.1250 1 1 0 1 1 1 1 0.1125 1 1 1 0 0 0 0 0.1000 1 1 1 0 0 0 1 0.0875 1 1 1 0 0 1 0 0.0750 1 1 1 0 0 1 1 0.0625 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.0000 http://onsemi.com 25 Figure 41. Typical 2−Phase Application Circuit ADP3208D http://onsemi.com 26 ADP3208D Application Information frequency is reduced with the load current in a linear manner. When considering power conversion efficiency in light load, lower switching frequency is usually preferred for RPM mode. However, the VCORE ripple specification in the IMVP−6 sets the limitation for lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM mode can be equal, larger, or smaller than its counterpart in PWM mode. A resistor from RPM to GND sets the pseudo constant frequency as following: The design parameters for a typical IMVP−6+ compliant CPU core VR application are as follows: • Maximum input voltage (VINMAX) = 19 V • Minimum input voltage (VINMIN) = 8.0 V • Output voltage by VID setting (VVID) = 1.4375 V • Maximum output current (IO) = 40 A • Droop resistance (RO) = 2.1 mW • Nominal output voltage at 40 A load (VOFL) = 1.3535 V • Static output voltage drop from no load to full load (DV) = VONL − VOFL = 1.4375 V − 1.3535 V = 84 mV • Maximum output current step (DIO) = 27.9 A • Number of phases (n) = 2 • Switching frequency per phase (fSW) = 300 kHz • Duty cycle at maximum input voltage (DMAX) = 0.18 V • Duty cycle at minimum input voltage (DMIN) = 0.076 V P S(MF) + 2 In PWM operation, the ADP3208D uses a fixed−frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. For a dual−phase design, a clock frequency of 600 kHz sets the switching frequency to 300 kHz per phase. This selection represents the trade−off between the switching losses and the minimum sizes of the output filter components. To achieve a 600 kHz oscillator frequency at a VID voltage of 1.2 V, RT must be 187 kW. Alternatively, the value for RT can be calculated by using the following equation: V VID ) 1.0 V 2 n f SW 9 pF * 16 kW P S(MF) + 2 RT + n f SW 9 pF * 16 kW RG n MF n C ISS (eq. 3) IO V CC f SW n MF RG n MF n C ISS (eq. 4) Inductor Selection The choice of inductance determines the ripple current of the inductor. Less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs. However, this allows the use of smaller−size inductors, and for a specified peak−to−peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger−size inductors and more output capacitance for the same peak−to−peak transient deviation. For a multiphase converter, the practical value for peak−to−peak inductor ripple current is less than 50% of the maximum dc current of that inductor. Equation 5 shows the relationship between the inductance, oscillator frequency, and peak−to−peak ripple current. Equation 6 can be used to determine the minimum inductance based on a given output ripple voltage. (eq. 1) where: 9 pF and 16 kW are internal IC component values. VVID is the VID voltage in volts. n is the number of phases. fSW is the switching frequency in hertz for each phase. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. When VARFREQ pin is connected to ground, the switching frequency does not change with VID. The value for RT can be calculated by using the following equation. 1.0 V n MF where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude. Because RR = 280 kW, the following resistance sets up 300 kHz switching frequency in RPM operation. Setting the Clock Frequency for PWM RT + IO V CC f SW IR + Lw ǒ1 * DMINǓ V VID L f SW V VID (eq. 5) RO (1 * (n f SW V RIPPLE D MIN)) (eq. 6) Solving Equation 6 for a 16 mV peak−to−peak output ripple voltage yields (eq. 2) Lw For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. 1.4375 V 2.1 mW 300 kHz (1 * (2 16 mV 0.076) + 533 nH (eq. 7) If the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. Choosing a 490 nH inductor is a good choice for a starting point, and it provides Setting the Switching Frequency for RPM Operation of Phase 1 During the RPM mode operation of Phase 1, the ADP3208D runs in pseudo constant frequency, given that the load current is high enough for continuous current mode. While in discontinuous current mode, the switching http://onsemi.com 27 ADP3208D a calculated ripple current of 9.0 A. The inductor should not saturate at the peak current of 24.5 A, and it should be able to handle the sum of the power dissipation caused by the winding’s average current (20 A) plus the ac core loss. In this example, 330 nH is used. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. Too large of a DCR causes excessive power losses, whereas too small of a value leads to increased measurement error. For this example, an inductor with a DCR of 0.8 mW is used. capacitor. In this example, a 220 kW is used for RCS to achieve optimal results. Next, solve for RPH(x) by rearranging Equation 8 as follows: R PH(X) w 0.8 mW 2.1 mW @ 220 kW + 83.8 kW (eq. 11) The standard 1% resistor for RPH(x) is 86.6 kW. Inductor DCR Temperature Correction If the DCR of the inductor is used as a sense element and copper wire is the source of the DCR, the temperature changes associated with the inductor’s winding must be compensated for. Fortunately, copper has a well−known temperature coefficient (TC) of 0.39%/°C. If RCS is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductor’s DCR. Due to the nonlinear nature of NTC thermistors, series resistors RCS1 and RCS2 (see Figure 42) are needed to linearize the NTC and produce the desired temperature coefficient tracking. Selecting a Standard Inductor After the inductance and DCR are known, select a standard inductor that best meets the overall design goals. It is also important to specify the inductance and DCR tolerance to maintain the accuracy of the system. Using 20% tolerance for the inductance and 15% for the DCR at room temperature are reasonable values that most manufacturers can meet. Power Inductor Manufacturers The following companies provide surface−mount power inductors optimized for high power applications upon request: • Vishay Dale Electronics, Inc. • Panasonic • Sumida Corporation • NEC Tokin Corporation Place as close as possible to nearest inductor R TH ADP3208D CSCOMP R PH1 + RPH2 To VOUT Sense R PH3 R CS1 R CS2 17 CCS1 CSSUM - To Switch Nodes 19 CSREF CCS2 Keep This Path As Short As Possible And Well Away From Switch Node Lines 18 Output Droop Resistance The design requires that the regulator output voltage measured at the CPU pins decreases when the output current increases. The specified voltage drop corresponds to the droop resistance (RO). The output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low−pass filter. The summing is implemented by the CS amplifier that is configured with resistor RPH(x) (summer) and resistors RCS and CCS (filters). The output resistance of the regulator is set by the following equations: RO + R CS R SENSE R PH(x) C CS + Figure 42. Temperature−Compensation Circuit Values The following procedure and expressions yield values for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS value. 1. Select an NTC to be used based on its type and value. Because the value needed is not yet determined, start with a thermistor with a value close to RCS and an NTC with an initial tolerance of better than 5%. 2. Find the relative resistance value of the NTC at two temperatures. The appropriate temperatures will depend on the type of NTC, but 50°C and 90°C have been shown to work well for most types of NTCs. The resistance values are called A (A is RTH(50°C)/RTH(25°C)) and B (B is RTH(90°C)/RTH(25°C)). Note that the relative value of the NTC is always 1 at 25°C. 3. Find the relative value of RCS required for each of the two temperatures. The relative value of RCS is based on the percentage of change needed, which is initially assumed to be 0.39%/°C in this example. The relative values are called r1 (r1 is 1/(1+ TC × (T1 − 25))) and r2 (r2 is 1/(1 + TC × (T2 − 25))), where TC is 0.0039, T1 is 50°C, and T2 is 90°C. (eq. 8) L R SENSE R CS (eq. 9) where RSENSE is the DCR of the output inductors. Either RCS or RPH(x) can be chosen for added flexibility. Due to the current drive ability of the CSCOMP pin, the RCS resistance should be greater than 100 kW. For example, initially select RCS to be equal to 200 kW, and then use Equation 9 to solve for CCS: C CS + 330 nH 0.8 mW 200 kW + 2.1 nF (eq. 10) If CCS is not a standard capacitance, RCS can be tuned. For example, if the optimal CCS capacitance is 1.5 nF, adjust RCS to 280 kW. For best accuracy, CCS should be a 5% NPO http://onsemi.com 28 ADP3208D allows a maximum VCORE overshoot (VOSMAX) of 10 mV more than the VID voltage for a step−off load current. 4. Compute the relative values for rCS1, rCS2, and rTH by using the following equations: ȡ ȧ Ȣn ǒR r CS2 + (A * B) A r CS1 + r1 (1 * B) (1 * B) r1 * B r2 ) B (1 * A) (1 * A) r1 1 1*r *r r 2 * (A * B) 1 *r 1 C X(MAX) v CS2 1 1 1*r CS2 *r 5. Calculate RTH = rTH × RCS, and then select a thermistor of the closest value available. In addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k+ k R CS2 + R CS ((1 * k) ) (k O V VID (eq. 15) V VID RO 2 ǒ 1 ) tv where: k + −1n V VID n Ǔ ȣȧ k Vv RO L 2 * 1 * Cz Ȥ ǒ Ǔ V ERR VV (eq. 17) To meet the conditions of these expressions and the transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is greater than CX(MAX), the system does not meet the VID OTF and/or the deeper sleep exit specifications and may require less inductance or more phases. In addition, the switching frequency may have to be increased to maintain the output ripple. For example, if 30 pieces of 10 mF, 0805−size MLC capacitors (CZ = 300 mF) are used, the fastest VID voltage change is when the device exits deeper sleep, during which the VCORE change is 220 mV in 22 ms with a setting error of 10 mV. If k = 3.1, solving for the bulk capacitance yields: (eq. 13) r CS1 r CS2)) DI (eq. 16) 6. Calculate values for RCS1 and RCS2 by using the following equations: R CS1 + R CS Ǔ OSMAX ȣ ȧ Ȥ * Cz Vv k2 n R TH(ACTUAL) R TH(CALCULATED) V O) Ǹ (eq. 12) DI O L ȡ ȧ Ȣ 1 CS1 L C x(MIN) w (1 * A) CS2 r TH + r2 * A (eq. 14) For example, if a thermistor value of 100 kW is selected in Step 1, an available 0603−size thermistor with a value close to RCS is the Vishay NTHS0603N04 NTC thermistor, which has resistance values of A = 0.3359 and B = 0.0771. Using the equations in Step 4, rCS1 is 0.359, rCS2 is 0.729, and rTH is 1.094. Solving for rTH yields 241 kW, so a thermistor of 220 kW would be a reasonable selection, making k equal to 0.913. Finally, RCS1 and RCS2 are found to be 72.1 kW and 166 kW. Choosing the closest 1% resistor for RCS2 yields 165 kW. To correct for this approximation, 73.3 kW is used for RCS1. ȡ ȣ 330 nH @ 27.9 A * 300 mFȧ ȧ ǒ Ȣ2 2.1 mW ) Ǔ 1.4375 V Ȥ C X(MIN) w 10 mV 27.9 A + 1.0 mF COUT Selection The required output decoupling for processors and platforms is typically recommended by Intel. For systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement. Select the number of ceramics and determine the total ceramic capacitance (CZ). This is based on the number and type of capacitors used. Keep in mind that the best location to place ceramic capacitors is inside the socket; however, the physical limit is twenty 0805−size pieces inside the socket. Additional ceramic capacitors can be placed along the outer edge of the socket. A combined ceramic capacitor value of 200 mF to 300 mF is recommended and is usually composed of multiple 10 mF or 22 mF capacitors. Ensure that the total amount of bulk capacitance (CX) is within its limits. The upper limit is dependent on the VID OTF output voltage stepping (voltage step, VV, in time, tV, with error of VERR); the lower limit is based on meeting the critical capacitance for load release at a given maximum load step, DIO. The current version of the IMVP−6+ specification C X(MAX) v 330 nH 3.1 2 2 ȡǸ1 ) ǒ22 ms ȧ Ȣ 220 mV (2.1 mW) 2 1.4375 V 220 mV 1.4375 V 2 3.1 490 nH Ǔ ȣȧ 2.1 mW 2 *1 Ȥ * 300 mF + 21 mF Using six 330 mF Panasonic SP capacitors with a typical ESR of 7 mW each yields CX = 1.98 mF and RX = 1.2 mW. Ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using: LX v CZ RO 2 L X v 300 mF Q2 (2.1 mW) 2 2 + 2 nH (eq. 18) where: Q is limited to the square root of 2 to ensure a critically damped system. http://onsemi.com 29 ADP3208D The high−side (main) MOSFET must be able to handle two main power dissipation components: conduction losses and switching losses. Switching loss is related to the time for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall times of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET: LX is about 150 pH for the six SP capacitors, which is low enough to avoid ringing during a load change. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. For this multi−mode control technique, an all ceramic capacitor design can be used if the conditions of Equations 16, 17, and 18 are satisfied. Power MOSFETs For typical 20 A per phase applications, the N−channel power MOSFETs are selected for two high−side switches and two or three low−side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). Because the voltage of the gate driver is 5.0 V, logic−level threshold MOSFETs must be used. The maximum output current, IO, determines the RDS(ON) requirement for the low−side (synchronous) MOSFETs. In the ADP3208D, currents are balanced between phases; the current in each low−side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO): P SF + (1 * D) ƪǒ IO Ǔ ǒ 2 n ) 1 12 n SF Ǔƫ IR n SF R RPM + L R RPM + RR (1 * D ) CR V VID f SW * 0.5 kW 2 280 kW 1.150 V ) 1.0 V 0.5 (1 * 0.061) 462 kW 5 pF 1.150 300 kHz * 500 kW + 202 kW (eq. 22) where RDS(MF) is the on resistance of the MOSFET. Typically, a user wants the highest speed (low CISS) device for a main MOSFET, but such a device usually has higher on resistance. Therefore, the user must select a device that meets the total power dissipation (about 0.8 W to 1.0 W for an 8−lead SOIC) when combining the switching and conduction losses. For example, an IRF7821 device can be selected as the main MOSFET (four in total; that is, nMF = 4), with approximately CISS = 1010 pF (max) and RDS(MF) = 18 mW (max at TJ = 120°C), and an IR7832 device can be selected as the synchronous MOSFET (four in total; that is, nSF = 4), with RDS(SF) = 6.7 mW (max at TJ = 120°C). Solving for the power dissipation per MOSFET at IO = 40 A and IR = 9.0 A yields 630 mW for each synchronous MOSFET and 590 mW for each main MOSFET. A third synchronous MOSFET is an option to further increase the conversion efficiency and reduce thermal stress. Finally, consider the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation: 2 R DS(SF) V OUT f SW 1.0 V AR (eq. 21) (eq. 19) (1 * D ) V VID RT where: nMF is the total number of main MOSFETs. RG is the total gate resistance. CISS is the input capacitance of the main MOSFET. The most effective way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following equation: where: D is the duty cycle and is approximately the output voltage divided by the input voltage. IR is the inductor peak−to−peak ripple current and is approximately: IR + 2 (eq. 20) Knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required RDS(ON) for the MOSFET. For 8−lead SOIC or 8−lead SOIC−compatible MOSFETs, the junction−to−ambient (PCB) thermal impedance is 50°C/W. In the worst case, the PCB temperature is 70°C to 80°C during heavy load operation of the notebook, and a safe limit for PSF is about 0.8 W to 1.0 W at 120°C junction temperature. Therefore, for this example (40 A maximum), the RDS(SF) per MOSFET is less than 8.5 mW for two pieces of low−side MOSFETs. This RDS(SF) is also at a junction temperature of about 120°C; therefore, the RDS(SF) per MOSFET should be less than 6 mW at room temperature, or 8.5 mW at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. P DRV + ƪ f SW 2 n ǒnMF Q GMF ) n SF ƫ Q QSFǓ ) I CC V CC (eq. 23) where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET. http://onsemi.com 30 ADP3208D the ADP3208D is set with RCLIM. RCLIM can be found using the following equation: The previous equation also shows the standby dissipation (ICC times the VCC) of the driver. Ramp Resistor Selection R LIM + The ramp resistor (RR) is used to set the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Use the following expression to determine a starting value: RR + RR + AR 3 0.5 3 CR 360 nH 5 5.2 mW 5 pF (eq. 24) + 462 kW where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low−side MOSFET ON−resistance; CR is the internal ramp capacitor value. Another consideration in the selection of RR is the size of the internal ramp voltage (see Equation 25). For stability and noise immunity, keep the ramp size larger than 0.5 V. Taking this into consideration, the value of RR in this example is selected as 280 kW. The internal ramp voltage magnitude can be calculated as follows: VR + VR + AR (1 * D) RR 0.5 CR 1.150 V 5 pF 280 kHz R MON + + 0.83 V 1* n 2 (1*n f C SW D) X R Ǔ O RO I FS (eq. 28) Optimized compensation of the ADP3208D allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and that is equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling. With the multi−mode feedback structure of the ADP3208D, it is necessary to set the feedback compensation so that the converter’s output impedance works in parallel with the output decoupling. In addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). In addition to the internal ramp, there is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: ǒ 10 R LIM Feedback Loop Compensation Design COMP Pin Ramp VR 1.15 V where: RMON is the current monitor resistor. RMON is connected from IMON pin to FBRTN. RLIM is the current limit resistor. RO is the output load line resistance. IFS is the output current when the voltage on IMON is at full scale. The size of the internal ramp can be increased or decreased. If it is increased, stability and transient response improves but thermal balance degrades. Conversely, if the ramp size is decreased, thermal balance improves but stability and transient response degrade. In the denominator of Equation 24, the factor of 3 sets the minimum ramp size that produces an optimal combination of good stability, transient response, and thermal balance. V RT + (eq. 27) The ADP3208D has output current monitor. The IMON pin sources a current proportional to the total inductor current. A resistor, RMON, from IMON to FBRTN sets the gain of the output current monitor. A 0.1 mF is placed in parallel with RMON to filter the inductor current ripple and high frequency load transients. Since the IMON pin is connected directly to the CPU, it is clamped to prevent it from going above 1.15V. The IMON pin current is equal to the RLIM times a fixed gain of 10. RMON can be found using the following equation: (eq. 25) (1 * 0.061) 462 kW 60 mA Output Current Monitor V VID f SW RO where: RLIM is the current limit resistor. RO is the output load line. ILIM is the current limit set point. When the ADP3208D is configured for 2−phase operation, the equation above is used to set the current limit. When the ADP3208D switches from 2−phase to 1−phase operation by PSI or DPRSLP signal, the current is single−phase is one half of the current limit in 2−phase. When the ADP3208D is configured for 1−phase operation, the equation above is used to set the current limit. L R DS AD I LIM (eq. 26) where CX is the total bulk capacitance, and RO is the droop resistance of the regulator. For this example, the overall ramp signal is 1.85 V. Current Limit Setpoint To select the current limit setpoint, the resistor value for RCLIM must be determined. The current limit threshold for http://onsemi.com 31 ADP3208D A Type III compensator on the voltage feedback is adequate for proper compensation of the output filter. Figure 43 shows the Type III amplifier used in the ADP3208D. Figure 44 shows the locations of the two poles and two zeros created by this amplifier. VOLTAGE ERROR AMPLIFIER TA + CX T B + (R X ) RȀ * R O) V RT REFERENCE VOLTAGE TC + ADP3208D COMP TD + FB RA CA ǒ L* R FB Figure 43. Voltage Error Amplifier GAIN –20dB/DEC RA + 0dB f Z1 FREQUENCY f P2 CB + Figure 44. Poles and Zeros of Voltage Error Amplifier The following equations give the locations of the poles and zeros shown in Figure 44: 2p CA f Z2 + 2p C FB f P1 + f P2 + RA R FB (eq. 31) CB ) CA (eq. 32) I CRMS + D The expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for ADP3208D section): RE + n RO ) AD ) 2 R DS ) L (1 * (n n CX RO Ǔ DS SW (eq. 36) RO 2 RO (eq. 37) n TA RO RE RB (eq. 38) TC CA (eq. 39) TB RB (eq. 40) TD RA (eq. 41) In continuous inductor−current mode, the source current of the high−side MOSFET is approximately a square wave with a duty ratio equal to n × VOUT/VIN and amplitude that is one−nth of the maximum output current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum RMS current. The maximum RMS capacitor current occurs at the lowest input voltage and is given by: (eq. 30) CA ) CB RA (eq. 35) CIN Selection and Input Current DI/DT Reduction R FB 1 2p (eq. 34) The standard values for these components are subject to the tuning procedure described in the Tuning Procedure for ADP3208D section. (eq. 29) 1 2pǒC A ) C BǓ R f CZ C FB + 1 f Z1 + RX (R O * RȀ) ) C Z –20dB/DEC f Z2 RO RE CX CX R O * RȀ CX D 2 V VID CA + f P1 A LX where: R’ is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.4 mW (assuming an 8−layer motherboard). RDS is the total low−side MOSFET for on resistance per phase. AD is 5. VRT is 1.25 V. LX is 150 pH for the six Panasonic SP capacitors. The compensation values can be calculated as follows: OUTPUT VOLTAGE CFB CB (R O * RȀ) ) RL I CRMS + 0.18 V RT V RT V VID Ǹ n 40 A 1 D Ǹ 2 *1 (eq. 42) 1 * 1 + 9.6 A 0.18 where IO is the output current. In a typical notebook system, the battery rail decoupling is achieved by using MLC capacitors or a mixture of MLC capacitors and bulk capacitors. In this example, the input capacitor bank is formed by eight pieces of 10 mF, 25 V MLC capacitors, with a ripple current rating of about 1.5 A each. V ID D)) IO (eq. 33) http://onsemi.com 32 ADP3208D Tuning Procedure for ADP3208D Selecting Thermal Monitor Components To monitor the temperature of a single−point hot spot, set RTTSET1 equal to the NTC thermistor’s resistance at the alarm temperature. For example, if the alarm temperature for VRTT is 100°C and a Vishey thermistor (NTHS−0603N011003J) with a resistance of 100 kW at 25°C, or 6.8 kW at 100°C, is used, the user can set RTTSET1 equal to 6.8 kW (the RTH1 at 100°C). Set Up and Test the Circuit 1. Build a circuit based on the compensation values computed from the design spreadsheet. 2. Connect a dc load to the circuit. 3. Turn on the ADP3208D and verify that it operates properly. 4. Check for jitter with no load and full load conditions. 5.0 V VCC Set the DC Load Line 31 ADP3208D R 1. Measure the output voltage with no load (VNL) and verify that this voltage is within the specified tolerance range. 2. Measure the output voltage with a full load when the device is cold (VFLCOLD). Allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (VFLHOT). If the difference between the two measured voltages is more than a few millivolts, adjust RCS2 using Equation 44. R TTSET1 TTSN - VRTT 30 C TT + R TH R Figure 45. Single−Point Thermal Monitoring To monitor the temperature of multiple−point hot spots, use the configuration shown in Figure 46. If any of the monitored hot spots reaches the alarm temperature, the VRTT signal is asserted. The following calculation sets the alarm temperature: 1 R TTSET1 + 2 ) V V R CS2(NEW) + R CS2(OLD) REF 1 * FD 2 V R TH1ALARMTEMPERATURE (eq. 43) REF where VFD is the forward drop voltage of the parallel diode. Because the forward current is very small, the forward drop voltage is very low, that is, less than 100 mV. Assuming the same conditions used for the single−point thermal monitoring example, that is, an alarm temperature of 100°C and use of an NTHS−0603N011003J Vishay thermistor; solving Equation 43 gives a RTTSET of 7.37 kW, and the closest standard resistor is 7.32 kW (1%). R PH(NEW) + R PH(OLD) 5.0 V 31 R TTSET1 R TTSET2 R TTSET3 R VRTT 30 + R OMEAS RO (eq. 45) Set the AC Load Line TTSN - (eq. 44) 6. Repeat Steps 4 and 5 until no adjustment of RPH is needed. Once this is achieved, do not change RPH, RCS1, RCS2, or RTH for the rest of the procedure. 7. Measure the output ripple with no load and with a full load with scope, making sure both are within the specifications. VCC ADP3208D V NL * V FLHOT 3. Repeat Step 2 until no adjustment of RCS2 is needed. 4. Compare the output voltage with no load to that with a full load using 5 A steps. Compute the load line slope for each change and then find the average to determine the overall load line slope (ROMEAS). 5. If the difference between ROMEAS and RO is more than 0.05 mW, use the following equation to adjust the RPH values: FD V V NL * V FLCOLD C TT R TH1 R TH2 1. Remove the dc load from the circuit and connect a dynamic load. 2. Connect the scope to the output voltage and set it to dc coupling mode with a time scale of 100 ms/div. 3. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. 4. Measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). Try to use a vertical scale of 100 mV/div or finer. R TH3 R Figure 46. Multiple−Point Thermal Monitoring The number of hot spots monitored is not limited. The alarm temperature of each hot spot can be individually set by using different values for RTTSET1, RTTSET2, ... RTTSETn. http://onsemi.com 33 ADP3208D 5. The resulting waveform will be similar to that shown in Figure 47. Use the horizontal cursors to measure VACDRP and VDCDRP, as shown in Figure 47. Do not measure the undershoot or overshoot that occurs immediately after the step. VDROOP VTRAN1 VACDRP VTRAN2 VDCDRP Figure 48. Transient Setting Waveform, Load Step 2. If both overshoots are larger than desired, try the following adjustments in the order shown. a. Increase the resistance of the ramp resistor (RRAMP) by 25%. b. For VTRAN1, increase CB or increase the switching frequency. c. For VTRAN2, increase RA by 25% and decrease CA by 25%. If these adjustments do not change the response, it is because the system is limited by the output decoupling. Check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable. 3. For load release (see Figure 49), if VTRANREL is larger than the value specified by IMVP−6+, a greater percentage of output capacitance is needed. Either increase the capacitance directly or decrease the inductor values. (If inductors are changed, however, it will be necessary to redesign the circuit using the information from the spreadsheet and to repeat all tuning guide procedures). Figure 47. AC Loadline Waveform 6. If the difference between VACDRP and VDCDRP is more than a couple of millivolts, use Equation 46 to adjust CCS. It may be necessary to try several parallel values to obtain an adequate one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason). C CS(NEW) + C CS(OLD) V ACDRP V DCDRP (eq. 46) 7. Repeat Steps 5 and 6 until no adjustment of CCS is needed. Once this is achieved, do not change CCS for the rest of the procedure. 8. Set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning VACDRP and VDCDRP are equal. 9. Ensure that the load step slew rate and the powerup slew rate are set to ~150 A/ms to 250 A/ms (for example, a load step of 50 A should take 200 ns to 300 ns) with no overshoot. Some dynamic loads have an excessive overshoot at powerup if a minimum current is incorrectly set (this is an issue if a VTT tool is in use). VTRANREL VDROOP Set the Initial Transient 1. With the dynamic load set at its maximum step size, expand the scope time scale to 2 ms/div to 5 ms/div. This results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after VDROOP (see Figure 48). Figure 49. Transient Setting Waveform, Load Release http://onsemi.com 34 ADP3208D Layout and Component Placement The following guidelines are recommended for optimal performance of a switching regulator in a PC system. problems for the entire PC system as well as noise−related operational problems in the power−converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. 2. When a power−dissipating component (for example, a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer heat to the surrounding air. To achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the MOSFETs on the opposite side of the PCB. In addition, improvements in thermal performance can be obtained using the largest possible pad area. 3. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. 4. For best EMI containment, a solid power ground plane should be used as one of the inner layers and extended under all power components. General Recommendations 1. 1. For best results, use a PCB of four or more layers. This should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 mW at room temperature. 2. When high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. If critical signal lines (including the output voltage sense lines of the ADP3208D) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise. 4. An analog ground plane should be used around and under the ADP3208D for referencing the components associated with the controller. This plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane. 5. The components around the ADP3208D should be located close to the controller with short traces. The most important traces to keep short and away from other traces are those to the FB and CSSUM pins. Refer to Figure 42 for more details on the layout for the CSSUM node. 6. The output capacitors should be connected as close as possible to the load (or connector) that receives the power (for example, a microprocessor core). If the load is distributed, the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic. 7. Avoid crossing signal lines over the switching power path loop, as described in the Power Circuitry section. Signal Circuitry 1. The output voltage is sensed and regulated between the FB and FBRTN pins, and the traces of these pins should be connected to the signal ground of the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be as small as possible. Therefore, the FB and FBRTN traces should be routed adjacent to each other, atop the power ground plane, and back to the controller. 2. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be Kelvin connected to the center point of the copper bar, which is the VCORE common node for the inductors of all the phases. 3. On the back of the ADP3208D package, there is a metal pad that can be used to heat sink the device. Therefore, running vias under the ADP3208D is not recommended because the metal pad may cause shorting between vias. Power Circuitry 1. The switching power path on the PCB should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI http://onsemi.com 35 ADP3208D ORDERING INFORMATION Device ADP3208DJCPZ−RL Temperature Range Package Package Option Shipping† −10°C to 100°C 48−Lead Frame Chip Scale Package [LFCSP_VQ] CP−48−1 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The “Z” suffix indicates Pb−Free part. All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. http://onsemi.com 36 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LFCSP48 7x7, 0.5P CASE 932AD−01 ISSUE A DATE 23 JAN 2009 SCALE 2:1 D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B D1 PIN ONE REFERENCE E1 E DIM A A1 A3 b D D1 D2 E E1 E2 e H K L M 0.20 C TOP VIEW 0.20 C H (A3) 0.10 C A NOTE 4 0.08 C SIDE VIEW A1 C 4X M D2 K 4X SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 7.00 BSC 6.75 BSC 4.95 5.25 7.00 BSC 6.75 BSC 4.95 5.25 0.50 BSC −−− 12 ° 0.20 −−− 0.30 0.50 −−− 0.60 SOLDERING FOOTPRINT* 7.30 M 5.14 13 48X 0.63 25 1 E2 PIN 1 INDICATOR 5.14 48X 7.30 L 1 37 48 e BOTTOM VIEW 48X b 0.10 C A B 0.05 C NOTE 3 PACKAGE OUTLINE 48X 0.50 PITCH 0.28 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON26683D LFCSP48, 7x7, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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