CAT1027LI-25-G

CAT1026, CAT1027 Dual Voltage Supervisory Circuits with EEPROM Serial 2k-bit I2C Description www.onsemi.com The CAT1026 and CAT1027 are complete memory and supervisory solutions for microcontroller−based systems. A EEPROM Serial 2k−bit I2C memory and a system power supervisor with brown−out protection are integrated together in low power CMOS technology. Memory interface is via a 400 kHz I2C bus. The CAT1026 and CAT1027 provide a precision VCC sense circuit with five reset threshold voltage options that support 5 V, 3.3 V and TSSOP−8 SOIC−8 CASE 948S CASE 751BD 3 V systems. The power supply monitor and reset circuit protects memory and systems controllers during power up/down and against brownout conditions. If power supply voltages are out of tolerance reset signals become active preventing the system microcontroller, ASIC, or peripherals from operating. MSOP−8 TDFN−8 The CAT1026 features two open drain reset outputs: one (RESET) CASE 846AD CASE 511AL drives high and the other (RESET) drives low whenever VCC falls below the threshold. Reset outputs become inactive typically 200 ms after the supply voltage exceeds the reset threshold value. With both active high and low reset signals, interface to microcontrollers and ORDERING INFORMATION other ICs is simple. CAT1027 has only a RESET output. In addition, For Ordering Information details, see page 13. the RESET pin can be used as an input for push−button manual reset capability. The CAT1026 and CAT1027 provide an auxiliary voltage sensor input, VSENSE, which is used to monitor a second system supply. The auxiliary high impedance comparator drives the open drain output, VLOW, whenever the sense voltage is below 1.25 V threshold. The CAT1027 is designed with a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. The CAT1027 features a watchdog timer interrupt input, WDI. The on−chip 2k−bit EEPROM memory features a 16−byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up. Available packages include a surface mount, 8−pin SOIC, 8−pin TSSOP, 8−pin TDFN and 8−pin MSOP packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint is 3 x 3 mm. Features • Precision VCC Power Supply Voltage Monitor • • • • • • • 5 V, 3.3 V and 3 V Systems Five Threshold Voltage Options Additional Voltage Monitoring ♦ Externally Adjustable Down to 1.25 V Watchdog Timer (CAT1027 Only) Active High or Low Reset ♦ Valid Reset Guaranteed at VCC = 1 V 400 kHz I2C Bus 2.7 V to 5.5 V Operation Low Power CMOS Technology ♦ • • • • • • ♦ © Semiconductor Components Industries, LLC, 2011 May, 2018 − Rev. 19 • 1 16−Byte Page Write Buffer Built−in Inadvertent Write Protection 1,000,000 Program/Erase Cycles Manual Reset Capability 100 Year Data Retention Industrial and Extended Temperature Ranges 8−Pin, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm foot−print) Packages ♦ TDFN max Height is 0.8 mm These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Publication Order Number: CAT1026/D CAT1026, CAT1027 Table 1. RESET THRESHOLD OPTION Part Dash Number Minimum Threshold Maximum Threshold −45 4.50 4.75 −42 4.25 4.50 −30 3.00 3.15 −28 2.85 3.00 −25 2.55 2.70 BLOCK DIAGRAM EXTERNAL LOAD SENSEAMPS SHIFT REGISTERS DOUT ACK VCC WORDADDRESS BU F F E R S VSS COLUMN DECODERS STA RT/ STOP LOGIC SDA XDEC 2kbit EEPROM CONTROL LOGIC DATA IN STORAGE HIGHVOLTAGE/ TIMING CONTROL V CC Monitor V CC STATE COUNTERS RESET + Controller V REF AuxiliaryVoltage Monitor V SENSE RESET RESET (CAT1026) + - SLAVE ADDRESS WDI COMPARATORS (CAT1027) V LOW V REF www.onsemi.com 2 SC L CAT1026, CAT1027 PIN CONFIGURATION DIP Package (L) SOIC Package (W) TSSOP Package (Y) MSOP Package (Z) VLOW 1 RESET 2 VSENSE 3 CAT1026 (Bottom View) TDFN Package: 3 mm x 3 mm 0.8 mm maximum height − (ZD4) VLOW 2 RESET 3 VSENSE 4 VSS 8 RESET 7 SCL SCL 6 SDA 5 8 1 VLOW 2 RESET 3 VSENSE 4 VSS VCC 7 RESET 6 VSS 4 5 SDA VLOW 1 8 VCC VCC RESET 2 7 WDI WDI 7 VSENSE 3 6 SCL SCL 6 VSS 4 5 SDA SDA 5 CAT1027 1 VCC 8 CAT1026 CAT1027 PIN DESCRIPTION RESET/RESET: RESET OUTPUTs (RESET CAT1026 Only) These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull−down resistor, and the RESET pin must be connected through a pull−up resistor. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire−ORed with other open drain or open collector outputs. SCL: SERIAL CLOCK Serial clock input. VSENSE : AUXILIARY VOLTAGE MONITOR INPUT The VSENSE input is a second voltage monitor which is compared against CAT1026 and CAT1027 internal reference voltage of 1.25 V typically. Whenever the input voltage is lower than 1.25 V, the open drain VLOW output will be driven low. An external resistor divider is used to set the voltage level to be sensed. Connect VSENSE to VCC if unused. VLOW : AUXILIARY VOLTAGE MONITOR OUTPUT This open drain output goes low when VSENSE is less than 1.25 V and goes high when VSENSE exceeds the reference voltage. WDI (CAT1027 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active. Table 2. PIN FUNCTION Pin Name RESET Function Active Low Reset Input/Output VSS Ground SDA Serial Data/Address SCL Clock Input RESET VCC VSENSE Active High Reset Output (CAT1026 Only) Power Supply Auxiliary Voltage Monitor Input VLOW Auxiliary Voltage Monitor Output WDI Watchdog Timer Interrupt (CAT1027 Only) Table 3. OPERATING TEMPERATURE RANGE Industrial −40°C to 85°C Extended −40°C to 125°C www.onsemi.com 3 CAT1026, CAT1027 Table 4. CAT102X FAMILY OVERVIEW Device Manual Reset Input Pin Watchdog Watchdog Monitor Pin Write Protection Pin CAT1021 n n SDA n CAT1022 n n SDA CAT1023 n n WDI CAT1024 n CAT1025 n Independent Auxiliary Voltage Sense RESET: Active High and LOW EEPROM n 2k 2k 2k n 2k n CAT1026 n CAT1027 n WDI n 2k n 2k 2k n NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. SPECIFICATIONS Table 5. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Temperature Under Bias –55 to +125 °C Storage Temperature –65 to +150 °C −2.0 to VCC + 2.0 V −2.0 to 7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 s) 300 °C Output Short Circuit Current (Note 2) 100 mA Voltage on any Pin with Respect to Ground (Note 1) VCC with Respect to Ground Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time. Table 6. D.C. OPERATING CHARACTERISTICS VCC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units mA ILI Input Leakage Current VIN = GND to VCC −2 10 −10 ILO Output Leakage Current VIN = GND to VCC 10 mA ICC1 Power Supply Current (Write) fSCL = 400 kHz VCC = 5.5 V 3 mA ICC2 Power Supply Current (Read) fSCL = 400 kHz VCC = 5.5 V 1 mA ISB Standby Current VCC = 5.5 V VIN = GND or VCC CAT1026 50 mA CAT1027 60 mA VIL (Note 3) Input Low Voltage −0.5 0.3 x VCC V VIH (Note 3) Input High Voltage 0.7 x VCC VCC + 0.5 V VOL Output Low Voltage (SDA, RESET) IOL = 3 mA VCC = 2.7 V 0.4 V VOH Output High Voltage (RESET) IOH = −0.4 mA VCC = 2.7 V www.onsemi.com 4 VCC − 0.75 V CAT1026, CAT1027 Table 6. D.C. OPERATING CHARACTERISTICS VCC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified. Symbol VTH VRVALID VRT (Note 4) VREF Parameter Test Conditions Reset Threshold Min Typ Max Units V CAT102x−45 (VCC = 5.0 V) 4.50 4.75 CAT102x−42 (VCC = 5.0 V) 4.25 4.50 CAT102x−30 (VCC = 3.3 V) 3.00 3.15 CAT102x−28 (VCC = 3.3 V) 2.85 3.00 CAT102x−25 (VCC = 3.0 V) 2.55 2.70 Reset Output Valid VCC Voltage 1.00 V Reset Threshold Hysteresis 15 mV Auxiliary Voltage Monitor Threshold 1.2 1.25 1.3 VS Max Units 3. VIL min and VIH max are reference values only and are not tested. 4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. Table 7. CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5 V Test Symbol COUT (Note 5) CIN (Note 5) Test Conditions Output Capacitance VOUT = 0 V 8 pF Input Capacitance VIN = 0 V 6 pF Max Units Table 8. AC CHARACTERISTICS VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle (Note 6) Parameter Symbol Min fSCL Clock Frequency 400 kHz tSP Input Filter Spike Suppression (SDA, SCL) 100 ns tLOW Clock Low Period 1.3 ms tHIGH Clock High Period 0.6 ms tR (Note 5) SDA and SCL Rise Time 300 ns tF (Note 5) SDA and SCL Fall Time 300 ns tHD; STA Start Condition Hold Time 0.6 ms tSU; STA Start Condition Setup Time (for a Repeated Start) 0.6 ms tHD; DAT Data Input Hold Time 0 ns tSU; DAT Data Input Setup Time 100 ns tSU; STO Stop Condition Setup Time 0.6 tAA SCL Low to Data Out Valid tDH Data Out Hold Time 50 ns tBUF (Note 5) Time the Bus must be Free Before a New Transmission Can Start 1.3 ms tWC (Note 7) Write Cycle Time (Byte or Page) ms 900 5 ns ms 5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 6. Test Conditions according to “AC Test Conditions” table. 7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. www.onsemi.com 5 CAT1026, CAT1027 Table 9. RESET CIRCUIT AC CHARACTERISTICS Symbol tPURST tRDP tGLITCH tWD tRPD2 Test Conditions Min Typ Max Units Power−Up Reset Timeout Parameter Note 2 130 200 270 ms VTH to RESET output Delay Note 3 5 ms Notes 4 and 5 30 ns 2.1 s 5 ms Max Units VCC Glitch Reject Pulse Width Watchdog Timeout Note 1 VSENSE to VLOW Delay Note 5 1.0 1.6 Table 10. POWER−UP TIMING (Notes 6 and 7) Symbol Parameter Test Conditions Min Typ tPUR Power−Up to Read Operation 270 ms tPUW Power−Up to Write Operation 270 ms Table 11. AC TEST CONDITIONS Parameter Input Pulse Voltages Test Conditions 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times 10 ns Input Reference Voltages 0.3 x VCC , 0.7 x VCC Output Reference Voltages 0.5 x VCC Output Load Current Source: IOL = 3 mA; CL = 100 pF Table 12. RELIABILITY CHARACTERISTICS Symbol Reference Test Method Min Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte TDR (Note 6) Data Retention MIL−STD−883, Test Method 1008 100 Years VZAP (Note 6) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 Volts JEDEC Standard 17 100 mA NEND (Note 6) ILTH (Notes 6 & 8) 1. 2. 3. 4. 5. 6. 7. 8. Parameter Latch−Up Max Units Test Conditions according to “AC Test Conditions” table. Power−up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table Power−Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table VCC Glitch Reference Voltage = VTHmin; Based on characterization data 0 < VSENSE − VCC, VLOW Output Reference Voltage and Load according to “AC Test Conditions” Table. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to VCC + 1 V. www.onsemi.com 6 CAT1026, CAT1027 DEVICE OPERATON Reset Controller Description Data Protection The CAT1026 and CAT1027 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs. During power−up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200 ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. During power−down, the RESET outputs will be active when VCC falls below VTH. The RESET output will be valid so long as VCC is > 1.0 V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Reset output timing is shown in Figure 1. The CAT1026 and CAT1027 devices have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal nonvolatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5 ms) before VCC reaches the minimum value of 2 V. In addition, to avoid data corruption due to the loss of power supply voltage during the memory internal write operation, the system controller should monitor the unregulated DC power. Using the second voltage sensor, VSENSE, to monitor an unregulated power supply, the CAT1026 and CAT1027 signals an impending power failure by setting VLOW low. Manual Reset Capability The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET input will initiate a reset timeout after detecting a high to low transition. When RESET I/O is driven to the active state, the 200 ms timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT1027 device will provide a reset signal after a time−out interval of 1.6 seconds for a lack of activity. CAT1027 is designed with the Watchdog timer feature on the WDI pin. If WDI does not toggle within 1.6 second intervals, the reset condition will be generated on reset output. The watchdog timer is cleared by any transition on monitored line. As long as reset signal is asserted, the watchdog timer will not count and will stay cleared. Monitoring Two Voltages The CAT1026 and CAT1027 feature a second voltage sensor, VSENSE, which drives the open drain VLOW output low whenever the input voltage is below 1.25 V. The auxiliary voltage monitor timing is shown in Figure 2. By using an external resistor divider the sense circuitry can be set to monitor a second supply in the system. The circuit shown in Figure 3 provides an externally adjustable threshold voltage, VTH_ADJ to monitor the auxiliary voltage. The low leakage current at VSENSE allows the use of large value resistors, to reduce the system power consumption. The VLOW output can be externally connected to the RESET output to generate a reset condition when either of the supplies is invalid. In other applications, VLOW signal can be used to interrupt the system controller for an impending power failure notification. www.onsemi.com 7 CAT1026, CAT1027 tGLITCH VTH VRVALID t PURST VCC t RPD t RPD t PURST RESET RESET Figure 1. RESET Output Timing VREF VSENSE tRPD2 tRPD2 tRPD2 VLOW Figure 2. Auxiliary Voltage Monitor Timing VCC VAUX CAT1026/27 Externally adjustable threshold R1 VTH-ADJ VLOW VSENSE R2 VTH-ADJ = VREF × R + R2 R1 + R2 = 1.25V × 1 R2 R2 Figure 3. Auxiliary Voltage Monitor www.onsemi.com 8 Power Fail Interrupt tRPD2 CAT1026, CAT1027 EMBEDDED EEPROM OPERATON 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. The CAT1026 and CAT1027 feature a 2−kbit embedded serial EEPROM that supports the I2C Bus data transmission protocol. This Inter−Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. Start Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT1026 and CAT1027 monitor the SDA and SCL lines and will not respond until this condition is met. I2C Bus Protocol Stop Condition The features of the I2C bus protocol are defined as follows: 1. Data transfer may be initiated only when the bus is not busy. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING After the Master sends a START condition and the slave address byte, the CAT1026 and CAT1027 monitor the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1026 and CAT 1027 then perform a Read or Write operation depending on the R/W bit. The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8−bit slave address are programmable in metal and the default is 1010. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 4. Bus Timing SCL SDA 8TH BIT ACK BYTE n tWR STOP CONDITION Figure 5. Write Cycle Timing www.onsemi.com 9 START CONDITION ADDRESS CAT1026, CAT1027 ACKNOWLEDGE When the CAT1026 and CAT1027 begin a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1026 and CAT1027 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT1026 and CAT1027 respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. WRITE OPERATIONS Byte Write Master device transmits the data to be written into the addressed memory location. The CAT1026 and CAT1027 acknowledge once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non−volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8−bit address that is to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the SDA SCL START BIT STOP BIT Figure 6. Start/Stop Timing SCL FROM MASTER 8 1 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 7. Acknowledge Timing Default Configuration 1 0 1 0 0 Figure 8. Slave Address Bits www.onsemi.com 10 0 0 R/W CAT1026, CAT1027 Page Write If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1026 and CAT1027 in a single write cycle. The CAT1026 and CAT1027 write up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1026 and CAT1027 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS S T O P DATA S P A C K A C K A C K Figure 9. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T BYTE ADDRESS (n) SLAVE ADDRESS DATA n S T DATA n+15 O P DATA n+1 S P A C K A C K A C K A C K A C K Figure 10. Page Write Timing Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT1026 and CAT1027 initiate the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. READ OPERATIONS The READ operation for the CAT1026 and CAT1027 is initiated in the same manner as the write operation with one exception, the R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. www.onsemi.com 11 CAT1026, CAT1027 BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS P S A C K DATA N O A C K SCL 8 9 SDA8TH BIT DATA OUT NO ACK STOP Figure 11. Immediate Address Read Timing Immediate/Current Address Read again, this time with the R/W bit set to one. The CAT1026 and CAT1027 then respond with its acknowledge and send the 8−bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. The CAT1026 and CAT1027 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1026 and CAT1027 receive its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8−bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1026 and CAT1027 sends the initial 8− bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT1026 and CAT1027 will continue to output an 8−bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1026 and CAT1027 is sent sequentially with the data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT1026and CAT1027 address bits so that the entire memory array can be read during one operation. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1026 and CAT1027 acknowledges, the Master device sends the START condition and the slave address BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS (n) S S T O P SLAVE ADDRESS S A C K A C K Figure 12. Selective Read Timing www.onsemi.com 12 P A C K DATA n N O A C K CAT1026, CAT1027 BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K Figure 13. Sequential Read Timing ORDERING INFORMATION Orderable Part Numbers − CAT1026 Series (See Notes 1 − 5) Device Reset Threshold CAT1026WI−45−GT3 4.50 V − 4.75 V CAT1026WI−42−GT3 4.25 V − 4.50 V CAT1026WI−30−GT3 3.00 V − 3.15 V CAT1026WI−28−GT3 2.85 V − 3.00 V CAT1026WI−25−GT3 2.55 V − 2.70 V CAT1026YI−45−GT3 4.50 V − 4.75 V CAT1026YI−30−GT3 3.00 V − 3.15 V CAT1026YI−28−GT3 2.85 V − 3.00 V CAT1026YI−25−GT3 2.55 V − 2.70 V CAT1026ZI−45−GT3 4.50 V − 4.75 V CAT1026ZI−42−GT3 4.25 V − 4.50 V CAT1026ZI−30−GT3 3.00 V − 3.15 V CAT1026ZI−28−GT3 2.85 V − 3.00 V CAT1026ZI−25−GT3 2.55 V − 2.70 V CAT1026ZD4I−45T3* 4.50 V − 4.75 V CAT1026ZD4I−42T3* 4.25 V − 4.50 V CAT1026ZD4I−30T3* 3.00 V − 3.15 V CAT1026ZD4I−28T3* 2.85 V − 3.00 V CAT1026ZD4I−25T3* 2.55 V − 2.70 V Package Shipping† SOIC TSSOP 3000 Tape & Reel MSOP TDFN †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1. All packages are RoHS−compliant (Lead−free, Halogen−free). 2. The standard lead finish is NiPdAu. 3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 4. TDFN not available in NiPdAu (–G) version. 5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com www.onsemi.com 13 CAT1026, CAT1027 Orderable Part Numbers − CAT1027 Series (See Notes 1 − 5) Device Reset Threshold CAT1027WI−45−GT3 4.50 V − 4.75 V CAT1027WI−42−GT3 4.25 V − 4.50 V CAT1027WI−30−GT3 3.00 V − 3.15 V CAT1027WI−28−GT3 2.85 V − 3.00 V CAT1027WI−25−GT3 2.55 V − 2.70 V CAT1027YI−45−GT3 4.50 V − 4.75 V CAT1027YI−42−GT3 4.25 V − 4.50 V CAT1027YI−30−GT3 3.00 V − 3.15 V CAT1027YI−28−GT3 2.85 V − 3.00 V CAT1027YI−25−GT3 2.55 V − 2.70 V CAT1027ZI−45−GT3 4.50 V − 4.75 V CAT1027ZI−42−GT3 4.25 V − 4.50 V CAT1027ZI−30−GT3 3.00 V − 3.15 V CAT1027ZI−28−GT3 2.85 V − 3.00 V CAT1027ZI−25−GT3 2.55 V − 2.70 V CAT1027ZD4I−45T3* 4.50 V − 4.75 V CAT1027ZD4I−42T3* 4.25 V − 4.50 V CAT1027ZD4I−30T3* 3.00 V − 3.15 V CAT1027ZD4I−28T3* 2.85 V − 3.00 V CAT1027ZD4I−25T3* 2.55 V − 2.70 V Package Shipping† SOIC TSSOP 3000 Tape & Reel MSOP TDFN †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1. All packages are RoHS−compliant (Lead−free, Halogen−free). 2. The standard lead finish is NiPdAu. 3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 4. TDFN not available in NiPdAu (–G) version. 5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. www.onsemi.com 14 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 DATE 19 DEC 2008 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 A θ c e b SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. DOCUMENT NUMBER: DESCRIPTION: 98AON34272E SOIC 8, 150 MILS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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