CAT1232LPZ-G

CAT1232LP/CAT1832 5V and 3.3V Supply Monitor, Watchdog Timer, Manual Reset, with Active High & Low Resets FEATURES DESCRIPTION ■ Selectable reset voltage tolerance The CAT1232LP and CAT1832 microprocessor supervisors can halt and restart a “hung-up” or “stalled” microprocessor, restart a microprocessor after a power failure, and debounce a manual/push-button microprocessor reset switch. The devices are drop in replacements for the Maxim/Dallas Semiconductor DS1232LP and DS1832 supervisors — CAT1232LP for 5V supply — CAT1832 for 3.3V supply ■ Selectable watchdog period: 150ms, 600ms or 1.2 sec ■ Two reset outputs Precision reference and comparator circuits monitor the 5V or 3.3V system power supply voltage, VCC. During power-up or when the power supply falls outside selectable tolerance limits, both the RESET and RESET become active. After the power supply voltage rises above the RESET threshold voltage, the reset signals remain active for a minimum of 250ms, allowing the power supply and system processor to stabilize. The trip-point tolerance input, TOL, selects the trip level tolerance to be either 5% or 10% for the CAT1232LP 5V supply and 10% or 20% for the CAT1832 3.3V supply. — Active high, push-pull reset output — Active low, open-drain reset output (CAT1232LP) — Active low, push-pull reset output (CAT1832) ■ Debounced manual push-button reset ■ Compact SOIC and MSOP packages APPLICATIONS ■ Microprocessor Systems Each device has a push-pull, active HIGH reset output. The CAT1232LP also has an open drain, active LOW reset output while the CAT1832 also has a push-pull, active LOW reset output. ■ Portable Equipment ■ Controllers ■ Single Board Computers A debounced manual reset input activates the reset outputs and holds them active for a minimum period of 250ms after being released. ■ Instrumentations ■ Telecommunications Also included is a watchdog timer to reset a microprocessor that has stopped due to a software or hardware failure. Three watchdog time-out periods are selectable: 150ms, 600ms and 1.2sec. If the ST input is not strobed low before the watchdog time out period expires, the reset signals become active for a minimum of 250ms. FUNCTIONAL DIAGRAM VCC TOL Tolerance Selection + Reference – (CAT1232LP) RESET VCC 40kΩ RESET PBRST Push Button Debounce TD Watchdog Timebase Selection ST Watchdog Transition Detector © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Reset & Watchdog Timer 1 RESET (CAT1832) Doc. No. 25089, Rev. B CAT1232LP/CAT1832 ORDERING INFORMATION Solder Plate Lead Finish Ordering Part Number Green Sn Lead Finish Ordering Part Number Green NiPdAu Lead Finish Ordering Part Number Parts per Tube Package Parts Per Reel Reel Size (inch) CAT1232LPP CAT1232LPL CAT1232LPL-G 8-lead, DIP 50 — — CAT1232LPJ CAT1232LPW CAT1232LPW-G 16-lead, SOIC 47 — — CAT1232LPS CAT1232LPV CAT1232LPV-G 8-lead, SOIC 100 — — CAT1232LPR CAT1232LPZ CAT1232LPZ-G MSOP 100 — — CAT1232LPJ-T13 CAT1232LPW-T13 CAT1232LPW-GT2 16-lead, SOIC — 2,000 13 CAT1232LPS-T13 CAT1232LPV-T13 CAT1232LPV-GT2 8-lead, SOIC — 2,000 13 CAT1232LPR-T13 CAT1232LPZ-T13 CAT1232LPGZ-GT25 MSOP — 2,500 13 CAT1832P CAT1832L CAT1832L-G 8-lead, DIP 50 — — CAT1832S CAT1832V CAT1832W-G 8-lead, SOIC 100 — — CAT1832R CAT1832Z CAT1832Z-G MSOP 100 — — CAT1832S-T13 CAT1832V-T13 CAT1832W-GT2 8-lead, SOIC — 2,000 13 CAT1832R-T13 CAT1832Z-T13 CAT1832Z-GT25 MSOP — 2,500 13 The “-G” NiPdAu Lead Finish is only available on the Green packager versions of this device. PIN CONFIGURATION 16-Lead SOIC 8-Lead SOIC/MSOP/DIP PBRST 1 8 VCC TD 2 7 ST NC 1 16 NC PBRST 2 15 VCC TOL 3 6 RESET NC 3 14 NC GND 4 5 RESET TD 4 13 ST NC 5 12 NC TOL 6 11 RESET NC 7 10 NC GND 8 9 RESET PIN DESCRIPTION Pin Number Pin Number 8-Lead Package 16-Lead Package 1 2 2 4 Name PBRST TD 3 6 TOL 4 5 8 9 GND RESET 6 7 8 11 13 15 1, 3. 5, 7, 10, 12, 14, 16 RESET ST VCC NC Doc. No. 25089, Rev. B Function Debounced manual pushbutton reset input Watchdog typical time delay selection: a) tTD = 150ms for TD = GND b) tTD = 600ms for TD = Open c) tTD = 1200ms for TD = VCC CAT1232LP TOL selects 5% (TOL = GND) or 10% (TOL = VCC) trip point tolerance. CAT1832 TOL selects 10% (TOL = GND) or 20% TOL = VCC) trip point tolerance. Ground Active HIGH reset output. RESET is active 1. If VCC falls below the reset voltage trip point 2. If PBRST is low 3. If ST is not strobed low before the timeout period set by TD expires. 4. During power-up. Active LOW reset output. (See RESET) Strobe Input Power Supply No internal connection 2 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1232LP/CAT1832 ABSOLUTE MAXIMUM RATINGS* Voltage on VCC ....................................... -0.5V to 7.0V Maximum Junction Temperature ...................... 125°C Voltage on ST and TD ................. -0.5V to VCC + 0.5V Storage Temperature Range ............ -65°C to +150°C Voltage on PBRST, RESET and RESET ............................ -0.5V to VCC + 0.5V Lead Soldering Temperature (10 sec) .............. 300°C Operating Temperature Range ........... -40°C to +85°C ELECTRICAL CHARACTERISTICS Unless otherwise stated, 1.0V ≤ VCC ≤ 5.5V and over the operating temperature range of -40°C to +85°C. All voltages are referenced to ground. Symbol Parameter VCC Conditions Min Supply Voltage ICC1 Supply Current VIH ST and PBRST Input High Level VIL ST and PBRST Input Low Level Typ 1.0 Max Units 5.5 V VCC = 5.5V, CAT1232LP 35 50 VCC = 3.6V, CAT1832 20 35 (5) 2 (6) VCC + 0.3V VCC - 0.4V VCC = 5.5V, CAT1232LP – 0.3 µA V 0.8 V VCC = 3.6V, CAT1832 0.5 VCCTP VCC Trip Point (TOL = GND) CAT1232LP 4.50 4.62 4.74 V VCCTP VCC Trip Point (TOL = VCC) CAT1232LP 4.25 4.37 4.49 V VCCTP VCC Trip Point (TOL = GND) CAT1832 2.80 2.88 2.97 V VCCTP VCC Trip Point (TOL = VCC) CAT1832 2.47 2.55 2.64 V tTD tTD tTD Watchdog Time-Out Period Watchdog Time-Out Period Watchdog Time-Out Period TD = GND TD = VCC TD floating 62.5 500 250 150 1200 600 250 2000 1000 ms ms ms VOH Output Voltage I = – 500µA(3) VCC - 0.5V VCC - 0.1V V – 350 µA IOH Output Current IOL Output Current Output = 0.4V, IIL RPU Input Leakage Internal Pull-Up Resistor (1) CIN COUT Input Capacitance 5 pF Output Capacitance 7 pF tRST Reset Active Time tPDLY tRPU tR – 1.0 32 mA µA kΩ PBRST Manual Reset Minimum Low Time tF 10 1.0 55 tPB tST tRPD Output = 2.4V(2) (1) PBRST = VIL 20 250 ST Pulse Width VCC Fail Detect to RESET or RESET VCC Slew Rate PBRST Stable LOW to RESET and RESET Active VCC Detect to RESET or RESET Inactive (4) VCC Slew Rate 4.25V to 4.75V ms 600 1000 ms 5 8 ns µs 20 µs ms 1000 ms 20 20 tRISE = 5µs 250 0 Notes: (1) PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor (RPU). (2) RESET is an open drain output on the CAT1232LP. (3) RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 40 600 ns (4) Must not exceed the minimum watchdog time-out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST must be strobed. (5) Measured with VCC ≥ 2.7V. (6) Measured with VCC < 2.7V. 3 Doc. No. 25089, Rev. B CAT1232LP/CAT1832 TYPICAL CHARACTERISTICS For the CAT1232LP, VCC = 5V and TAMB = 25°C unless otherwise stated. Threshold Voltage vs. Temperature (5% TOL) 4.450 THRESHOLD VOLTAGE (V) THRESHOLD VOLTAGE (V) Threshold Voltage vs. Temperature (10% TOL) 4.445 TOL = Vcc (10%) 4.440 4.435 0 50 4.625 TOL = GND (5%) 4.620 4.615 4.610 -50 4.430 -50 4.630 100 Supply Current vs. Temperature 800 RESET ACTIVE TIME (ms) SUPPLY CURRENT (µA) Vcc = 5.5V Vcc = 4.5V 20 10 0 50 100 TEMPERATURE (°C) TD = open 700 600 500 Vcc = 5.5V Vcc = 4.5V 400 300 -50 0 50 100 TEMPERATURE (°C) Reset Active Time Waveform Doc. No. 25089, Rev. B 100 Reset Active Time vs. Temperature 40 0 -50 50 TEMPERATURE (°C) TEMPERATURE (°C) 30 0 Transient Response 4 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1232LP/CAT1832 APPLICATION INFORMATION Connecting TOL to VCC makes the VCC trip threshold 4.37V for the CAT1232LP and 2.55V for the CAT1832. SUPPLY VOLTAGE MONITOR After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. Reset Signal Polarity and Output Stage Structure RESET is an active LOW signal. It is developed with an open drain driver in the CAT1232LP. A pull-up resistor is required, typical values are 10kΩ to 50kΩ. The CAT1832 uses a CMOS push-pull output stage for the RESET. On power-down, once VCC falls below the reset threshold the RESET outputs will remain active and are guaranteed valid down to a VCC level of 1.0V. RESET is an active High signal developed by a CMOS push-pull output stage and is the logical opposite to RESET. Trip Point Tolerance Selection The TOL input is used to select the VCC trip point threshold. This selection is made connecting the TOL input to ground or VCC. Connecting TOL to Ground makes the VCC trip threshold 4.62V for the CAT1232LP and 2.88V for the CAT1832. Tolerance Select Voltage Trip Point Tolerance MIN NOMINAL MAX CAT1232LP TOL = VCC 10 % 4.25 4.37 4.49 CAT1232LP TOL = GND 5% 4.50 4.62 4.74 CAT1832 TOL = VCC 20 % 2.47 2.55 2.64 CAT1832 TOL = GND 10 % 2.80 2.88 2.97 tF tR VCCTP(MIN) VCC VCCTP(MAX) VCCTP VCC Trip Point Voltage (V) VCCTP(MAX) VCCTP VCCTP(MIN) tRPU RESET VOL tRPD RESET VOH RESET RESET VOH VOL Figure 1. Timing Diagram: Power Up Figure 2. Timing Diagram: Power Down Manual Reset Operation Push-button input, PBRST, allows the user to issue reset signals. The pushbutton input is debounced and is pulled high through an internal 40kΩ resistor. No external pull-up resistor is required, since PBRST is pulled high by an internal 40kΩ resistor. PBRST can be driven from a TTL or CMOS logic line or short-ed to ground with a mechanical switch. When PBRST is held low for the minimum time of 20 ms, both resets become active and remain active for a minimum time period of 250ms after PBRST returns high. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 25089, Rev. B CAT1232LP/CAT1832 WATCHDOG TIMER AND ST INPUT A watchdog timer stops and restarts a microprocessor that has stopped proper operation or become “hung”. The watchdog performs this function by monitoring the ST input. After the reset outputs go inactive the ST input must be strobed with a high-to-low signal transition prior to the minimum watchdog timeout period. However if the ST input is not strobed with a high-to-low signal transition prior to a watchdog timeout the reset outputs will become active for TRST reseting and restarting the microprocessor. Once the resets return to the inactive state the watchdog timer restarts the process. MIN NOMINAL MAX GND 62.5 150 250 Floating 250 600 1000 VCC 500 1200 2000 3.3V CAT1832 1 The TD input allows the user to select from three predetermined watchdog timeout periods. Always use the minimum timeout period to determine the required frequency of ST high-to-low transitions and the maximum to determine the time prior to the reset outputs becoming active. ST pulse widths must be 20ns or greater. 2 3 4 The watchdog timer cannot be disabled. It must be strobed with a high-to-low signal transition to avoid a watchdog timeout and subsequent reset. 2 3 4 PBRST TD TOL GND VCC ST RESET RESET PBRST TD VCC ST TOL RESET GND RESET 8 7 I/O µP 6 5 RESET Figure 4. CAT1832 Application Circuit: Pushbutton Reset 5V CAT1232LP 1 Watchdog Time-out Period (ms) TD Voltage Level 8 MREQ 7 10k Address Bus µP 6 RESET Decoder 5 Figure 5. CAT1232LP Application Circuit: Watchdog Timer tPB PBRST tPDLY VIH Valid Strobe ST VIL RESET tRST RESET VOH VOL tTD (Min) tTD (Min) RESET Note: ST is ignored whenever a reset is active. Figure 6. Timing Diagram: Pushbutton Reset Doc. No. 25089, Rev. B Invalid Strobe tST tRST RESET Valid Strobe Figure 7. Timing Diagram: Strobe Input 6 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1232LP/CAT1832 PACKAGE MECHANICAL 16-LEAD WIDE BODY SOIC (300mil) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.010 (0.25) X 45 0.029 (0.75) 0.3977 (10.10) 0.4133 (10.50) 0.0091 (0.23) 0.0125 (0.32) 0.0926 (2.35) 0.1043 (2.65) 0.050 (1.27) BSC 0 –8 0.0040 (0.10) 0.0118 (0.30) 0.013 (0.33) 0.020 (0.51) 0.016 (0.40) 0.050 (1.27) Notes: 1. Complies with JEDEC publication 95 MS-013 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 8-LEAD DIP (300mil) 0.245 (6.17) 0.295 (7.49) 0.300 (7.62) 0.325 (8.26) 0.355 (9.02) 0.400 (10.16) 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX 0.015 (0.38) — 0.110 (2.79) 0.150 (3.81) 0.100 (2.54) BSC 0.310 (7.87) 0.380 (9.65) 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 25089, Rev. B CAT1232LP/CAT1832 PACKAGE MECHANICAL 8-LEAD MSOP 0.38 0.28 0.0150 0.0110 0.1970 0.1890 5.00 4.80 S 0.0256 [0.65] BSC 0.0433 [1.10] MAX. 0.1220 0.1142 3.10 2.90 0.0374 0.0295 0.0059 0.0020 0.039 [0.10] MAX. 0.15 0.05 0.95 0.75 0.1220 0.1142 S 0.0276 0.0157 S 3.10 2.90 0˚ - 6˚ 0.70 0.40 8-LEAD Narrow Body SOIC (150mil) 0.1497 (3.90) 0.1574 (4.00) 0.2294 (5.90) 0.2440 (6.20) 0.0099 (0.25) X 45 0.0196 (0.75) 0.1990 (4.90) 0.1969 (5.00) 0.0075 (0.19) 0.0099 (0.25) 0.0926 (2.35) 0.1043 (2.65) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) Doc. No. 25089, Rev. B 0 –8 0.0040 (0.10) 0.0099 (0.25) 0.016 (0.40) 0.050 (1.27) 8 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date Revision Comments 06/13/2005 00 Initial Issue 07/26/2005 A Update Electrical Characteristics 03/27/2006 B Update Document Title Update Ordering Information Add Typical Characteristics Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 25089 B 03/27/06