CAT25020LI

CAT25010, CAT25020, CAT25040 1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM FEATURES DESCRIPTION „ 10 MHz SPI compatible The CAT25010/20/40 are 1-Kb/2-Kb/4-Kb Serial CMOS EEPROM devices internally organized as 128x8/256x8/512x8 bits. They feature a 16-byte page write buffer and support the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip ¯¯ ) input. In addition, the required bus signals Select (CS are a clock input (SCK), data input (SI) and data ¯¯¯¯¯ input may be used to output (SO) lines. The HOLD pause any serial communication with the CAT25010/20/40 device. These devices feature software and hardware write protection, including partial as well as full array protection. „ 1.8V to 5.5V supply voltage range „ SPI modes (0,0) & (1,1) „ 16-byte page write buffer „ Self-timed write cycle „ Hardware and software protection „ Block write protection – Protect 1/4, 1/2 or entire EEPROM array „ Low power CMOS technology „ 1,000,000 program/erase cycles „ 100 year data retention „ Industrial and Extended temperature range „ RoHS-compliant 8-lead PDIP, SOIC, TSSOP and 8-pad TDFN packages PIN CONFIGURATION PDIP (L) SOIC (V) TSSOP (Y) TDFN (VP2) FUNCTIONAL SYMBOL VCC ¯¯ CS 1 8 VCC SO 2 ¯¯¯¯¯ 7 HOLD ¯¯¯ WP 3 6 SCK VSS 4 5 SI SI CS WP HOLD PIN FUNCTION Pin Name Function ¯¯ CS Chip Select SO Serial Data Output ¯¯¯ WP Write Protect VSS Ground SI Serial Data Input SCK Serial Clock ¯¯¯¯¯ HOLD Hold Transmission Input VCC Power Supply © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25010 CAT25020 CAT25040 SO SCK VSS For Ordering Information details, see page 16. 1 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 ABSOLUTE MAXIMUM RATINGS(1) Parameters Ratings Units -65 to +150 ºC -0.5 to VCC + 0.5 V Storage Temperature Voltage on any Pin with Respect to Ground (2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, TA=-40°C to +125°C unless otherwise specified. Symbol Parameter Test Conditions Min Max Units 10MHz / -40°C to 85°C 2 mA 5MHz / -40°C to 125°C 2 mA 2 µA TA= -40°C to +85°C 4 µA TA= -40°C to +125°C 5 µA -2 2 µA TA= -40°C to +85°C -1 1 µA TA= -40°C to +125°C -1 2 µA ICC Supply Current Read, Write, VCC = 5.0V, SO open ISB1 Standby Current ¯¯ = VCC, VIN = GND or VCC , CS ¯¯¯ WP = VCC, VCC = 5.0V ISB2 Standby Current ¯¯ = VCC, VIN = GND or VCC , CS ¯¯¯ WP = GND, VCC = 5.0V IL Input Leakage Current VIN = GND or VCC ILO Output Leakage Current ¯¯ = VCC , CS VOUT = GND or VCC VIL Input Low Voltage -0.5 0.3VCC V VIH Input High Voltage 0.7VCC VCC + 0.5 V VOL1 Output Low Voltage VCC > 2.5V, IOL = 3.0mA 0.4 V VOH1 Output High Voltage VCC > 2.5V, IOH = -1.6mA VOL2 Output Low Voltage VCC > 1.8V, IOL = 150µA VOH2 Output High Voltage VCC > 1.8V, IOH = -100µA VCC - 0.8V V 0.2 VCC - 0.2V V V PIN CAPACITANCE(3) TA = 25˚C, f = 1.0MHz, VCC = +5.0V Symbol COUT CIN Test Conditions Output Capacitance (SO) ¯¯ , SCK, SI, ¯¯¯, ¯¯¯¯¯) Input Capacitance (CS WP HOLD Min Typ Max Units VOUT = 0V 8 pF VIN = 0V 8 pF Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5V, 25°C Doc. No. MD-1006 Rev. T 2 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25010, CAT25020, CAT25040 A.C. CHARACTERISTICS TA = -40°C to +125°C, unless otherwise specified.(1) VCC = 1.8V-5.5V Symbol VCC = 2.5V-5.5V TA= -40°C to +85°C Parameter Min. Max. Min. Max. Units fSCK Clock Frequency DC 5 DC 10 MHz tSU Data Setup Time 30 20 ns tH Data Hold Time 30 20 ns tWH SCK High Time 75 40 ns tWL SCK Low Time 75 40 ns tLZ ¯¯¯¯¯ to Output Low Z HOLD 50 25 ns tRI(2) tFI(2) Input Rise Time 2 2 µs Input Fall Time 2 2 µs tHD ¯¯¯¯¯ HOLD Setup Time 0 0 ns tCD ¯¯¯¯¯ HOLD Hold Time 10 10 ns tV Output Valid from Clock Low tHO Output Hold Time tDIS Output Disable Time 50 20 ns tHZ ¯¯¯¯¯ to Output High Z HOLD 100 25 ns tCS ¯¯ High Time CS 50 15 ns tCSS ¯¯ Setup Time CS 50 15 ns tCSH ¯¯ Hold Time CS 50 15 ns tWPS ¯¯¯ WP Setup Time 10 10 ns tWPH ¯¯¯ WP Hold Time 10 10 ns (4) tWC 75 0 Write Cycle Time 40 0 ns ns 5 5 ms Power-Up Timing(2)(3) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max. Units 1 1 ms ms Notes: (1) AC Test Conditions: Input Pulse Voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤ 10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; CL = 50pF (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. ¯¯ after a valid write sequence to the end of the internal write cycle. (4) tWC is the time from the rising edge of CS © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 PIN DESCRIPTION FUNCTIONAL DESCRIPTION SI: The serial data input pin accepts op-codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. The CAT25010/20/40 devices support the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8-bit instruction register. The instruction set and associated op-codes are listed in Table 1. SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock. Reading data stored in the CAT25010/20/40 is accom– plished by simply providing the READ command and an address. Writing to the CAT25010/20/40, in addition to a WRITE command, address and data, also requires enabling the device for writing by first setting certain bits in a Status Register, as will be explained later. SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAT25010/20/40. ¯¯ : The chip select input pin is used to enable/disable CS ¯¯ is high, the SO output the CAT25010/20/40. When CS is tri-stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication session between host and CAT25010/20/40 must be preceded by a high to low transition and concluded with a low to high ¯¯ input. transition of the CS ¯¯ input pin, the After a high to low transition on the CS CAT25010/20/40 will accept any one of the six instruction op-codes listed in Table 1 and will ignore all other possible 8-bit combinations. The communication protocol follows the timing from Figure 1. Table 1: Instruction Set (1) ¯¯¯: WP The write protect input pin will allow all write operations to the device when held high. When ¯¯¯ WP pin is tied low all write operations are inhibited. Instruction ¯¯¯¯¯: The ¯¯¯¯¯ HOLD HOLD input pin is used to pause trans– mission between host and CAT25010/20/40, without having to retransmit the entire sequence at a later ¯¯¯¯¯ must be taken low and to time. To pause, HOLD resume it must be taken back high, with the SCK input low during both transitions. When not used for pausing, the ¯¯¯¯¯ HOLD input should be tied to VCC, either directly or through a resistor. Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 X011 Read Data from Memory WRITE 0000 X010 Write Data to Memory Note: (1) X = 0 for CAT25010, CAT25020. X = A8 for CAT25040 Figure 1. Synchronous Data Timing tCS V IH CS VIL SCK VIH tWL tWH VIL tH tSU VIH SI tCSH tCSS VALID IN VIL tRI tFI tV SO VOH HI-Z tHO tDIS HI-Z VOL Note: Dashed Line = mode (1, 1) - - - - - - © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 4 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 STATUS REGISTER The Status Register, as shown in Table 2, contains a number of status and control bits. in a Write Enable state and when set to 0, the device is in a Write Disable state. The ¯¯¯¯ RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non-volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 3. The protected blocks then become read-only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is Table 2. Status Register 7 6 5 4 3 2 1 0 1 1 1 1 BP1 BP0 WEL ¯¯¯¯ RDY Table 3. Block Protection Bits Status Register Bits Array Address Protected Protection 0 None No Protection 0 1 CAT25010: 060-07F CAT25020: 0C0-0FF CAT25040: 180-1FF Quarter Array Protection 1 0 CAT25010: 040-07F CAT25020: 080-0FF CAT25040: 100-1FF Half Array Protection 1 1 CAT25010: 000-07F CAT25020: 000-0FF CAT25040: 000-1FF Full Array Protection BP1 BP0 0 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 WRITE OPERATIONS ¯¯ input high after the WREN instruction, to take the CS as otherwise the Write Enable Latch will not be properly set. WREN timing is illustrated in Figure 2. The WREN instruction must be sent prior any WRITE or WRSR instruction. The CAT25010/20/40 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of the memory location(s) to be written must be outside the protected area, as defined by BP0 and BP1 bits from the status register. The internal write enable latch is reset by sending the WRDI instruction as shown in Figure 3. Disabling write operations by resetting the WEL bit, will protect the device against inadvertent writes. Write Enable and Write Disable The internal Write Enable Latch and the corresponding Status Register WEL bit are set by sending the WREN instruction to the CAT25010/20/40. Care must be taken Figure 2. WREN Timing CS SCK SI 0 0 0 0 0 1 1 0 HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) - - - - - - Figure 3. WRDI Timing CS SCK SI SO 0 0 0 0 0 1 0 0 HIGH IMPEDANCE Note: Dashed Line = mode (1, 1) - - - - - - Doc. No. MD-1006 Rev. T 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25010, CAT25020, CAT25040 Page Write After sending the first data byte to the CAT25010/20/40, the host may continue sending data, up to a total of 16 bytes, according to timing shown in Figure 5. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will “roll over” to the first byte in the page, thus possibly overwriting previoualy loaded data. Following completion of the write cycle, the CAT25010/20/40 is automatically returned to the write disable state. Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 8-bit address and data as shown in Figure 4. For the CAT25040, bit 3 of the write instruction opcode contains A8 address bit. Internal programming will ¯¯ transition. During an start after the low to high CS internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The ¯¯¯¯ RDY bit will indicate if the internal write cycle is in progress ¯¯¯¯ high), or the the device is ready to accept (RDY ¯¯¯¯ low). commands (RDY Figure 4. Byte WRITE Timing CS 0 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 21 22 23 SCK BYTE ADDRESS OPCODE SI 0 0 0 0 X* 0 1 A7 0 DATA IN A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE SO Notes: Dashed Line = mode (1, 1) - - - - - * X = 0 for CAT25010, CAT25020. x = A8 for CAT25040 Figure 5. Page WRITE Timing CS 0 1 2 3 4 5 6 7 8 13 14 15 16-23 24-31 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1 SCK SI 0 0 0 0 X* DATA IN BYTE ADDRESS OPCODE 0 1 0 SO A7 A0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte N 0 7..1 HIGH IMPEDANCE Notes: Dashed Line = mode (1, 1) - - - - - * X = 0 for CAT25010, CAT25020. x = A8 for CAT25040 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 Write Protection When ¯¯¯ WP input is low all write operations to the memory array and Status Register are inhibited. ¯¯¯ WP ¯¯ is still low will interrupt a write to going low while CS the status register. If the internal write cycle has already been initiated, ¯¯¯ WP going low will have no effect on any write operation to the Status Register. The ¯¯¯ WP input timing is shown in Figure 7. Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 6. Only bits 2 and 3 can be written using the WRSR command. Figure 6. WRSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK OPCODE SI 0 0 0 0 0 DATA IN 0 0 3 MSB SO HIGH IMPEDANCE Note: Dashed Line = mode (1, 1) - - - - - - Figure 7. ¯¯¯ WP Timing t WPS t WPH CS SCK WP WP Note: Dashed Line = mode (1, 1) - - - - - - Doc. No. MD-1006 Rev. T 8 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25010, CAT25020, CAT25040 READ OPERATIONS Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT25010/20/40 will shift out the contents of the status register on the SO pin (Figure 9). The status register may be read at any time, including during an internal write cycle. Read from Memory Array To read from memory, the host sends a READ instruction followed by a 8-bit address (for the CAT25040, bit 3 of the read instruction opcode contains A8 address bit). After receiving the last address bit, the CAT25010/20/40 will respond by shifting out data on the SO pin (as shown in Figure 8). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking ¯¯ high. CS Figure 8. READ Timing CS 0 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20 21 22 SCK BYTE ADDRESS OPCODE SI 0 0 0 0 X* 0 1 1 A0 A7 DATA OUT HIGH IMPEDANCE SO D7 D6 D5 D4 D3 D2 D1 D0 MSB Notes: Dashed Line = mode (1, 1) - - - - - * X = 0 for CAT25010, CAT25020. X = A8 for CAT25040 Figure 9. RDSR Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 6 5 11 12 13 14 2 1 SCK OPCODE SI 0 0 0 0 0 DATA OUT SO HIGH IMPEDANCE 7 4 3 0 MSB Note: Dashed Line = mode (1, 1) - - - - - - © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 Hold Operation The ¯¯¯¯¯ HOLD input can be used to pause communication between host and CAT25010/20/40. To pause, ¯¯¯¯¯ HOLD must be taken low while SCK is low (Figure 10). During the hold condition the device must remain ¯¯ low). During the pause, the data output selected (CS pin (SO) is tri-stated (high impedance) and SI transitions are ignored. To resume communication, ¯¯¯¯¯ must be taken high while SCK is low. HOLD DESIGN CONSIDERATIONS ¯¯ pin must be brought low to After power up, the CS enter a ready state and receive an instruction. After a successful byte/page write or status register write, the ¯¯ input device goes into a write disable mode. The CS must be set high after the proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write cycle is ignored and programming is continued. Any invalid op-code will be ignored and the serial output pin (SO) will remain in the high impedance state. The CAT25010/20/40 devices incorporate Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power. The CAT25010/20/40 device powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued prior any writes to the device. ¯¯¯¯¯ Timing Figure 10. HOLD CS tCD tCD SCK tHD tHD HOLD tHZ HIGH IMPEDANCE SO tLZ Note: Dashed Line = mode (1, 1) - - - - - - Doc. No. MD-1006 Rev. T 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25010, CAT25020, CAT25040 PACKAGE OUTLINES DRAWING PDIP 8-Lead 300mils (L) (1)(2) SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 4.95 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 e PIN # 1 IDENTIFICATION MAX 2.54 BSC E1 6.10 eB 7.87 L 2.92 6.35 7.11 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MS-001 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 SOIC 8-Lead 150mils (V) (1)(2) SYMBOL E1 E MIN MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 e PIN # 1 IDENTIFICATION NOM 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MS-012. Doc. No. MD-1006 Rev. T 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25010, CAT25020, CAT25040 TSSOP 8-Lead (Y) (1)(2) b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.15 0.90 1.05 0.65 BSC L 1.00 REF L1 0.50 θ1 0° 0.60 0.75 8° e TOP VIEW D A2 A1 A c θ1 L1 SIDE VIEW L END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MO-153. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 TDFN 8-Pad 2 x 3mm (VP2) (1)(2) D e A b E2 E PIN#1 IDENTIFICATION A1 PIN#1 INDEX AREA D2 TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A2 0.45 0.55 0.65 A3 b 0.25 A2 A3 D 1.90 2.00 2.10 1.30 1.40 1.50 E 2.90 3.00 3.10 E2 1.20 1.30 1.40 e FRONT VIEW 0.30 D2 L BOTTOM VIEW 0.20 REF 0.20 L 050 TYP 0.20 0.30 0.40 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MO-229. Doc. No. MD-1006 Rev. T 14 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25010, CAT25020, CAT25040 MSOP 8-Lead 3 x 3mm (Z) (1)(2) SYMBOL MIN NOM MAX A E E1 1.10 A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 c 0.13 D 2.90 0.38 0.23 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 e L 0.65 BSC 0.40 0.60 L1 L2 θ 0.80 0.95 REF 0.25 BSC 0º 6º TOP VIEW D A A2 A1 DETAIL A e b c SIDE VIEW END VIEW θ L2 L L1 DETAIL A For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MO-187. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 15 Doc. No. MD-1006 Rev. T CAT25010, CAT25020, CAT25040 EXAMPLE OF ORDERING INFORMATION (1)(2) Prefix Device # Suffix CAT 25040 V Temperature Range I = Industrial (-40ºC to +85ºC) E = Extended (-40ºC to +125ºC) Company ID Product Number 25010: 1-Kb 25020: 2-Kb 25040: 4-Kb I L: V: Y: VP2: Z: Package PDIP SOIC, JEDEC TSSOP TDFN (2 x 3mm) (4) MSOP -G T3 Lead Finish G: NiPdAu Blank: Matte-Tin Tape & Reel T: Tape & Reel 3: 3000 units/Reel Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT25040VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). (4) For availabitily, please contact your nearest Catalyst Semiconductor Sales office. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 16 Doc. No. MD-1006 Rev. T REVISION HISTORY Date Rev. 10/13/05 N 12/09/05 O 03/21/06 P 06/30/06 Q 07/31/06 R 10/13/06 S Update Example of Ordering Information T Add Extended Temperature range Updated text format Update D.C. Operating Characteristics table for Extended Temperature range Update A.C. Characteristics table for Extended Temperature range Add MD- to document number 9/14/07 Comments Update D.C. Operating Characteristics Update Ordering Information Update Pin Configuration Update D.C. Operating Characteristics Update Pin Impedance Characteristics Update Figure 2, 3, 4, 6, 8 Add Tape and Reel Update Ordering Information Update D.C. Operating Characteristics Update A.C. Characteristics Update Pin Description Update Features Update Description Update A.C. Characteristics Update Package Marking Remove Tape and Reel Update Example of Ordering Information Add TDFN and MSOP packages Update Package Marking Update Ordering Information Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. 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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: MD-1006 Revision: T Issue date: 9/14/07