CAT521WI-T2

Not Recommended for New Design CAT521 Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications FEATURES 8-bit DPP configured as a programmable voltage source in DAC-like applications Buffered wiper output Non-volatile NVRAM memory wiper storage Output voltage range includes both supply rails 1 LSB accuracy, high resolution Serial Microwire-like interface Single supply operation: 2.7V – 5.5V Setting read-back without effecting outputs DESCRIPTION The CAT521 is a 8-bit digitally-programmable potentiometer (DPP™) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. The programmable DPP has an output voltage range which includes both supply rails. The wiper is buffered by a rail to rail op amp. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically reinstated when power is returned. The wiper can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP’s output. The CAT521 is controlled with a simple 3-wire, Microwire like serial interface. A Chip Select pin allows several devices to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the CAT521 Tri¯¯¯¯ Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. The CAT521 is available in 0°C to 70°C commercial and -40°C to 85°C industrial operating temperature ranges. Both 14-pin plastic DIP and surface mount packages are available. For Ordering Information details, see page 12. APPLICATIONS Automated product calibration Remote control adjustment of equipment Offset, gain and zero adjustments in selfcalibrating and adaptive control systems Tamper-proof calibrations DAC (with memory) substitute PIN CONFIGURATION PDIP 14-Lead (L) SOIC 14-Lead (W) VDD CLK RDY/¯¯¯¯ BSY CS DI DO PROG 1 2 3 14 13 12 VREFH NC VOUT NC NC VREFL GND 4 CAT521 11 5 6 7 10 8 8 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 1 Doc. No. MD-2003 Rev. I CAT521 Not Recommended for New Design FUNCTIONAL DIAGRAM VDD 1 RDY/BSY 3 VREFH 14 PROG 7 PROGRAM CONTROL WIPER CONTROL REGISTERS AND NVRAM 24kΩ 24kΩ DI CLK CS 5 2 4 SERIAL CONTROL 24kΩ 24kΩ + – 12 VOUT SERIAL DATA OUTPUT REGISTER 6 DO CAT521 8 GND 9 VREFL Doc. No. MD-2003 Rev. I 2 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT521 ABSOLUTE MAXIMUM RATINGS Parameters Supply Voltage* VDD to GND Inputs CLK to GND CS to GND DI to GND ¯¯¯¯ RDY/BSY to GND PROG to GND VREFH to GND VREFL to GND Ratings -0.5 to +7 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 Units V Parameters Outputs D0 to GND VOUT 1– 4 to GND Operating Ambient Temperature Commercial (‘C’ or Blank suffix) Industrial (‘I’ suffix) Junction Temperature Storage Temperature Lead Soldering (10 sec max) Ratings -0.5 to VDD +0.5 -0.5 to VDD +0.5 0 to +70 -40 to +85 +150 -65 to +150 +300 Units V V °C °C °C °C °C V V V V V V V RELIABILITY CHARACTERISTICS Symbol VZAP(2) ILTH(2)(3) Parameter ESD Susceptibility Latch-Up Test Method MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 2000 100 Max Units V mA POWER SUPPLY Symbol IDD1 IDD2 VDD Parameter Supply Current (Read) Supply Current (Write) Operating Voltage Range Conditions Normal Operating Programming, VDD = 5V VDD = 3V Min — — — 2.7 Typ 400 1600 1000 — Max 600 2500 1600 5.5 Units µA µA µA V LOGIC INPUTS Symbol IIH IIL VIH VIL Parameter Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage Conditions VIN = VDD VIN = 0V Min — — 2 0 Typ — — — — Max 10 -10 VDD 0.8 Units µA µA V V LOGIC OUTPUTS Symbol VOH VIL Parameter High Level Output Voltage Low Level Output Voltage Conditions IOH = -40µA IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V Min VDD -0.3 — — Typ — — — Max — 0.4 0.4 Units V V V Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 3 Doc. No. MD-2003 Rev. I CAT521 Not Recommended for New Design POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Potentiometer Resistance RPOT to RPOT Match Pot Resistance Tolerance Voltage on VREFH pin Voltage on VREFL pin Resolution INL DNL ROUT IOUT TCRPOT CH/CL Integral Linearity Error Differential Linearity Error Buffer Output Resistance Buffer Output Current TC of Pot Resistance Potentiometer Capacitances 300 8/8 2.7 0 0.4 0.5 0.25 1 0.5 10 3 Conditions See note 3 — Min Typ 24 ±0.5 ±1 ±20 VDD VDD - 2.7 Max Units kΩ % % V V % LSB LSB Ω mA ppm/ºC pF AC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Analog tDS DPP Settling Time to 1 LSB CLOAD = 10pF, VDD = +5V CLOAD = 10pF, VDD = +3V — — 3 6 10 10 µs µs Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL = 100pF (1) Parameter Conditions Min 150 100 0 50 50 — — — — — 150 700 500 300 DC Typ — — — — — — — 400 400 4 — — — — — Max — — — — — 150 150 — — 5 — — — — 1 Units ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz Notes: (1) All timing measurements are defined at the point of signal crossing VDD / 2. (2) These parameters are periodically sampled and are not 100% tested. (3) The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ +20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value. 4 Doc. No. MD-2003 Rev. I © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT521 A.C. TIMING DIAGRAM to 1 2 3 4 5 tCLK H CLK tCSS CS tCLK L t CSH tCSMIN tDIS DI tDIH tLZ DO t DO0 tHZ tDO1 PROG t PS tPROG RDY/BSY tBUSY to 1 2 3 4 5 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 5 Doc. No. MD-2003 Rev. I CAT521 Not Recommended for New Design PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name VDD CLK ¯¯¯¯ RDY/BSY CS DI DO PROG GND VREFL NC NC VOUT NC VREFH Function Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin EEPROM Programming Enable Input Power supply ground Minimum DAC output voltage No Connect No Connect DPP output No Connect Maximum DPP 1 output voltage DPP OUTPUT VOUT A0 1 A1 0 DPP addressing is as follows: DEVICE OPERATION The CAT521 is a single 8-bit configured digitally programmable potentiometer (DPP™) whose output can be programmed to any one of 256 individual voltage steps. Once programmed, the output setting is retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPP returns to the setting stored in non-volatile memory. The DPP can be written to and read from without effecting the output voltage during the read or write cycle. The output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT521 employs a 3 wire, Microwire-like serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired Doc. No. MD-2003 Rev. I IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT521’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control register will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30ns to 90ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT521 clock controls both data flow in and out of the device and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. 6 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT521 No clock is necessary upon system power-up. The CAT521 internal power-on reset circuitry loads data from non-volatile memory to the DPP without using the external clock. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control register. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. VREF VREF, the voltage applied between pins VREFH & VREFL, sets the DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH & VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. ¯¯¯¯¯ READY/BUSY When saving data to non-volatile memory, the ¯¯¯¯ Ready/Busy ouput (RDY/BSY ) signals the start and duration of the erase/write cycle. Upon receiving a ¯¯¯¯ command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT521 will ignore any data appearing at DI and no data will be output on DO. ¯¯¯¯ RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, Figure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 ¯¯¯¯ RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT Data is output serially by the CAT521, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 521s to share a single serial data line and simplifies interfacing multiple 521s to a microprocessor. WRITING TO MEMORY Programming the CAT521’s non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. The CAT521 nonvolatile memory cells will endure over 1,000,000 write cycles and will retain data for a minimum of 100 years without being refreshed. 10 11 12 N N+1 N+2 CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 D7 PROG RDY/BSY DPP OUTPUT CURRENT DPP VALUE NON-VOL ATILE NEW DPP VALUE VOLATILE NEW DPP VALUE NON-VOL ATILE © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 7 Doc. No. MD-2003 Rev. I CAT521 Not Recommended for New Design READING DATA Each time data is transferred into the DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP’s output. This feature allows µPs to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory's setting is reloaded into the DPP wiper control register. Since this value is the same as that which had been there previously no change in the DPP’s output is noticed. Had the value held in the control register been different from that stored in nonvolatile memory then a change would occur at the read cycle’s conclusion. TEMPORARILY CHANGE OUTPUT The CAT521 allows temporary changes in the DPP’s output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DPP settings may be changed as many times as required. The temporary setting remains in effect long as CS remains high. When CS returns low the DPP will return to the output value stored in non-volatile memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP wiper control register prior to programming. This is because the CAT521’s internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. Figure 2. Reading from Memory to 1 2 3 4 5 6 7 8 9 10 11 12 Figure 3. Temporary Change in Output to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS CS NEW DPP DATA 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI 1 A0 A1 CURRENT DPP DATA DI CURRENT DPP DATA D6 D7 DO D0 D1 D2 D3 D4 D5 DO D0 D1 D2 D3 D4 D5 D6 D7 PROG PROG RDY/BSY RDY/BSY DPP OUTPUT CURRENT DPP VALUE NON-VOL ATILE DPP OUTPUT CURRENT DPP VALUE NON-VOL ATILE NEW DPP VALUE VOLATILE CURRENT DPP VALUE NON-VOL ATILE Doc. No. MD-2003 Rev. I 8 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT521 APPLICATION CIRCUITS +5V VI RI +15V RF DPP INPUT DPP OUTPUT VDPP = MSB LSB CODE x (VFS - VZERO + VZERO ) 255 ANALOG OUTPUT VFS = 0.99VREF VREF = 5V RI = RF GND VREFL VOUT = VDPP ( RI + RF ) - VI R F RI For R I = RF VOUT = 2VDPP - VI +5V RI +15V GND VREFL R VOUT = (1 + F ) VDPP RI Amplified DPP Output VDD CONTROL & DATA CAT521 GND VREFL Digitally Controlled Voltage Reference © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice + CONTROL & DATA CAT521 – VDD VREFH -15V VREFH + -15V RF CONTROL & DATA CAT521 VDPP – OP 07 OP 07 VDD VOUT 1111 1000 0111 0000 0000 1111 0000 1111 0001 0000 VZERO = 0.01VREF 255 × 0.98VREF + 0.01VREF = 0.990 VREF 255 128 × 0.98VREF + 0.01VREF = 0.502VREF 255 127 × 0.98VREF + 0.01VREF = 0.498 VREF 255 1 × 0.98VREF + 0.01VREF = 0.014 VREF 255 0 × 0.98VREF + 0.01VREF = 0.010 VREF 255 VOUT = +4.90V VOUT = +0.02V VOUT = -0 .02V VOUT = -4.86V VOUT = -4.90V Bipolar DPP Output V+ I > 2mA VOUT VREF = 5.00V VDD CONTROL & DATA VREFH LT 1029 CAT521 GND VREFL Digitally Trimmed Voltage Reference 28 - 32V 15kΩ 10µF 1N5231B 5.1V 10kΩ + – LM 324 MPT3055EL OUTPUT 1.00kΩ 4.02kΩ 10µF 35V 0 - 25V @ 1A 9 Doc. No. MD-2003 Rev. I CAT521 Not Recommended for New Design PACKAGE OUTLINE DRAWINGS PDIP 14-Lead (L)(1)(2) SYMBOL MIN NOM MAX A A1 A2 E1 3.56 0.38 2.92 0.36 1.15 0.21 18.67 7.62 6.10 7.88 2.99 3.30 3.30 0.45 1.52 0.26 19.05 7.87 6.35 2.54 BSC 5.33 4.95 0.55 1.77 0.35 19.68 8.25 7.11 10.92 3.81 b b1 c D E E1 e eB L D TOP VIEW E A2 A c A1 L e b1 b eB SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-001. Doc. No. MD-2003 Rev. I 10 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT521 SOIC 14-Lead (W)(1)(2) SYMBOL MIN NOM MAX A A1 b c E1 E 1.35 0.10 0.33 0.19 8.55 5.80 3.80 0.25 0.40 0º 8.65 6.00 3.90 1.27 BSC 1.75 0.25 0.51 0.25 8.75 6.20 4.00 0.50 1.27 8º D E E1 e h L θ PIN#1 IDENTIFICATION TOP VIEW D h A θ e b A1 L c SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 11 Doc. No. MD-2003 Rev. I CAT521 Not Recommended for New Design EXAMPLE OF ORDERING INFORMATION Prefix CAT Optional Company ID Device # Suffix 521 W I Temperature Range I = Industrial (-40ºC to 85ºC) - T2 Tape & Reel T2: 2000/Reel Product Number 521 Package L: PDIP W: SOIC Notes: (1) (2) (3) All packages are RoHS compliant (Lead-free, Halogen-free). Standard lead finish is Matte-Tin. The device used in the above example is a CAT521WI-T2 (SOIC, Industrial Temperature, Tape & Reel). ORDERING INFORMATION CAT521WI CAT521LI Doc. No. MD-2003 Rev. I 12 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT521 REVISION HISTORY Date 16-Mar-04 12-Jul-04 Revision E F Description Updated Potentiometer Characteristics Updated Functional Diagram Updated Potentiometer Characteristics Added Note 3 under Potentiometer/AC Characteristics tables Updated Ordering Information Added MD- to document number Add Package Outline Drawings Add “Not Recommended for New Design” to the top of all pages Change logo and fine print to ON Semiconductor 26-Jul-07 15-Jul-08 21-Nov-08 G H I ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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