CAT93C86P

H CAT93C46/56/57/66/86 EE GEN FR ALO 1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM LE A D F R E ETM FEATURES ■ High speed operation: ■ Power-up inadvertant write protection ■ 1,000,000 Program/erase cycles – 93C46/56/57/66: 1MHz – 93C86: 3MHz ■ 100 year data retention ■ Low power CMOS technology ■ Commercial, industrial and automotive ■ 1.8 to 6.0 volt operation temperature ranges ■ Selectable x8 or x16 memory organization ■ Sequential read (except CAT93C46) ■ Self-timed write cycle with auto-clear ■ Program enable (PE) pin (CAT93C86 only) ■ Hardware and software write protection ■ “Green” package option available DESCRIPTION CMOS EEPROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and have a data retention of 100 years. The devices are available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8pad TDFN packages. The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit Serial EEPROM memory devices which are configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46/56/ 57/66/86 are manufactured using Catalyst’s advanced PIN CONFIGURATION CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC (PE*) VCC NC (PE*) ORG CS SK GND *Only For 93C86 1 2 3 4 8 7 6 5 ORG GND DO DI CS CS SK DI DO 1 2 3 4 8 7 6 5 VCC CS NC (PE*) SK ORG DI GND DO 1 2 3 4 8 7 6 5 VCC NC (PE*) ORG GND ** TSSOP (U/Y) package only available for 93C46/56/57/66 PIN FUNCTIONS Pin Name TSSOP Package (U,Y) SOIC Package (J,W) SOIC Package (S,V) SOIC Package (K,X) DIP Package (P, L) VCC Clock Input DI Serial Data Input DO Serial Data Output VCC +1.8 to 6.0V Power Supply GND Ground ORG Memory Organization NC No Connection PE* Program Enable Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. © 2003 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice. 8 7 DI 3 4 6 5 DO VCC 8 NC 7 GND ORG 6 Chip Select SK 1 2 GND 5 ORG MEMORY ARRAY ORGANIZATION VCC NC ORG GND TDFN Package (RD4, ZD4) BLOCK DIAGRAM Function CS SK ADDRESS DECODER 1 CS CAT93C46 CAT93C56 CAT93C66 2 SK 3 DI 4 DO Bottom View DATA REGISTER OUTPUT BUFFER DI CS PE* SK MODE DECODE LOGIC CLOCK GENERATOR DO Doc. No. 1023, Rev. J 93C46/56/57/66/86 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias .................. -55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ........................ -65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............. -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min NEND(3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR(3) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts Latch-Up JEDEC Standard 17 100 mA ILTH (3)(4) Typ Max Units D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Symbol Parameter Test Conditions ICC1 Power Supply Current (Operating Write) ICC2 Min Typ Max Units fSK = 1MHz VCC = 5.0V 3 mA Power Supply Current (Operating Read) fSK = 1MHz VCC = 5.0V 500 µA ISB1 Power Supply Current (Standby) (x8 Mode) CS = 0V ORG=GND 10 µA ISB2(5) Power Supply Current (Standby) (x16Mode) CS=0V ORG=Float or VCC 0 µA ILI Input Leakage Current VIN = 0V to VCC 1 µA ILO Output Leakage Current (Including ORG pin) VOUT = 0V to VCC, CS = 0V 1 µA VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V VIH2 Input High Voltage 4.8V ≤ VCC < 4.5V VCC x 0.7 VCC+1 V VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V IOL = 2.1mA 0.4 V VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V IOH = -400µA VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V IOL = 1mA VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V IOH = -100µA 2.4 V 0.2 VCC - 0.2 V V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Standby Current (ISB2)=0µA (