CAT9554AWI-G

CAT9554, CAT9554A 8-bit I²C and SMBus I/O Port with Interrupt FEATURES 400kHz I²C bus compatible 2.3V to 5.5V operation Low stand-by current 5V tolerant I/Os 8 I/O pins that default to inputs at power-up High drive capability Individual I/O configuration Polarity inversion register Active low interrupt output Internal power-on reset No glitch on power-up Noise filter on SDA/SCL inputs Cascadable up to 8 devices Industrial temperature range RoHS-compliant 16-lead SOIC and TSSOP, and 16-pad TQFN (4 x 4mm) packages Any of the eight I/Os can be configured as an input or output by writing to the configuration register. The system master can invert the CAT9554/9554A input data by writing to the active-high polarity inversion register. The CAT9554/9554A features an active low interrupt output which indicates to the system master that an input state has changed. The device’s extended addressing capability allows up to 8 devices to share the same bus. The CAT9554A is identical to the CAT9554 except the fixed part of the I²C slave address is different. This allows up to 16 of devices (eight CAT9554 and eight CAT9554A) to be connected on the same bus. For Ordering Information details, see page 15. (1) DESCRIPTION The CAT9554 and CAT9554A are CMOS devices that provide 8-bit parallel input/output port expansion for I²C and SMBus compatible applications. These I/O expanders provide a simple solution in applications where additional I/Os are needed: sensors, power switches, LEDs, pushbuttons, and fans. The CAT9554/9554A consist of an input port register, an output port register, a configuration register, a polarity inversion register and an I²C/SMBuscompatible serial interface. APPLICATIONS White goods (dishwashers, washing machines) Handheld devices (cell phones, PDAs, digital cameras) Data Communications (routers, hubs and servers) BLOCK DIAGRAM A0 A1 A2 SCL SDA (1) I/O0 I/O1 8-BIT INPUT FILTER I2C/SMBUS CONTROL WRITE pulse READ pulse INPUT/ OUTPUT PORTS I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 LP FILTER INT VCC VCC VSS POWER-ON RESET Notes: (1) All I/Os are set to inputs at RESET. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 1 Doc. No. MD-9002, Rev. F CAT9554, CAT9554A PIN CONFIGURATION SOIC (W), TSSOP (Y) A0 1 A1 2 A2 3 I/O0 4 I/O1 5 I/O2 6 I/O3 7 VSS 8 16 VCC 15 SDA 14 SCL 13 INT 12 I/O7 11 TQFN 4 x 4mm (HV4) (Top View) A1 16 A2 I/O0 I/O1 I/O2 1 2 3 4 5 6 7 8 A0 15 VCC SDA 14 13 12 SCL 11 INT 10 I/O7 9 I/O6 I/O6 10 I/O5 9 I/O4 I/O3 VSS I/O4 I/O5 PIN DESCRIPTION SOIC / TSSOP 1 2 3 4-7 8 9-12 13 14 15 16 TQFN 15 16 1 2-5 6 7-10 11 12 13 14 Pin Name A0 A1 A2 I/O0-3 VSS I/O4-7 ¯¯¯ INT SCL SDA VCC Function Address Input 0 Address Input 1 Address Input 2 Input/Output Port 0 to Input/Output Port 3 Ground Input/Output Port 4 to Input/Output Port 7 Interrupt Output (open drain) Serial Clock Serial Data Power Supply ABSOLUTE MAXIMUM RATINGS (1) Parameters VCC with Respect to Ground Voltage on Any Pin with Respect to Ground DC Current on I/O0 to I/O7 DC Input Current VCC Supply Current VSS Supply Current Package Power Dissipation Capability (TA = 25°C) Junction Temperature Storage Temperature Ratings -0.5 to +6.5 -0.5 to +5.5 ±50 ±20 85 100 1.0 +150 -65 to +150 Units V V mA mA mA mA W ºC ºC RELIABILITY CHARACTERISTICS Symbol VZAP(2) ILTH (2)(3) Parameter ESD Susceptibility Latch-up Reference Test Method JEDEC Standard JESD 22 JEDEC Standard 17 Min 2000 100 Units Volts mA Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC +1V. Doc. No. MD-9002 Rev. F 2 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9554, CAT9554A D.C. OPERATING CHARACTERISTICS VCC = 2.3 to 5.5V; TA = -40°C to +85°C, unless otherwise specified. Symbol Supplies VCC ICC Istbl Istbh VPOR VIL (1) VIH (1) Parameter Supply voltage Supply current Standby current Standby current Power-on reset voltage Low level input voltage Conditions Min 2.3 Typ — 104 550 0.25 1.5 — — — — — — — — — — — 10 13 17 24 14 19 — — — — — — — — — — Max 5.5 175 700 1 1.65 0.3 x VCC 5.5 — +1 6 8 0.8 5.5 1 0.8 5.5 — — — — — — — — — — — — 1 -100 5 8 Unit V µA µA µA V V V mA µA pF pF V V µA V V mA mA mA mA mA mA V V V V V V µA µA pF pF Operating mode; VCC = 5.5V; no load; fSCL = 100kHz Standby mode; VCC = 5.5V; no load; VI = VSS; fSCL = 0kHz; I/O = inputs Standby mode; VCC = 5.5V; no load; VI = VCC; fSCL = 0kHz; I/O = inputs No load; VI = VCC or VSS — — — — -0.5 0.7 x VCC SCL, SDA, ¯¯¯ INT High level input voltage Low level output IOL current IL Leakage current (2) CI Input capacitance CO (2) Output capacitance A0, A1, A2 VIL (1) Low level input voltage (1) VIH High level input voltage ILI Input leakage current I/Os VIL Low level input voltage VIH High level input voltage VOL = 0.4V VI = VCC or VSS VI = VSS VO = VSS 3 -1 — — -0.5 2.0 -1 -0.5 2.0 8 10 8 10 8 10 1.8 1.7 2.6 2.5 4.1 4.0 — — — — IOL Low level output current VOH High level output voltage IIH IIL CI (2) CO (2) Input leakage current Input leakage current Input capacitance Output capacitance VOL = 0.5V; VCC = 2.3V (3) VOL = 0.7 V; VCC = 2.3 V (3) VOL = 0.5 V; VCC = 4.5 V (3) VOL = 0.7 V; VCC = 4.5 V (3) VOL = 0.5 V; VCC = 3.0 V (3) VOL = 0.7 V; VCC = 3.0 V (3) IOH = -8 mA; VCC = 2.3 V (4) IOH = -10 mA; VCC = 2.3 V (4) IOH = - 8 mA; VCC = 3.0 V (4) IOH = -10 mA; VCC = 3.0 V (4) IOH = -8 mA; VCC = 4.75 V (4) IOH = -10 mA; VCC = 4.75 V (4) VCC = 3.6V; VI = VCC VCC = 5.5V; VI = VSS Notes: (1) VIL min and VIH max are reference values only and are not tested. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (3) The total current sunk by all I/Os must be limited to 100mA and each I/O limited to 25mA maximum. (4) The total current sourced by all I/Os must be limited to 85mA. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 3 Doc. No. MD-9002, Rev. F CAT9554, CAT9554A A.C. CHARACTERISTICS VCC = 2.3V to 5.5V; TA = -40°C to +85°C, unless otherwise specified. (1) Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF (2) (2) Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs Parameter Output Data Valid Input Data Setup Time Input Data Hold Time Interrupt Valid Interrupt Reset Standard I2C Min 4 4.7 4 4.7 0 250 1000 300 4 4.7 3.5 100 100 Max 100 Fast I2C Min 0.6 1.3 0.6 0.6 0 100 300 300 0.6 1.3 0.9 50 100 Min Max 200 100 1 4 4 Max 400 Units kHz µs µs µs µs µs ns ns ns µs µs µs ns ns Units ns ns µs µs µs tSU:STO tBUF (2) tAA tDH Ti (2) Symbol Port Timing tPV tPS tPH tIV tIR Interrupt Timing Notes: (1) Test conditions according to "AC Test Conditions" table. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. Doc. No. MD-9002 Rev. F 4 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9554, CAT9554A A.C. TEST CONDITIONS Input Rise and Fall time CMOS Input Voltages CMOS Input Reference Voltages TTL Input Voltages TTL Input Reference Voltages Output Reference Voltages Output Load: SDA, ¯¯¯ INT Output Load: I/Os tF tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO ≤ 10ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC 0.4V to 2.4V 0.8V, 2.0V 0.5VCC Current Souce IOL = 3mA; CL = 100pF Current Source: IOL/IOH = 10mA; CL = 50pF tHIGH tLOW tR SDA IN tAA SDA OUT tDH tBUF Figure 1. I²C Serial Interface Timing © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 5 Doc. No. MD-9002, Rev. F CAT9554, CAT9554A PIN DESCRIPTION SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull-up resistor if it is driven by an open drain output. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A pullup resistor must be connected from SDA line to VCC. The value of the pull-up resistor, RP, can be calculated based on minimum and maximum values from Figure 2 and Figure 3 (see Note). A0, A1, A2: Device Address Inputs These inputs are used for extended addressing capability. The A0, A1, A2 pins should be hardwired to VCC or VSS. When hardwired, up to eight CAT9554/9554As may be addressed on a single bus system. The levels on these inputs are compared with corresponding bits, A2, A1, A0, from the slave address byte. I/O0 to I/O7: Input / Output Ports Any of these pins may be configured as input or output. The simplified schematic of I/O0 to I/O7 is shown in Figure 4. When an I/O is configured as an input, the Q1 and Q2 output transistors are off creating a high impedance input with a weak pull-up resistor (typical 100kΩ). If the I/O pin is configured as an output, the push-pull output stage is enabled. Care should be taken if an external voltage is applied to an I/O pin configured as an output due to the low impedance paths that exist between the pin and either VCC or VSS. IOL = 3mA @ VOLmax 2.5 2 1.5 1 0.5 0 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 8.00 Fast Mode I²C Bus / tr max - 300ns 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 50 100 150 200 250 300 350 400 VCC (V) RPmax (KΩ) RPmin (KΩ) CBUS (pF) Figure 2. Minimum RP Value versus Supply Voltage Figure 3. Maximum RP Value versus Bus Capacitance Note: According to the Fast Mode I²C bus specification, for bus capacitance up to 200pF, the pull up device can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax = 3mA) or a switched resistor circuit. Doc. No. MD-9002 Rev. F 6 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9554, CAT9554A ¯¯¯: Interrupt Output INT The open-drain interrupt output is activated when one of the port pins configured as an input changes state (differs from the corresponding input port register bit state). The interrupt is deactivated when the input Data from Shift Register Data from Shift Register returns to its previous state or the input port register is read. Changing an I/O from an output to an input may cause a false interrupt if the state of the pin does not match the contents of the input port register. Configuration Register D FF Q Output Port Register Data VCC Q1 100kΩ Write Configuration Pulse CK Q D FF Q Write Pulse I/O 0 to I/O 7 CK Q Q2 Output Port Register Input Port Register VSS Input Port Register Data D LATCH Read Pulse CK Q Q To INT Data from Shift Register Write Polarity Register D FF CK Q Polarity Register Data Q Polarity Inversion Register Figure 4. Simplified Schematic of I/O0 to I/O7 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 7 Doc. No. MD-9002, Rev. F CAT9554, CAT9554A FUNCTIONAL DESCRIPTION The CAT9554 and CAT9554A general purpose input/ output (GPIO) peripherals provide up to eight I/O ports, controlled through an I²C compatible serial interface The CAT9554/54A support the I²C Bus data transmission protocol. This I²C Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT9554/9554A operate as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. I²C BUS PROTOCOL The features of the I²C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 5). START AND STOP CONDITIONS The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SCL SDA when SCL is HIGH. The CAT9554/9554A monitors the SDA and SCL lines and will not respond until this condition is met. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING After the bus Master sends a START condition, a slave address byte is required to enable the CAT9554/9554A for a read or write operation. The four most significant bits of the slave address are fixed as binary 0100 for the CAT9554 (Figure 6) and as 0111 for the CAT9554A (Figure 7). The CAT9554/9554A uses the next three bits as address bits. The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The 8th bit following the 7¯¯ bit slave address is the R/W bit that specifies whether a read or write operation is to be performed. When this bit is set to “1”, a read operation is initiated, and when set to “0”, a write operation is selected. Following the START condition and the slave address byte, the CAT9554/9554A monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT9554/9554A then performs a read or a write ¯¯ operation depending on the state of the R/W bit. SDA START CONDITION STOP CONDITION Figure 5. START/STOP Condition SLAVE ADDRESS 0 1 0 0 A2 A1 A0 R/W 0 1 SLAVE ADDRESS 1 1 A2 A1 A0 R/W FIXED PROGRAMMABLE HARDWARE SELECTABLE FIXED PROGRAMMABLE HARDWARE SELECTABLE Figure 6. CAT9554 Slave Address Figure 7. CAT9554A Slave Address Doc. No. MD-9002 Rev. F 8 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9554, CAT9554A ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 5). The CAT9554/9554A respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT9554/9554A begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9554/9554A will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a STOP condition to return the CAT9554/9554A to the standby power mode and place the device in a known state. REGISTERS AND BUS TRANSACTIONS The CAT9554/9554A consist of an input port register, an output port register, a polarity inversion register and a configuration register. Table 1 shows the register address table. Tables 2 to 5 list Register 0 through Register 3 information. Table 1. Register Command Byte Command (hex) 0x00 0x01 0x02 0x03 Protocol Read byte Read/write byte Read/write byte Read/write byte Function Input port register Output port register Polarity inversion register Configuration register The command byte is the first byte to follow the device address byte during a write/read bus transaction. The register command byte acts as a pointer to determine which register will be written or read. The input port register is a read only port. It reflects the incoming logic levels of the I/O pins, regardless of whether the pin is defined as an input or an output by the configuration register. Writes to the input port register are ignored. Table 2. Register 0 – Input Port Register bit default I7 1 I6 1 I5 1 I4 1 I3 1 I2 1 I1 1 I0 1 Table 3. Register 1 – Output Port Register bit default O7 1 O6 1 O5 1 O4 1 O3 1 O2 1 O1 1 O0 1 Table 4. Register 2 – Polarity Inversion Register bit default N7 0 N6 0 N5 0 N4 0 N3 0 N2 0 N1 0 N0 0 Table 5. Register 3 – Configuration Register bit default C7 1 C6 1 C5 1 C4 1 C3 1 C2 1 C1 1 C0 1 BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START 1 8 9 BUS RELEASE DELAY (RECEIVER) ACK SETUP ACK DELAY Figure 8. Acknowledge Timing © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 9 Doc. No. MD-9002, Rev. F CAT9554, CAT9554A The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Bit values in this register have no effect on I/O pins defined as inputs. Reads from the output port register reflect the value that is in the flip-flop controlling the output, not the actual I/O pin value. The polarity inversion register allows the user to invert the polarity of the input port register data. If a bit in this register is set (“1”) the corresponding input port data is inverted. If a bit in the polarity inversion register is cleared (“0”), the original input port polarity is retained. The configuration register sets the directions of the ports. Set the bit in the configuration register to enable the corresponding port pin as an input with a high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At power-up, the I/Os are configured as inputs with a weak pull-up resistor to VCC. Data is transmitted to the CAT9554/9554A registers using the write mode shown in Figure 9 and Figure 10. The CAT9554/9554A registers are read according to the timing diagrams shown in Figure 11 and Figure 12. Once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte will be sent. SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 1 0 0 A2 A1 A0 R/W 0 A 0 0 command byte 0 0 0 0 0 1 A data to port DATA 1 acknowledge from slave A P stop condition start condition WRITE TO PORT DATA OUT FROM PO RT acknowledge from slave acknowledge from slave DATA 1 VALID tpv Figure 9. Write to Output Port Register SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 1 0 0 A2 A1 A0 R/W 0 A 0 0 command byte 0 0 0 0 1 1/0 A data to register DATA 1 acknowledge from slave A P stop condition start condition WRITE TO REGISTER acknowledge from slave acknowledge from slave Figure 10. Write to Configuration or Polarity Inversion Register Doc. No. MD-9002 Rev. F 10 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9554, CAT9554A POWER-ON RESET OPERATION When the power supply is applied to VCC pin, an internal power-on reset pulse holds the CAT9554/9554A in a reset state until VCC reaches VPOR level. At this point, the reset condition is released and the internal state machine and the CAT9554/9554A registers are initialized to their default state. slave address S 0 1 0 0 A2 A1 A0 R/W 0 A COMMAND BYTE acknowledge from slave A S 0 1 slave address 0 0 R/W acknowledge from master data from register DATA first byte A A2 A1 A0 1 A acknowledge from slave acknowledge from slave At this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter no acknowledge from master data from register DATA last byte NA P Figure 11. Read from Register SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 1 0 0 A2 A1 A0 R/W 1 A data from port DATA 1 acknowledge from master A data from port DATA 4 no acknowledge from master NA P stop condition start condition READ FROM PORT DATA INTO PORT acknowledge from slave DATA 1 DATA 2 DATA 3 DATA 4 tPH tPS INT tIV tIR Figure 12. Read Input Port Register © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 11 Doc. No. MD-9002, Rev. F CAT9554, CAT9554A PACKAGE OUTLINE DRAWINGS SOIC 16-Lead 150mils (W) (1) (2) SYMBOL MIN NOM MAX A A1 b c E1 E 1.35 0.10 0.33 0.19 9.80 5.80 3.80 0.25 0.40 0º 9.90 6.00 3.90 1.27 BSC 1.75 0.25 0.51 0.25 10.00 6.20 4.00 0.50 1.27 8º D E E1 e h L θ PIN#1 IDENTIFICATION TOP VIEW D h A θ e b A1 L c SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012 Doc. No. MD-9002 Rev. F 12 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9554, CAT9554A TSSOP 16-Lead 4.4mm (Y) (1) (2) b SYMBOL MIN NOM MAX A A1 A2 b E1 E 1.10 0.05 0.85 0.19 0.13 4.90 6.30 4.30 0.65 BSC 1.00 REF 0.45 0° 0.75 8° 0.15 0.95 0.30 0.20 5.10 6.50 4.50 c D E E1 e L L1 θ1 PIN#1 IDENTIFICATION TOP VIEW e D c A2 A θ1 A1 L SIDE VIEW END VIEW L1 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-153. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 13 Doc. No. MD-9002, Rev. F CAT9554, CAT9554A TQFN 16-Pad 4 x 4mm (HV4) (1) (2) D A DETAIL A E E2 PIN#1 ID PIN#1 INDEX AREA A1 SIDE VIEW D2 TOP VIEW BOTTOM VIEW SYMBOL MIN NOM MAX b e A A1 A3 b D D2 E E2 e L 0.70 0.00 0.25 3.90 2.00 3.90 2.00 0.45 0.75 0.02 0.20 REF 0.30 4.00 – 4.00 – 0.65 BSC – 0.80 0.05 0.35 4.10 2.25 4.10 2.25 A L DETAIL A 0.65 A1 FRONT VIEW A3 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-220. Doc. No. MD-9002 Rev. F 14 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9554, CAT9554A EXAMPLE OF ORDERING INFORMATION (1) Prefix CAT Optional Company ID Device # 9554 Product Number Suffix W Package W: SOIC Y: TSSOP HV4: TQFN I -G Lead Finish Blank: Matte-Tin G: NiPdAu T2 Tape & Reel T: Tape & Reel 2: 2,000/Reel 9554 9554A Temperature Range I = Industrial (-40ºC to 85ºC) ORDERING PART NUMBER Part Number CAT9554WI-G CAT9554WI-GT2 CAT9554YI-G CAT9554YI-GT2 CAT9554HV4I-G CAT9554HV4I-GT2 Package SOIC SOIC TSSOP TSSOP TQFN TQFN Lead Finish NiPdAu NiPdAu NiPdAu NiPdAu NiPdAu NiPdAu Part Number CAT9554AWI-G CAT9554AWI-GT2 CAT9554AYI-G CAT9554AYI-GT2 CAT9554AHV4I-G CAT9554AHV4I-GT2 Package SOIC SOIC TSSOP TSSOP TQFN TQFN Lead Finish NiPdAu NiPdAu NiPdAu NiPdAu NiPdAu NiPdAu Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT9554WI-GT2 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel). (4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 15 Doc. No. MD-9002, Rev. F CAT9554, CAT9554A REVISION HISTORY Date 08-Jul-05 28-Jun-06 Revision A B Description Initial Issue Update Features Add Applications Update Descriptions Update Pin Description Table Update Absolute Maximum Ratings Update D.C. Operating Characteristics Update A.C. Characteristics Update A.C. Test Conditions Update Pin Description Update Figure 2, Figure 4, Figure 5, Figure 8 and Figure 12 Update Functional Description Update Package Drawings Update Ordering Information Update Package Outline Drawings Update Example of Ordering Information Update Ordering Part Number Change Document number from 25088 Delete TQFN package in Matte-Tin. Update Package Outline Drawing - TQFN 16-Pad 4 x 4mm Update Package Outline Drawing - TQFN 16-Pad 4 x 4mm Update A.C. Characteristics table to include Standard I2C and Fast I2C. Change logo and fine print to ON Semiconductor 21-Jan-08 C 24-Apr-08 02-June-08 01-Dec-08 D E F ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. 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American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Doc. No. MD-9002, Rev. F 16 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice