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CM1293-08MR

CM1293-08MR

  • 厂商:

    ONSEMI(安森美)

  • 封装:

  • 描述:

    CM1293-08MR - 8-Channel Low Capacitance ESD Protection Arrays - ON Semiconductor

  • 数据手册
  • 价格&库存
CM1293-08MR 数据手册
8-Channel Low Capacitance ESD Protection Arrays CM1293 Features • Eight channels of ESD protection Note: For 2 and 4 channel devices, see the CM1293A datasheet. Provides ESD protection to IEC61000-4-2 • ±8kV contact discharge Low loading capacitance of 2.0pF max. Low clamping voltage Channel I/O to I/O capacitance 1.5pF typical Zener diode protects supply rail and eliminates the need for external by-pass capacitors Each I/O pin can withstand over 1000 ESD strikes* Available in MSOP, lead-free packaging Product Description The CM1293 family of diode arrays has been designed to provide ESD protection for electronic components or sub-systems requiring minimal capacitive loading. These devices are ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either the positive (VP) or negative (VN) supply rail. A Zener diode is embedded between VP and VN, offering two advantages. First, it protects the VCC rail against ESD strikes, and second, it eliminates the need for a bypass capacitor that would otherwise be needed for absorbing positive ESD strikes to ground. The CM1293 will protect against ESD pulses up to ( 8kV contact discharge) per the IEC 61000-4-2 Level 4 standard. This device is particularly well-suited for protecting systems using high-speed ports such as USB2.0, IEEE1394 (Firewire®, iLink™), Serial ATA, DVI, HDMI and corresponding ports in removable storage, digital camcorders, DVD-RW drives and other applications where extremely low loading capacitance with ESD protection are required in a small package footprint. • • • • • • • Applications • • • • DVI ports, HDMI ports in notebooks, set top boxes, digital TVs, LCD displays Serial ATA ports in desktop PCs and hard disk drives PCI Express ports General purpose high-speed data line ESD protection Block Diagram *Standard test condition is IEC61000-4-2 level 4 test circuit with each pin subjected to ±8kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. ©2010 SCILLC. All rights reserved. April 2010 – Rev. 3 Publication Order Number: CM1293/D CM1293 T p View o CH1 CH2 CH3 CH4 1 2 3 4 5 10 9 8 7 6 CH6 CH5 CH8 CH7 10-Lead MSOP-10 PIN DESCRIPTIONS 8-CHANNEL, 10-LEAD MSOP-10 PACKAGE PIN 1 2 3 4 5 6 7 8 9 10 NAME CH1 CH2 CH3 CH4 VN CH5 CH6 VP CH7 CH8 TYPE I/O I/O I/O I/O GND I/O I/O PWR I/O I/O DESCRIPTION ESD Channel ESD Channel ESD Channel ESD Channel Negative voltage supply rail ESD Channel ESD Channel Positive voltage supply rail ESD Channel ESD Channel Rev. 3 | Page 2 of 10 | www.onsemi.com CM1293 Ordering Information PART NUMBERING INFORMATION Lead-free Finish # of Channels 8 Leads 10 Package MSOP-10 Ordering Part Number1 CM1293-08MR Part Marking D039 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER Operating Supply Voltage (VP - VN) Operating Temperature Range Storage Temperature Range DC Voltage at any channel input RATING 6.0 -40 to +85 -65 to +150 (VN - 0.5) to (VP + 0.5) UNITS V °C °C V STANDARD OPERATING CONDITIONS PARAMETER Operating Temperature Range Package Power Rating MSOP-10 Package (CM1293-08MR) RATING -40 to +85 UNITS °C 400 mW Rev. 3 | Page 3 of 10 | www.onsemi.com CM1293 ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1) SYMBOL VP IP VF PARAMETER Operating Supply Voltage (VP-VN) Operating Supply Current Diode Forward Voltage Top Diode Bottom Diode Channel Leakage Current Channel Input Capacitance (VP-VN)=3.3V IF = 8mA; TA=25°C 0.60 0.60 TA=25°C; VP=5V, VN=0V At 1 MHz, VP=3.3V, VN=0V, VIN=1.65V 0.80 0.80 ±0.1 1.0 0.95 0.95 ±1.0 1.5 V V μA pF CONDITIONS MIN TYP 3.3 MAX 5.5 8.0 UNITS V μA ILEAK CIN ΔC IN Channel Input Capacitance Matching Mutual Capacitance between signal pin and adjacent signal pin ESD Protection Peak Discharge Voltage at any channel input, in system Contact discharge per IEC 61000-4-2 standard Channel Clamp Voltage Positive Transients Negative Transients Dynamic Resistance Positive Transients Negative Transients At 1 MHz, VP=3.3V, VN=0V, VIN=1.65V 0.02 pF CMUTUAL At 1 MHz, VP=3.3V, VN=0V, VIN=1.65V 0.11 pF VESD Notes 3 and 4; TA=25°C TA=25°C, IPP = 1A, tP = 8/20μs; Notes 4 IPP = 1A, tP = 8/20μs Any I/O pin to Ground; Note 4 ±8 kV VCL +8.8 -1.4 V V Ω Ω RDYN 0.7 0.4 Note 1: Note 2: Note 3: Note 4: All parameters specified at TA = -40°C to +85°C unless otherwise noted. Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 3.3V, VN grounded. Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 3.3V, VN grounded. These measurements performed with no external capacitor on VP (VP floating). Rev. 3 | Page 4 of 10 | www.onsemi.com CM1293 Performance Information Input Channel Capacitance Performance Curves Rev. 3 | Page 5 of 10 | www.onsemi.com CM1293 Performance Information (cont’d) Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment) Figure 1. Insertion Loss (S21) VS. Frequency (0V DC Bias, VP=3.3V) Figure 2. Insertion Loss (S21) VS. Frequency (2.5V DC Bias, VP=3.3V) Rev. 3 | Page 6 of 10 | www.onsemi.com CM1293 Application Information Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is: VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt+ L2 x d(IESD) / dt where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by ΔIESD/Δt, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. The CM1293 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22μF ceramic chip capacitor be connected between VP and the ground plane. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Figure 3. Application of Positive ESD Pulse between Input Channel and Ground Rev. 3 | Page 7 of 10 | www.onsemi.com CM1293 Mechanical Details MSOP-10 Mechanical Specifications, 10 pin The 10-pin MSOP package dimensions are presented below. PACKAGE DIMENSIONS Package Pins Millimeters Dimensions Min A A1 B C D E e H L # per tape and reel 0.75 0.05 0.17 0.13 2.90 2.90 Max 0.95 0.15 0.27 0.23 3.10 3.10 Min 0.028 0.002 0.007 0.005 0.114 0.114 Max 0.038 0.006 0.013 0.009 0.122 0.122 MSOP 10 Inches 0.50 BSC 4.90 BSC 0.40 0.70 0.0196 BSC 0.193 BSC 0.0137 4000 0.029 Controlling dimension: millimeters Package Dimensions for MSOP-10 Rev. 3 | Page 8 of 10 | www.onsemi.com CM1293 Tape and Reel Specifications PART NUMBER CM1293-08MR PACKAGE SIZE (mm) 3.00 X 3.00 X 0.85 POCKET SIZE (mm) B0 X A0 X K0 3.30 X 5.30 X 1.30 TAPE WIDTH W 12mm REEL DIAMETER 330mm (13") QTY PER REEL 4000 P0 4mm P1 4mm Rev. 3 | Page 9 of 10 | www.onsemi.com CM1293 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 For additional information, please contact your local Sales Representative Order Literature: http://www.onsemi.com/orderlit ON Semiconductor Website: www.onsemi.com Rev. 3 | Page 10 of 10 | www.onsemi.com
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