CS5101

CS5101 Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters The CS5101 is a bipolar monolithic secondary side post regulator (SSPR) which provides tight regulation of multiple output voltages in AC/DC or DC/DC converters. Leading edge pulse width modulation is used with the CS5101. The CS5101 is designed to operate over an 8.0 V to 45 V supply voltage (VCC) range and up to a 75 V drive voltage (VC). The CS5101 features include a totem pole output with 1.5 A peak output current capability, externally programmable overcurrent protection, an on chip 2.0% precision 5.0 V reference, internally compensated error amplifier, externally synchronized switching frequency, and a power switch drain voltage monitor. It is available in a 14 lead plastic DIP or a 16 lead wide body SOIC package. Features http://onsemi.com PDIP−14 N SUFFIX CASE 646 1 14 16 1 SO−16WB DW SUFFIX CASE 751G • • • • • • • • • • • 1.5 A Peak Output (Grounded Totem Pole) 8.0 V to 75 V Gate Drive Voltage 8.0 V to 45 V Supply Voltage 300 ns Propagation Delay 1.0% Error Amplifier Reference Voltage Lossless Turn On and Turn Off Sleep Mode: < 100 mA Overcurrent Protection with Dedicated Differential Amp Synchronization to External Clock External Power Switch Drain Voltage Monitor Pb−Free Packages are Available* MARKING DIAGRAMS AND PIN ASSIGNMENTS 1 SYNC VCC VREF LGND VFB COMP RAMP PDIP−14 1 CS5101 AWLYYWWG 16 VD VC VG PGND PGND IS COMP IS− IS+ CS5101EN14 AWLYYWWG 14 VD VC VG PGND IS COMP IS− IS+ SYNC VCC VREF DGND AGND VFB COMP RAMP SO−16WB A WL YY WW G *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION October, 2006 − Rev. 6 1 Publication Order Number: CS5101/D CS5101 VSY 1 TR CR4 L1 3 Q1 4 5 R10 VOUT 6 CR5 R5 R6 R8 R11 R13 + C6 R9 R12 R14 GND CR1 + R1 R2 CR3 R7 C5 VSYNC VCC R3 CR2 VREF LGND VFB COMP + C1 C2 R4 RAMP VD VC VG C4 CS5101 SSPR PGND IS COMP IS− IS+ 2 C3 CR Figure 1. Application Diagram MAXIMUM RATINGS Rating Power Supply Voltage, VCC VSYNC and Output Supply Voltages, VC, VG, VSYNC, VD VIS+, VIS− (VCC − 4.0 V, up to 24 V) VREF, VFB, VCOMP, VRAMP, VISCOMP Operating Junction Temperature, TJ Operating Temperature Range Storage Temperature Range Output Energy (Capacitive Load Per Cycle) ESD Human Body Lead Temperature Soldering Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Value −0.3 to 45 −0.3 to 75 −0.3 to 24 −0.3 to 10 −40 to +150 −40 to +85 −65 to +150 5.0 2.0 260 peak 230 peak Unit V V V V °C °C °C mJ kV °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 10 second maximum 2. 60 second maximum above 183°C http://onsemi.com 2 CS5101 otherwise specified.) ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 85°C, −40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless Characteristic Error Amplifier Input Voltage Initial Accuracy Input Voltage Input Bias Current Open Loop Gain Unity Gain Bandwidth Output Sink Current Output Source Current VCOMP High VCOMP Low PSRR Voltage Reference Output Voltage Initial Accuracy Output Voltage Line Regulation Load Regulation Current Limit VREF−OK FAULT V VREF−OK V VREF−OK Hysteresis Current Sense Amplifier IS COMP High V IS COMP Low V Source Current Sink Current Open Loop Gain CMRR PSRR Unity Gain Bandwidth Input Offset Voltage Input Bias Currents Input Offset Current (IS+, IS−) Input Signal Voltage Range RAMP/SYNC Generator RAMP Source Current Initial Accuracy RAMP Source Current RAMP Sink Current RAMP Peak Voltage RAMP Valley Voltage RAMP Dynamic Range RAMP Sleep Threshold Voltage SYNC Threshold VSYNC = 5.0 V, VRAMP = 2.5 V, T = 25°C, Note 3 VSYNC = 5.0 V, VRAMP = 2.5 V VSYNC = 0 V, VRAMP = 2.5 V VSYNC = 5.0 V VSYNC = 0 V VRAMPDR = VRAMPPK − VRAMPVY VRAMP @ VREF < 2.0 V VSYNC @ VRAMP > 2.5 V 0.18 0.16 1.0 3.3 1.4 1.7 0.3 2.3 − 0.20 0.20 4.0 3.5 1.5 2.0 0.6 2.5 1.0 0.22 0.24 − 3.7 1.6 2.3 1.0 2.7 20 mA mA mA V V V V V mA Note 3 IS+ = 5.0 V, IS− = IS COMP IS+ = 0 V, IS− = IS COMP IS+ = 5.0 V, IS− = 0 V IS− = 5.0 V, IS+ = 0 V 1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 kW Note 3 10 V < VCC < 45 V, Note 3 1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 kW, Note 3 VIS+ = 2.5 V, VIS− = VISCOMP VIS+ = VIS− = 0 V, IIS flows out of pins − 4.7 0.5 2.0 10 60 60 60 0.5 −8.0 − −250 −0.3 5.0 1.0 10 20 80 80 80 0.8 0 20 0 − 5.3 1.3 − − − − − − 8.0 250 250 VCC − 4.0 V V mA mA dB dB dB MHz mV nA nA V VCC = 15 V, T = 25°C, Note 3 0 A < IREF < 8.0 mA 10 V < VCC < 45 V, IREF = 0 A 0 A < IREF < 8.0 mA VREF = 4.8 V VSYNC = 5.0 V, VREF = VLOAD VSYNC = 5.0 V, VREF = VLOAD − 4.9 4.8 − − 10 4.10 4.30 40 5.0 5.0 10 20 50 4.40 4.50 100 5.1 5.2 60 60 − 4.60 4.80 250 V V mV mV mA V V mV VFB = VCOMP, VCC = 15 V, T = 25°C, Note 3 VFB = VCOMP, includes line and temp VFB = 0 V, IVFB flows out of pin 1.5 V < VCOMP < 3.0 V 1.5 V < VCOMP < 3.0 V, Note 3 VCOMP = 2.0 V, VFB = 2.2 V VCOMP = 2.0 V, VFB = 1.8 V VFB = 1.8 V VFB = 2.2 V 10 V < VCC < 45 V, VFB = VCOMP, Note 3 1.98 1.94 − 60 0.7 2.0 2.0 3.3 0.85 60 2.00 2.00 − 70 1.0 8.0 6.0 3.5 1.0 70 2.02 2.06 500 − − − − 3.7 1.15 − V V nA dB MHz mA mA V V dB Test Conditions Min Typ Max Unit SYNC Input Bias Current VSYNC = 0 V, ISYNC flows out of pin 3. Guaranteed by design. Not 100% tested in production. http://onsemi.com 3 CS5101 unless otherwise specified.) Characteristic Output Stage VG, High VG, Low VG Rise Time VG Fall Time VG Resistance to GND VD Resistance to GND General ICC, Operating ICC in UVL ICC in Sleep Mode High ICC in Sleep Mode Low IC, Operating High IC, Operating Low UVLO Start Voltage UVLO Stop Voltage UVLO Hysteresis Leading Edge, tDELAY Trailing Edge, tDELAY VSYNC = 5.0 V VCC = 6.0 V VRAMP = 0 V, VCC = 45 V VRAMP = 0 V, VCC = 10 V VSYNC = 5.0 V, VFB = VIS− = 0 V, VC = 75 V VSYNC = 5.0 V, VFB = VIS− = 0 V, VC = 8.0 V − − − VSYNC = 2.5 V to VG = 8.0 V VSYNC = 2.5 V to VG = 2.0 V − − − − − − 7.4 6.4 0.8 − − 12 300 80 20 4.0 3.0 8.0 7.0 1.0 280 750 18 500 200 50 8.0 6.0 9.2 8.3 1.2 − − mA mA mA mA mA mA V V V ns ns VSYNC = 5.0 V, IVG = 200 mA, VC − VG VSYNC = 0 V, IVG = 200 mA Switch VSYNC High, CG = 1.0 nF, VCC = 15 V, measure 2.0 V to 8.0 V Switch VSYNC Low, CG = 1.0 nF, VCC = 15 V, measure 8.0 V to 2.0 V Remove supplies, VG = 10 V Remove supplies, VD = 10 V − − − − − 500 1.6 0.9 30 40 50 1500 2.5 1.5 75 100 100 − V V ns ns kW W ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 85°C, −40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; Test Conditions Min Typ Max Unit PACKAGE PIN DESCRIPTION PACKAGE LEAD # PDIP−14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 − − SO−16WB 1 2 3 − 6 7 8 9 10 11 12, 13 14 15 16 5 4 LEAD SYMBOL SYNC VCC VREF LGND VFB COMP RAMP IS+ IS− IS COMP PGND VG VC VD AGND DGND Synchronization input. Logic supply (10 V to 45 V). 5.0 V voltage reference. Logic level ground (analog and digital ground tied). Error amplifier inverting input. Error amplifier output and compensation. RAMP programmable with the external capacitor. Current sense amplifier non−inverting input. Current sense amplifier inverting input. Current sense amplifier compensation and output. Power ground. External power switch gate drive. Output power stage supply voltage (8.0 V to 75 V). External FET DRAIN voltage monitor. Analog ground. Digital ground. FUNCTION http://onsemi.com 4 CS5101 ORDERING INFORMATION Device CS5101EN14 CS5101EN14G CS5101EDW16 CS5101EDW16G CS5101EDWR16 CS5101EDWR16G Package PDIP−14 PDIP−14 (Pb−Free) SOIC−16WB SOIC−16WB (Pb−Free) SOIC−16WB SOIC−16WB (Pb−Free) 1000 / Tape & Reel 47 Units / Rail 25 Units / Rail Shipping † †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. CIRCUIT DESCRIPTION VCC VCC REF VREF LGND 5.0 V OK + UVL + − + − 8.0 V/7.0 V VD VC + SLEEP − 0.7 V + − Q1 VG Q2 PGND IS COMP 5.0 V VFB − + VCC 24.6 k − BUF + + 2.4 V − 5.0 V IS − + IS− IS+ EA 10 k 10 k VC + 2.0 V − − − + PWM + Q S 5.0 V Q3 COMP 5.0 V 5.0 V 0.7 V + − VCC−OK I = 200 mA RAMP 5.0 V + RAMP − + − 1.65 V + 1.5 V − LATCH Q R 5.0 V − + Q4 G1 REF_OK + 5.0 V + SYNC − G2 − + − 4.5 V/4.4 V VCC SYNC + − 2.5 V Figure 2. Block Diagram http://onsemi.com 5 CS5101 Theory of Operation The CS5101 is designed to regulate voltages in multiple output power supplies. Functionally, it is similar to a magnetic amplifier, operating as a switch with a delayed turn−on. It can be used with both single ended and dual ended topologies. The VFB voltage is monitored by the error amplifier EA. It is compared to an internal reference voltage and the amplified differential signal is fed through an inverting amplifier into the buffer, BUF. The buffered signal is compared at the PWM comparator with the ramp voltage generated by capacitor CR. When the ramp voltage VR, exceeds the control voltage VC, the output of the PWM comparator goes high, latching its state through the LATCH, the output stage transistor Q1 turns on, and the external power switch, usually an N−FET, turns on. SYNC Function The logic state of the LATCH can be changed only when both the voltage level of the trailing edge of the power pulse at the SYNC pin is less than the threshold voltage of the SYNC comparator (2.5 V) and the RAMP voltage is less than the threshold voltage of the RAMP comparator (1.65 V). On the negative going transition of the secondary side pulse VSY, gate G2 output goes high, resetting the latch at time t3. Capacitor CR is discharged through transistor Q4. CR’s output goes low disabling the output stage, and the external power switch (an N−FET) is turned off. RAMP Function The SYNC circuit is activated at time t1 (Figure 3) when the voltage at the SYNC pin exceeds the threshold level (2.5V) of the SYNC comparator. The external ramp capacitor CR is allowed to charge through the internal current source I (200 mA). At time t2, the ramp voltage intersects with the control voltage VC and the output of the PWM comparator goes high, turning on the output stage and the external power switch. At the same time, the PWM comparator is latched by the RS latch, LATCH. The value of the ramp capacitor CR is based on the switching frequency of the regulator and the maximum duty cycle of the secondary pulse VSY. If the RAMP pin is pulled externally to 0.3 V or below, the SSPR is disabled. Current drawn by the IC is reduced to less than 100 mA, and the IC is in SLEEP mode. FAULT Function 1 VSY 0V VSY 2 VSY + VD VC VRAMP VDS 3 0V VSY VD VS 4 0V The voltage at the VCC pin is monitored by the undervoltage lockout comparator with hysteresis. When VCC falls below the UVL threshold, the 5.0 V reference and all the circuitry running off of it is disabled. Under this condition the supply current is reduced to less than 500 mA. The VCC supply voltage is further monitored by the VCC_OK comparator. When VCC is reduced below VREF − 0.7 V, a fault signal is sent to gate G1 . This fault signal, which determines if VCC is absent, works in conjunction with the ramp signal to disable the output, but only after the current cycle has finished and the RS latch is reset. Therefore this fault will not cause the output to turn off during the middle of an on pulse, but rather will utilize lossless turn−off. This feature protects the FET from overvoltage stress. This is accomplished through gate G1 by driving transistor Q4 on. An additional fault signal is derived from the REF_OK comparator. VREF is monitored so to disable the output through gate G1 when the VREF voltage falls below the OK threshold. As in the VCC_OK fault, the REF_OK fault disables the output after the current cycle has been completed. The fault logic will operate normally only when VREF voltage is within the specification limits of REF_OK. DRAIN Function VSY − VOUT VL1 VOUT + VD 5 0V VSY + VC VD VG The drain pin, VD monitors the voltage on the drain of the power switch and derives energy from it to keep the output stage in an off state when VC or VCC is below the minimum specified voltage. 6 0V t1 t2 t3 t4 t1 Ground Level (Gate doesn’t go below GND) Figure 3. Waveforms for CS5101. The Number to the Left of Each Curve Refers to a Node On the Application Diagram on Page 2. http://onsemi.com 6 CS5101 S1 C1 1.0 mF SW SPST 8.0 V − 45 V R1 100 k R2 100 k VSYNC VD VCC VC CS5101 VREF VG LGND PGND VFB IS COMP COMP IS− RAMP IS+ R7 10 k C5 680 pF V1 100 kHz 0 V to 5.0 V Square Wave C2 0.1 mF R3 5.0 k C3 1.0 nF R6 10 k C4 0.1 mF R4 2.2 k R5 10 k Figure 4. CS5101 Bench Test on DIP−14 Package http://onsemi.com 7 CS5101 PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01 A F N −T− SEATING PLANE L C H G D 14 PL K M J M DIM A B C D F G H J K L M N 0.13 (0.005) http://onsemi.com 8 CS5101 PACKAGE DIMENSIONS SOIC−16WB CASE 751G−03 ISSUE C D 16 M 9 A q h X 45 _ 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ H M B 8X 1 16X 8 B TA S 0.25 M B S A E B A1 14X e SEATING PLANE T C PACKAGE THERMAL DATA Parameter RqJC RqJA Typical Typical PDIP−14 23 105 SOIC−16WB 48 85 Unit °C/W °C/W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative L http://onsemi.com 9 CS5101/D