CS5112

CS5112 1.4 A Switching Regulator with 5.0 V, 100 mA Linear Regulator with Watchdog, RESET and ENABLE The CS5112 is a dual output power supply integrated circuit. It contains a 5.0 V ± 2%, 100 mA linear regulator, a watchdog timer, a linear output voltage monitor to provide a Power On Reset (POR) and a 1.4 A current mode PWM switching regulator. The 5.0 V linear regulator is comprised of an error amplifier, reference, and supervisory functions. It has low internal supply current consumption and provides 1.2 V (typical) dropout voltage at maximum load current. The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal. If a correct watchdog signal is not received within the externally programmable time, a reset signal is issued. The externally programmable active reset circuit operates correctly for an output voltage (VLIN) as low as 1.0 V. During power up, or if the output voltage shifts below the regulation limit, RESET toggles low and remains low for the duration of the delay after proper output voltage regulation is restored. Additionally a reset pulse is issued if the correct watchdog is not received within the programmed time. Reset pulses continue until the correct watchdog signal is received. The reset pulse width and frequency, as well as the Power On Reset delay, are set by one external RC network. The current mode PWM switching regulator is comprised of an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator, and a 1.4 A output power switch with anti−saturation control. The switching regulator can be configured in a variety of topologies. The CS5112 is load dump capable and has protection circuitry which includes current limit on the linear and switcher outputs, and an overtemperature limiter. Features http://onsemi.com SOIC−24 DWF SUFFIX CASE 751E 1 24 MARKING DIAGRAM 24 CS5112 AWLYYWWG 1 CS5112 A WL YY WW G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS VIN NC NC VSW GND GND GND GND VFB1 VFB2 SELECT COMP 1 24 ENABLE VREG VLIN IBIAS GND GND GND GND RESET CDelay WDI COSC • Linear Regulator ♦ ♦ ♦ ♦ • Switching Regulator 5.0 V ± 2% @ 100 mA • • • • 1.4 A Peak Internal Switch 120 kHz Maximum Switching Frequency 5.0 V to 26 V Operating Supply Range Smart Functions ♦ Watchdog ♦ RESET ♦ ENABLE Protection ♦ Overtemperature ♦ Current Limit Internally Fused Leads in a SOIC Package Pb−Free Packages are Available* ORDERING INFORMATION Device CS5112YDWF24 CS5112YDWF24G CS5112YDWFR24 CS5112YDWFR24G Package SOIC−24 SOIC−24 (Pb−Free) Shipping † 30 Units/Rail 30 Units/Rail SOIC−24 1000/Tape & Reel SOIC−24 1000/Tape & Reel (Pb−Free) *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: CS5112/D 1 October, 2005 − Rev. 7 CS5112 Switcher Error Amplifier Multiplexer − + COMP Base Drive VIN VSW Logic 1.4 A VFB1 VFB2 SELECT COMP IBIAS COSC Current Sense Amplifier Oscillator + − + − GND Switcher Shutdown VREG ENABLE Linear Error Amplifier + − Current Limit VLIN Bandgap Reference 1.25 V Over Temperature RESET RESET & Watchdog Timer CDELAY WDI Figure 1. Block Diagram MAXIMUM RATINGS Rating Logic Inputs/Outputs (ENABLE, SELECT, WDI, RESET) VLIN VIN, VREG: VSW Peak Transient Voltage COSC, CDelay, COMP, VFB1, VFB2 Power Dissipation VLIN Output Current VSW Output Current RESET Output Sink Current ESD Susceptibility (Human Body Model) ESD Susceptibility (Machine Model) Storage Temperature Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) DC Input Voltage Peak Transient Voltage (26 V Load Dump @ 14 V VIN) Value −0.3 to VLIN −0.3 to 10 −0.3 to 26 −0.3 to 40 54 −0.3 to VLIM Internally Limited Internally Limited Internally Limited 5.0 2.0 200 −65 to 150 230 peak V V V V − − − mA kV V °C °C Unit V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 60 second maximum above 183°C. http://onsemi.com 2 CS5112 ELECTRICAL CHARACTERISTICS (5.0 V ≤ VIN ≤ 26 V and −40°C ≤ TJ ≤ 150°C, COUT = 100 mF (ESR ≤ 8.0 W), CDelay = 0.1 mF, RBIAS = 64.9 kW, COSC = 390 pF, CCOMP = 0.1 mF; unless otherwise specified.) Characteristic General IIN Off Current IIN On Current IREG Current Thermal Limit 5.0 V Regulator Section VLIN Output Voltage Dropout Voltage Line Regulation Load Regulation Current Limit DC Ripple Rejection RESET Section Low Threshold (VRTL) High Threshold (VRTH) Hysteresis Active High Active Low Delay Power On Delay Watchdog Input (WDI) VIH VIL Hysteresis Pullup Resistor Low Threshold Floating Input Voltage WDI Pulse Width Switcher Section Minimum Operating Input Voltage Switching Frequency Switch Saturation Voltage Output Current Limit Max Switching Frequency VFB1 Regulation Voltage VFB2 Regulation Voltage VFB1, VFB2 Input Current Oscillator Charge Current Oscillator Discharge Current CDelay Charge Current VFB1 = VFB2 = 5.0 V COSC = 0 V COSC = V40 CDelay = 0 V Refer to Figure 5 ISW = 1.4 A − VSW = 7.5 V with 50 W Load, Refer to Figure 5 − − − − 80 0.7 1.4 120 1.206 1.206 − 35 270 35 − 95 1.1 − − 1.25 1.25 − 40 320 40 5.0 110 1.6 2.5 − 1.294 1.294 1.0 45 370 45 V kHz V A kHz V V mA mA mA mA (Note 2) WDI = 0 V − − − Peak WDI Needed to Activate RESET − − 0.8 25 20 6.25 3.5 − − − 50 50 8.78 − − 2.0 − − 100 11 − 5.0 V V mV kW ms V ms VLIN Decreasing VLIN Increasing VRTH − VRTL VLIN > VRTH, IRESET = −25 mA VLIN = 1.0 V, 10 kW Pullup from RESET to VLIN VLIN = 4.0 V, IRESET = 1.0 mA Invalid WDI VLIN Crossing VRTH 4.05 4.2 140 VLIN − 0.5 − − 6.25 6.25 4.25 4.45 190 − − − 8.78 − 4.45 4.7 240 − 0.4 0.7 11 − V V mV V V V ms ms 6.6 V ≤ VREG ≤ 26 V, 1.0 mA ≤ ILIN ≤ 100 mA (VREG − VLIN) @ ILIN = 100 mA 6.6 V ≤ VREG ≤ 26 V, ILIN = 5.0 mA VREG = 19 V, 1.0 mA ≤ ILIN ≤ 100 mA 6.6 V ≤ VREG ≤ 26 V 14 V ≤ VREG ≤ 24 V 4.9 − − − 120 60 5.0 1.2 5.0 5.0 − 75 5.1 1.5 25 25 − − V V mV mV mA dB 6.6 V ≤ VIN ≤ 26 V, ISW = 0 A 6.6 V ≤ VIN ≤ 26 V, ISW = 1.4 A ILIN = 100 mA, 6.6 V ≤ VIN ≤ 26 V Guaranteed by Design − − − 160 − 30 − − 2.0 70 6.0 210 mA mA mA °C Test Conditions Min Typ Max Unit 2. Guaranteed by design, not 100% tested in productions. http://onsemi.com 3 CS5112 ELECTRICAL CHARACTERISTICS (5.0 V ≤ VIN ≤ 26 V and −40°C ≤ TJ ≤ 150°C, COUT = 100 mF (ESR ≤ 8.0 W), CDelay = 0.1 mF, RBIAS = 64.9 kW, COSC = 390 pF, CCOMP = 0.1 mF; unless otherwise specified.) Characteristic Switcher Section (continued) Switcher Max Duty Cycle Current Sense Amp Gain Error Amp DC Gain Error Amp Transconductance ENABLE Input VIL VIH Hysteresis Input Impedance Select Input VIL (Selects VFB1) VIH (Selects VFB2) SELECT Pullup Floating Input Voltage 4.9 ≤ VLIN ≤ 5.1 4.9 ≤ VLIN ≤ 5.1 SELECT = 0 V − 0.8 − 10 3.5 1.25 1.25 24 4.5 − 2.0 50 − V V kW V − − − − 0.8 − − 10 1.24 1.3 60 20 − 2.0 − 40 V V mV kW VSW = 5.0 V with 50 W Load, VFB1 = VFB2 = 1.0 V ISW = 2.3 A − − 72 − − − 85 7.0 67 2700 95 − − − % V/V dB mA/V Test Conditions Min Typ Max Unit PIN FUNCTION DESCRIPTION PACKAGE PIN # SOIC−24 1 2, 3 4 5, 6, 7, 8, 17, 18, 19, 20 9 10 11 12 13 14 15 16 21 22 23 24 PIN SYMBOL VIN NC VSW GND VFB1 VFB2 SELECT COMP COSC WDI CDelay RESET IBIAS VLIN VREG ENABLE Supply voltage. No connection. Collector of NPN power switch for switching regulator section. Connected to the heat removing leads. Feedback input voltage 1 (referenced to 1.25 V). Feedback input voltage 2 (referenced to 1.25 V). Logic level input that selects either VFB1 or VFB2. An open selects VFB2. Connect to GND to select VFB1. Output of the transconductance error amplifier. A capacitor connected to GND sets the switching frequency. Refer to Figure 5. Watchdog input. Active on falling edge. A capacitor connected to GND sets the Power On Reset and Watchdog time. RESET output. Active low if VLIN is below the regulation limit. If watchdog timeout is reached, a reset pulse train is issued. A resistor connected to GND sets internal bias currents as well as the COSC and CDelay charge currents. Regulated 5.0 V output from the linear regulator section. Input voltage to the linear regulator and the internal supply circuitry. Logic level input to shut down the switching regulator. FUNCTION http://onsemi.com 4 CS5112 TYPICAL PERFORMANCE CHARACTERISTICS 4.5 0 IREG − ILIN (mA) −10 IIN (mA) 0 20 40 100 4.0 −20 −30 3.5 60 ILIN (mA) 80 −40 0 0.5 1.0 ISW (A) 1.5 2.0 Figure 2. 5.0 V Regulator Bias Current vs. Load Current Figure 3. Supply Current vs. Switch Current 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 Frequency (kHz) 0 0.5 1.0 ISW (A) 1.5 2.0 VSW (V) 180 160 140 120 100 80 60 40 20 0 0 500 1000 1500 COSC (pF) 2000 2500 3000 Figure 4. Switch Saturation Voltage Figure 5. Oscillator Frequency (kHz) vs. COSC (pF), Assuming RBIAS = 64.9 kW http://onsemi.com 5 CS5112 CIRCUIT DESCRIPTION VREG R1 Linear Error Amplifier Q2 Q1 Q3 R2 R3 IBIAS RBIAS 64.9 kW CDelay WDI Bandgap Reference 1.25 V Over Temperature R4 R5 RESET & Watchdog Timer RESET VLIN COUT = 100 mF ESR < 8.0 W + − Current Limit Figure 6. Block Diagram of 5.0 V Linear Regulator Portion of the CS5112 5.0 V LINEAR REGULATOR The 5.0 V linear regulator consists of an error amplifier, bandgap voltage reference, and a composite pass transistor. The 5.0 V linear regulator circuitry is shown in Figure 6. When an unregulated voltage greater than 6.6 V is applied to the VREG input, a 5.0 V regulated DC voltage will be present at VLIN. For proper operation of the 5.0 V linear regulator, the IBIAS lead must have a 64.9 kW pull down resistor to ground. A 100 mF or larger capacitor with an ESR < 8.0 W must be connected between VLIN and ground. To operate the 5.0 V linear regulator as an independent regulator (i.e. separate from the switching supply), the input voltage must be tied to the VREG lead. As the voltage at the VREG input is increased, Q1 is turned on. Q1 provides base drive for Q2 which in turn provides base current for Q3. As Q3 is turned on, the output voltage, VLIN, begins to rise as Q3’s output current charges the output capacitor, COUT. Once VLIN rises to a certain level, the error amplifier becomes biased and provides the appropriate amount of base current to Q1. The error amplifier monitors the scaled output voltage via an internal voltage divider, R2 through R5, and compares it to the bandgap voltage reference. The error amplifier output or error signal is an output current equal to the error amplifier’s input differential voltage times the transconductance of the amplifier. Therefore, the error amplifier varies the base current to Q1, which provides bias to Q2 and Q3, based on the difference between the reference voltage and the scaled VLIN output voltage. CONTROL FUNCTIONS edge of this watchdog signal which it expects to see within an externally programmable time (see Figure 7). The watchdog time is given by: tWDI + 1.353 CDelayRBIAS Using CDelay = 0.1 mF and RBIAS = 64.9 kW gives a time ranging from 6.25 ms to 11 ms assuming ideal components. Based on this, the software must be written so that the watchdog arrives at least every 6.25 ms. In practice, the tolerance of CDelay and RBIAS must be taken into account when calculating the minimum watchdog time (tWDI). VREG RESET WDI VLIN tPOR Normal Operation Figure 7. Timing Diagram for Normal Regulator Operation The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling If a correct watchdog signal is not received within the specified time a reset pulse train is issued until the correct watchdog signal is received. The nominal reset signal in this case is a 5 volt square wave with a 50% duty cycle as shown in Figure 8. http://onsemi.com 6 CS5112 50% Duty Cycle The POR delay (tPOR) is given by: tPOR + 1.353 CDelayRBIAS VREG RESET CURRENT MODE PWM SWITCHING CIRCUITRY WDI VLIN tPOR A B A: Watchdog waiting for low−going transition on WDI B: RESET stays low for tWDI time Figure 8. Timing Diagram When WDI Fails to Appear Within the Preset Time Interval, tWDI The RESET signal frequency is given by: fRESET + 1 2(tWDI) The Power On Reset (POR) and low voltage RESET use the same circuitry and issue a reset when the linear output voltage is below the regulation limit. After VLIN rises above the minimum specified value, RESET remains low for a fixed period tPOR as shown in Figures 9 and 10. VLIN 4.45 V 4.25 V RESET VR(LO) VR(PEAK) tPOR The current mode PWM switching voltage regulator contains an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator and a 1.4 A output power switch with antisaturation control. The switching regulator and external components, connected in a boost configuration, are shown in Figure 11. The switching regulator begins operation when VREG and VIN are raised above 5.0 V. VREG is required since the switching supply’s control circuitry is powered through VLIN. VIN supplies the base drive to the switcher output transistor. The output transistor turns on when the oscillator starts to charge the capacitor on COSC. The output current will develop a voltage drop across the internal sense resistor (RS). This voltage drop produces a proportional voltage at the output of the current sense amplifier, which is compared to the output of the error amplifier. The error amplifier generates an output voltage which is proportional to the difference between the scaled down output boost voltage (VFB1 or VFB2) and the internal bandgap voltage reference. Once the current sense amplifier output exceeds the error amplifier’s output voltage, the output transistor is turned off. The energy stored in the inductor during the output transistor on time is transferred to the load when the output transistor is turned off. The output transistor is turned back on at the next rising edge of the oscillator. On a cycle by cycle basis, the current mode controller in a discontinuous mode of operation charges the inductor to the appropriate amount of energy, based on the energy demand of the load. Figure 12 shows the typical current and voltage waveforms for a boost supply operating in the discontinuous mode. Notes: Figure 9. The Power On Reset Time Interval (tPOR) Begins When VLIN Rises Above 4.45 V (Typical) VLIN 5.0 V 4.25 V 1. Refer to Figure 5 to determine oscillator frequency. 2. The switching regulator can be disabled by providing a logic high at the ENABLE input. 3. The boost output voltage can be controlled dynamically by the feedback select input. If select is open, VFB2 is selected. If select is low, then VFB1 is selected. RESET 5.0 V tPOR Figure 10. RESET Signal Is Issued Whenever VLIN Falls Below 4.25 V (Typical) http://onsemi.com 7 CS5112 VIN VLIN VOUT COMP VSW Logic + − Base Drive 1.4 A COUT IBIAS RBIAS 64.9 kW COSC Oscillator Current Sense Amplifier RS GND ENABLE + − Switcher Shutdown 1.25 V Bandgap Reference R1 R2 R3 SELECT COMP Switcher Error Amplifier VFB1 − + Multiplexer VFB2 Figure 11. Block Diagram of the 1.4 A Current Mode Control Switching Regulator Portion of the CS5112 in a Boost Configuration VSW VOUT PROTECTION CIRCUITRY VIN VSAT 0 ISW IPeak t 0 ID IPeak t The current out of VLIN is sensed in order to limit excessive power dissipation in the linear output transistor over the output range of 0 V to regulation. Also, the current into VSW is sensed in order to provide the current limit function in the switcher output transistor. If the die temperature is increased above 160°C, either due to excessive ambient temperature or excessive power dissipation, the drive to the linear output transistor is reduced proportionally with increasing die temperature. Therefore, VLIN will decrease with increasing die temperature above 160°C. Since the switcher control circuitry is powered through VLIN, the switcher performance, including current limit, will be affected by the decrease in VLIN. 0 t Figure 12. Voltage and Current Waveforms for Boost Topology in CS5112 http://onsemi.com 8 CS5112 APPLICATION NOTES DESIGN PROCEDURE FOR BOOST TOPOLOGY Therefore: VINtON + (VOUT * VIN)tOFF (6) This section outlines a procedure for designing a boost switching power supply operating in the discontinuous mode. Step 1 where the maximum on time is: POUT + IOUTVOUT tON(MAX) [ 1 * (1) Determine the output power required by the load. VIN(MIN) VOUT(MAX) 1 fSW(MIN) (7) Step 2 Step 5 Choose COSC based on the target oscillator frequency with an external resistor value, RBIAS = 64.9 kW. (See Figure 5). Step 3 Calculate the maximum inductance allowed for discontinuous operation: 2 f V2 t L(MAX) + SW(MIN) IN (MIN) ON (MAX) 2POUT h (8) Next select the output voltage feedback sense resistor divider as follows (Figure 13). For VFB1 active, choose a value for R1 and then solve for REQ where: R REQ + VOUT 1 *1 VFB1 (2) For VFB2 active, find: REQ VFB1 + VOUT R1 ) REQ (3) where η = efficiency. Usually η = 0.75 is a good starting point. The IC’s power dissipation should be calculated after the peak current has been determined in Step 6. If the efficiency is less than originally assumed, decrease the efficiency and recalculate the maximum inductance and peak current. Step 6 and then calculate R2 where: V V * VFB2 R2 + R2 + FB1 IR2 VFB1 REQ (4) Determine the peak inductor current at the minimum inductance, minimum VIN and maximum on time to make sure the inductor current doesn’t exceed 1.4 A. V t IPK + IN(MIN) ON(MAX) L(MIN) Step 7 (9) Then find R3, where: R3 + REQ * R2 VOUT R1 VFB1 VR2 REQ R3 R2 VFB2 (5) Determine the minimum output capacitance and maximum ESR based on the allowable output voltage ripple. IPK COUT(MIN) + 8fDVRIPPLE ESR(MIN) + DVRIPPLE IPK (10) (11) In practice, it is normally necessary to use a larger capacitance value to obtain a low ESR. By placing capacitors in parallel, the equivalent ESR can be reduced. Step 8 Figure 13. Feedback Sense Resistor Divider Connected Between VOUT and Ground Step 4 Determine the maximum on time at the minimum oscillator frequency and VIN. For discontinuous operation, all of the stored energy in the inductor is transferred to the load prior to the next cycle. Since the current through the inductor cannot change instantaneously and the inductance is constant, a volt−second balance exists between the on time and off time. The voltage across the inductor during the on cycle is VIN and the voltage across the inductor during the off cycle is VOUT − VIN. Compensate the feedback loop to guarantee stability under all operating conditions. To do this, we calculate the modulator gain and the feedback resistor network attenuation and set the gain of the error amplifier so that the overall loop gain is 0 dB at the crossover frequency, fCO. In addition, the gain slope should be −20 dB/decade at the crossover frequency. The low frequency gain of the modulator (i.e. error amplifier output to output voltage) is: IPK(MAX) DVOUT + DVEA VEA(MAX) RLOADLf 2 (12) where: V G 2.4 V 7 IPK(MAX) + EA(MAX) CSA + + 2.3 A (13) 150 mW RS http://onsemi.com 9 CS5112 The VOUT/VEA transfer function has a pole at: fp + 1 (pRLOADCOUT) (14) R1 VFB1 M U X 1.25 V + − Error Amplifier C1 R4 C2 VOUT and a zero due to the output capacitor’s ESR at: fz + 1 (2pESR(COUT)) (15) R2 Since the error amplifier reference voltage is 1.25 V, the output voltage must be divided down or attenuated before being applied to the input of the error amplifier. The feedback resistor divider attenuation is: 1.25 V VOUT VFB2 R3 The error amplifier in the CS5112 is an operational transconductance amplifier (OTA), with a gain given by: GOTA + gmZOUT (16) SELECT Figure 14. RC Network Used to Compensate the Error Amplifier (OTA) where: gm + DIOUT DVIN (17) A pole at point C: fp + 1 (pR4C2) (19) For the CS5112, gm = 2700 mA/V typical. One possible error amplifier compensation scheme is shown in Figure 14. This gives the error amplifier a gain plot as shown in Figure 15. For the error amplifier gain shown in Figure 15, a low frequency pole is generated by the error amplifier output impedance and C 1 . This is shown by the line AB with a −20 dB/decade slope in Figure 15. The slope changes to zero at point B due to the zero at: fz + 1 (2pR4C1) (18) offsets the zero set by the ESR of the output capacitors. An alternative scheme uses a single capacitor as shown in Figure 16, to roll the gain off at a relatively low frequency. Step 9 Finally the watchdog timer period and Power on Reset time is determined by: tDelay + 1.353 CDelayRBIAS (20) Pole due to error amplifier output impedance and C1 G A fz = 1/(2πR4C1) +G B error amplifier gain Gain (dB) −20 dB/dec C fp = 1/(πR4C2) fp = 1/(πRLOADCOUT) fCO 0 modulator gain + feedback resistor divider attenuation −G fz = 1/(2πESR(COUT)) Figure 15. Bode Plot of Error Amplifier (OTA) Gain and Modulator Gain Added to the Feedback Resistor Divider Attenuation http://onsemi.com 10 CS5112 VIN VOUT = 18 V, Select > 2.0 V VOUT = 16 V, Select < 0.8 V VIN NC ENABLE VREG VLIN IBIAS GND GND CS5112 GND GND RESET CDelay WDI COSC COSC 390 pF Microprocessor RBIAS 64.9 kW 100 mF ESR < 8.0 W 5.0 V L = 33 mH NC VSW COUT 88 mF (2) GND GND R1 100 kW GND GND VFB1 (1) VFB2 SELECT COMP CCOMP 0.33 mF R2 946 W R3 7.5 kW CDelay 0.1 mF Figure 16. A Typical Application Diagram with External Components Configured in a Boost Topology http://onsemi.com 11 CS5112 LINEAR REGULATOR OUTPUT CURRENT VS. INPUT VOLTAGE 100 ILIN (mA) 100 ILIN (mA) 75 qJA = 55°C/W VIN = 14 V Max Total Power = 1.18 W 75 qJA = 35°C/W VIN = 14 V Max Total Power = 1.86 W 50 50 25 25 0 0 5 10 15 VREG (V) 20 25 30 0 0 5 10 15 VREG (V) 20 25 30 Figure 17. The Shaded Area Shows the Safe Operating Area of the CS5112 as a Function of ILIN, VREG, and qJA. Refer to Table 1 for Typical Loads and Voltages. Table 1. Linear Power Dissipation (W) 0.44 0.83 1.22 1.60 0.60 1.11 1.62 2.14 Worst Case Switcher Power Available (qJA = 55°C/W) (W) 0.74 0.35 * * 0.58 0.07 * * Worst Case Switcher Power Available (qJA = 35°C/W) (W) 1.42 1.03 0.64 0.26 1.26 0.75 0.24 * VREG (V) 20 20 20 20 25 25 25 25 VIN (V) 14 14 14 14 14 14 14 14 ILIN (mA) 25 50 75 100 25 50 75 100 *Subjecting the CS5112 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal limit. http://onsemi.com 12 CS5112 PACKAGE DIMENSIONS SOIC−24 DWF SUFFIX CASE 751E−04 ISSUE E −A− 24 13 −B− 12X P 0.010 (0.25) M B M 1 12 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 24X D 0.010 (0.25) M J TA S B S F R C −T− SEATING PLANE X 45 _ M 22X G K PACKAGE THERMAL DATA Parameter RqJC RqJA Typical Typical SOIC−24 9 55 Unit °C/W °C/W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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