CS8126-1YDPSR7G

CS8126 5.0 V, 750 mA Low Dropout Linear Regulator with Delayed RESET The CS8126 is a low dropout, high current 5.0 V linear regulator. It is an improved replacement for the CS8156. Improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced RESET circuitry. Familiar PNP regulator features such as reverse battery protection, overvoltage shutdown, thermal shutdown, and current limit make the CS8126 suitable for use in automotive and battery operated equipment. Additional on−chip filtering has been included to enhance rejection of high frequency transients on all external leads. An active microprocessor RESET function is included on−chip with externally programmable delay time. During power−up, or after detection of any error in the regulated output, the RESET lead will remain in the low state for the duration of the delay. Types of errors include short circuit, low input voltage, overvoltage shutdown, thermal shutdown, or others that cause the output to become unregulated. This function is independent of the input voltage and will function correctly with an output voltage as low as 1.0 V. Hysteresis is included in both the reset and Delay comparators for enhanced noise immunity. A latching discharge circuit is used to discharge the Delay capacitor, even when triggered by a relatively short fault condition. This circuit improves upon the commonly used SCR structure by providing full capacitor discharge (0.2 V type). Note: The CS8126 is lead compatible with the LM2927 and LM2926. Features • • • • • • Low Dropout Voltage (0.6 V at 0.5 A) 3.0% Output Accuracy Active RESET External RESET Delay for Reset Protection Circuitry − Reverse Battery Protection − +60 V, −50 V Peak Transient Voltage − Short Circuit Protection − Internal Thermal Overload Protection These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 18 http://onsemi.com MARKING DIAGRAM 1 D2PAK−7 DPS SUFFIX CASE 936AB CS 8126 AWLYWWG 7 Pin 1. VIN 2. VOUT 3. VOUT(SENSE) 4. GND 5. Delay 6. RESET 7. NC A W Y WW G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Device ORDERING INFORMATION Device Package Shipping† CS8126−1YDPS7G D2PAK−7 (Pb−Free) 50 Units / Rail CS8126−1YDPSR7G D2PAK−7 (Pb−Free) 750/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 1 Publication Order Number: CS8126/D CS8126 VIN Over Voltage Shutdown VOUT Regulated Supply for Circuit Bias Pre−Regulator Bandgap Reference − Error Amp Anti−Saturation and Current Limit + VOUT(SENSE) Charge Current Generator Thermal Shutdown Delay Latching Discharge Q S R − − + Reset Comparator + VDischarge + − GND Figure 1. Block Diagram http://onsemi.com 2 Delay Comparator RESET CS8126 MAXIMUM RATINGS* Rating Value Unit Internally Limited − −50, 60 V Internally Limited − 4.0 kV Package Thermal Resistance: Junction−to−Case, RqJC Junction−to−Ambient, RqJA 2.1 10−50** °C/W °C/W Junction Temperature Range −40 to +150 °C Storage Temperature Range −55 to +150 °C 260 peak 230 peak °C °C Power Dissipation Peak Transient Voltage (46 V Load Dump) Output Current ESD Susceptibility (Human Body Model) Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 10 second maximum. 2. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. **Depending on thermal properties of substrate. RqJA = RqJC + RqCA. ELECTRICAL CHARACTERISTICS (TA = −40°C to +125°C, TJ = −40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 kW to VCC , unless otherwise noted.) Characteristic Test Conditions Min Typ Max Unit − 4.85 5.00 5.15 V Output Stage (VOUT) Output Voltage Dropout Voltage IOUT1 = 500 mA − 0.35 0.60 V Supply Current IOUT ≤ 10 mA IOUT ≤ 100 mA IOUT ≤ 500 mA − − − 2.0 6.0 55 7.0 12 100 mA mA mA Line Regulation VIN = 6.0 to 26 V, IOUT = 50 mA − 5.0 50 mV Load Regulation IOUT = 50 to 500 mA, VIN = 14 V − 10 50 mV Ripple Rejection f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA 54 75 − dB Current Limit − 0.75 1.20 − A Overvoltage Shutdown − 32 − 40 V − 95 − V −15 −30 − V − −80 − V 150 180 210 °C Maximum Line Transient VOUT ≤ 5.5 V Reverse Polarity Input Voltage DC VOUT ≥ −0.6 V, 10 W Load Reverse Polarity Input Voltage Transient 1.0% Duty Cycle, T < 100 ms, 10 W Load Thermal Shutdown Note 3 3. Guaranteed By Design http://onsemi.com 3 CS8126 ELECTRICAL CHARACTERISTICS (continued) (TA = −40°C to +125°C, TJ = −40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 kW to VCC , unless otherwise noted.) Characteristic Test Conditions Min Typ Max Unit RESET and Delay Functions Delay Charge Current VDelay = 2.0 V 5.0 10 15 mA RESET Threshold VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) 4.65 4.50 4.90 4.70 VOUT − 0.01 VOUT − 0.15 V V RESET Hysteresis VRH = VRT(ON) − VRT(OFF) 150 200 250 mV Delay Threshold Charge, VDC(HI) Discharge, VDC(LO) 3.25 2.85 3.50 3.10 3.75 3.35 V V 200 400 800 mV Delay Hysteresis − RESET Output Voltage Low 1.0 V < VOUT < VRTL, 3.0 kW to VOUT − 0.1 0.4 V RESET Output Leakage Current VOUT > VRT(ON) − 0 10 mA Delay Capacitor Discharge Voltage Discharge Latched “ON”, VOUT > VRT − 0.2 0.5 V Delay Time CDelay = 0.1 mF*. Note 4 16 32 48 ms * Delay Time + CDelay VDelayThreshold Charge + CDelay ICharge 3.2 4. Assumes Ideal Capacitor PACKAGE LEAD DESCRIPTION PACKAGE LEAD # LEAD SYMBOL FUNCTION 1 VIN 2 VOUT Regulated 5.0 V output. 4 GND Ground connection. 5 Delay Timing capacitor for RESET function. 6 RESET 3 VOUT(SENSE) 7 NC Unregulated supply voltage to IC. CMOS/TTL compatible output lead. RESET goes low after detection of any error in the regulated output or during power up. Remote sensing of output voltage. No Connection. http://onsemi.com 4 CS8126 TYPICAL PERFORMANCE CHARACTERISTICS RLOAD = 25 W 55 50 45 ICQ (mA) ICQ (mA) 35 30 25°C 25 20 15 5.0 0 0 1.0 2.0 3.0 5.0 6.0 7.0 8.0 9.0 10 RLOAD = NO LOAD 0 1.0 2.0 3.0 7.0 8.0 4.5 4.0 3.5 3.5 3.0 125°C 2.5 2.0 −40°C 1.5 10 3.0 2.5 2.0 RLOAD = 10 0.5 25°C 2.0 9.0 RLOAD = 6.67 1.0 1.0 10 RLOAD = NO LOAD 1.5 1.0 0.5 9.0 Room Temp. 4.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 0 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VIN (V) VIN (V) Figure 4. VOUT vs. VIN Over Temperature Figure 5. VOUT vs. VIN Over RLOAD 6.0 VIN 6.0−26 V 80 6.0 5.5 5.0 100 5.0 Figure 3. ICQ vs. VIN Over RLOAD RLOAD = 25 W 0 4.0 Figure 2. ICQ vs. VIN Over Temperature 4.5 TEMP = −40°C 4.0 40 Load Regulation (mV) 60 TEMP = 25°C 20 TEMP = 40°C 0 −20 −40 TEMP = 125°C −60 2.0 0 −2.0 TEMP = 25°C −4.0 VIN = 14 V −6.0 TEMP = 125°C −8.0 −10 −80 −100 RLOAD = 25 VIN (V) VOUT (V) VOUT (V) 4.0 10 0 5.0 0 RLOAD = 10 50 40 VIN (V) 5.5 Line Regulation (mV) 70 60 30 20 −40°C 10 RLOAD = 6.67 100 90 80 125°C 40 Room Temp. 120 110 −12 0 100 200 300 400 500 600 700 −14 800 0 100 200 300 400 500 600 700 Output Current (mA) Output Current (mA) Figure 6. Line Regulation vs. Output Current Over Temperature Figure 7. Load Regulation vs. Output Current Over Temperature http://onsemi.com 5 800 CS8126 900 100 800 90 25°C 700 600 Quiescent Current (mA) Dropout Voltage (mV) TYPICAL PERFORMANCE CHARACTERISTICS (continued) 125°C 500 400 300 −40°C 200 100 0 0 100 200 300 25°C VIN = 14 V 70 −40°C 60 50 40 30 20 400 500 600 700 0 800 100 200 300 400 500 600 700 Output Current (mA) Figure 8. Dropout Voltage vs. Output Current Over Temperature Figure 9. Quiescent Current vs. Output Current Over Temperature 800 103 COUT C 10mF, mF,ESR = 1 OUT ==10 & ESR 0.1=mF, 1 &ESR 0.1 =mF, 0 ESR = 0 70 102 101 50 100 40 ESR (W) 60 COUT = 10 mF, ESR = 1.0 W 30 COUT = 47/68 mF Stable Region 10−1 COUT = 47 mF 10−2 20 COUT = 10 mF, ESR = 10 W 10 100 0 Output Current (mA) 80 Rejection (dB) 80 10 90 0 125°C 101 102 103 104 105 106 COUT = 68 mF 10−3 107 10−4 108 100 101 102 Freq. (Hz) Output Current (mA) Figure 10. Ripple Rejection Figure 11. Output Capacitor ESR 103 RESET CIRCUIT WAVEFORM VOUT VRT(ON) VRT(OFF) (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max:RESET Voltage (1.0 V) VRH (1) RESET (2) (3) VRL tDelay Delay VDC(HI) VDC(LO) VDH VDIS (2) Figure 12. RESET Circuit Waveform http://onsemi.com 6 CS8126 CIRCUIT DESCRIPTION voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage falls below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled RESET pulse is generated following detection of an error condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(H1). The Delay time for the RESET function is calculated from the formula: The CS8126 RESET function, has hysteresis on both the Reset and Delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram). Low Voltage Inhibit Circuit This circuit monitors output voltage, and when the output voltage falls below VRT(OFF), causes the RESET output transistor to be in the ON (saturation) state. When the output voltage rises above VRT(ON), this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit. Delay time + CDelay VDelayThreshold ICharge Delay time + CDelay RESET Delay Circuit VOUT VIN RRST 4.7 kW CS8126 Delay 0.1 mF 105 If CDelay = 0.1 mF, Delay time (ms) = 32 ms ± 50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the “Low Voltage Inhibit” circuit indicates that output C1 * 100 nF 3.2 C2** 10 mF to 100 mF RESET Delay GND * C1 is required if the regulator is far from the power source filter. ** C2 is required for stability. Figure 13. Application Diagram APPLICATION NOTES Stability Considerations temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low http://onsemi.com 7 CS8126 Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: RQJA + (2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN IOUT VIN SMART REGULATOR® VOUT Control Features IQ Figure 14. Single Output Regulator With Key Performance Parameters Labeled Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. RQJA + RQJC ) RQCS ) RQSA (3) where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heatsink thermal resistance, and RqSA = the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 14) is: PD(max) + NJVIN(max) * VOUT(min)NjIOUT(max) ) VIN(max)IQ 150° C * TA PD (1) SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK−7 (SHORT LEAD) CASE 936AB−01 ISSUE B DATE 08 SEP 2009 A 1 SCALE 1:1 E L1 B A 0.10 A E/2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.005 MAXIMUM PER SIDE. THESE DIMENSIONS TO BE MEASURED AT DATUM H. 4. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS E, L1, D1, AND E1. DIMENSIONS D1 AND E1 ESTABLISH A MINIMUM MOUNTING SURFACE FOR THE THERMAL PAD. SEATING PLANE M B A M E1 c2 D1 D 7X H DETAIL C e b 0.13 M B A VIEW A−A c A M B H SEATING PLANE A1 RECOMMENDED SOLDERING FOOTPRINT* L 0.424 INCHES MIN MAX 0.170 0.180 0.000 0.010 0.026 0.036 0.017 0.026 0.045 0.055 0.325 0.368 0.270 −−− 0.380 0.420 0.245 −−− 0.050 BSC 0.539 0.579 0.058 0.078 −−− 0.066 0.010 BSC 0° 8° MILLIMETERS MIN MAX 4.32 4.57 0.00 0.25 0.66 0.91 0.43 0.66 1.14 1.40 8.25 9.53 6.86 −−− 9.65 10.67 6.22 −−− 1.27 BSC 13.69 14.71 1.47 1.98 −−− 1.68 0.25 BSC 0° 8° GENERIC MARKING DIAGRAM* M L3 DIM A A1 b c c2 D D1 E E1 e H L L1 L3 M GAUGE PLANE XX XXXXXXXXX AWLYWWG DETAIL C 0.310 0.584 1 XXXXX A WL Y WW G 0.136 7X 0.050 PITCH 0.040 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14119D D2PAK−7 (SHORT LEAD) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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