CS8156
12 V, 5.0 V Low Dropout
Dual Regulator with ENABLE
The CS8156 is a low dropout 12 V/5.0 V dual output linear regulator.
The 12 V ±5.0% output sources 750 mA and the 5.0 V ±2.0% output
sources 100 mA.
The on board ENABLE function controls the regulator’s two
outputs. When the ENABLE lead is low, the regulator is placed in
SLEEP mode. Both outputs are disabled and the regulator draws only
200 nA of quiescent current.
The regulator is protected against overvoltage conditions. Both
outputs are protected against short circuit and thermal runaway
conditions.
The CS8156 is packaged in a 5 lead TO−220 with copper tab. The
copper tab can be connected to a heat sink if necessary.
Features
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TO−220
FIVE LEAD
T SUFFIX
CASE 314D
1
5
TO−220
FIVE LEAD
TVA SUFFIX
CASE 314K
1
• Two Regulated Outputs
− 12 V ±5.0%; 750 mA
− 5.0 V ±2.0%; 100 mA
• Very Low SLEEP Mode Current Drain 200 nA
• Fault Protection
− Reverse Battery
− +60 V, −50 V Peak Transient Voltage
− Short Circuit
− Thermal Shutdown
• CMOS Compatible ENABLE
• Pb−Free Packages are Available
1
TO−220
FIVE LEAD
THA SUFFIX
CASE 314A
5
PIN CONNECTIONS AND
MARKING DIAGRAM
CS
8156
AWLYWWG
Tab = GND
Pin 1. VIN
2. VOUT1
3. GND
4. ENABLE
5. VOUT2
1
CS8156
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 8
1
Publication Order Number:
CS8156/D
CS8156
VOUT2, 5.0 V
VIN
Anti−saturation
and
Current Limit
ENABLE
−
+
+
−
Pre−Regulator
VOUT1, 12 V
Overvoltage
Shutdown
Anti−saturation
and
Current Limit
Bandgap
Reference
+
−
GND
Thermal
Shutdown
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
−0.5 to 26
60
V
V
Internally Limited
−
Operating Temperature Range
−40 to +125
°C
Junction Temperature Range
−40 to +150
°C
Storage Temperature Range
−65 to +150
°C
260 peak
°C
Input Voltage:
Operating Range
Peak Transient Voltage (Note 1)
Internal Power Dissipation
Lead Temperature Soldering:
Wave Solder (through hole styles only) (Note 2)
1. Load Dump = 46 V
2. 10 second maximum.
*The maximum package power dissipation must be observed.
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2
CS8156
ELECTRICAL CHARACTERISTICS for VOUT: (VIN = 14.5 V, IOUT1 = 5.0 mA, IOUT2 = 5.0 mA, −40°C ≤ TJ ≤ +150°C,
−40°C ≤ TC ≤ +125°C; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Voltage, (VOUT1)
13 V ≤ VIN ≤ 16 V, IOUT1 ≤ 750 mA
11.2
12.0
12.8
V
Dropout Voltage
IOUT1 = 500 mA
IOUT1 = 750 mA
−
0.4
0.6
0.6
1.0
V
V
Line Regulation
13 V ≤ VIN ≤ 16 V, 5.0 mA ≤ IOUT1 < 100 mA
−
15
80
mV
Load Regulation
5.0 mA ≤ IOUT1 ≤ 500 mA
−
15
80
mV
Quiescent Current
IOUT1 ≤ 500 mA, No Load on Standby
IOUT1 ≤ 750 mA, No Load on Standby
−
−
45
100
125
250
mA
mA
Quiescent Current (Sleep Mode)
ENABLE = Low
−
0.2
50
µA
Ripple Rejection
f = 120 Hz, IOUT = 5.0 mA, VIN = 1.5 VPP at 15.5 VDC
42
70
−
dB
−
0.75
1.20
2.50
A
Output Stage (VOUT1)
Current Limit
Maximum Line Transient
VOUT1 ≤ 13 V
60
90
−
V
Reverse Polarity Input Voltage, DC
VOUT1 ≥ −0.6 V, 10 Ω Load
−18
−30
−
V
Reverse Polarity Input Voltage,
Transient
1.0% Duty Cycle, t = 100 ms, VOUT ≥ −6.0 V,
10 Ω Load
−50
−80
−
V
Output Noise Voltage
10 Hz − 100 kHz
−
−
500
µVrms
Output Impedance
500 mA DC and 10 mA rms, 100Hz
−
0.2
1.0
Ω
28
34
45
V
4.90
5.00
5.10
V
Overvoltage Shutdown
−
Standby Output (VOUT2)
Output Voltage, (VOUT2)
9.0 V ≤ VIN ≤ 16 V, 1.0 mA ≤ IOUT2 ≤ 100 mA
Dropout Voltage
IOUT2 ≤ 100 mA
−
−
0.60
V
Line Regulation
6.0 V ≤ VIN ≤ 26 V, 1.0 mA ≤ IOUT ≤ 100 mA
−
5.0
50
mV
Load Regulation
1.0 mA ≤ IOUT2 ≤ 100 mA; 9.0 V ≤ VIN ≤ 16 V
−
5.0
50
mV
Ripple Rejection
f = 120 Hz; IOUT = 100 mA, VIN = 1.5 VPP at 14.5 VDC
42
70
−
dB
−
100
200
−
mA
Current Limit
ENABLE Function (ENABLE)
Input ENABLE Threshold
VOUT1 Off
VOUT1 On
−
2.00
1.25
1.25
0.80
−
V
V
Input ENABLE Current
VENABLE ≤ VTHRESHOLD
−10
0
10
µA
PACKAGE PIN DESCRIPTION
PACKAGE LEAD #
5 Lead TO−220
LEAD SYMBOL
1
VIN
2
VOUT1
3
GND
4
ENABLE
5
VOUT2
FUNCTION
Supply voltage, usually direct from battery.
Regulated output 12 V, 750 mA (typ).
Ground connection.
CMOS compatible input lead; switches outputs on and off.
When ENABLE is high VOUT1 and VOUT2 are active.
Regulated output 5.0 V, 100 mA (typ).
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3
CS8156
TYPICAL PERFORMANCE CHARACTERISTICS
2000
1600
Output Voltage (V)
Dropout Voltage (mV)
1800
1400
1200
1000
800
600
400
200
0
0
50
100
150
13
12
11
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
−1.0
−2.0
RL = 10 Ω
200
−40
−20
0
20
40
IOUT (mA)
Input Voltage (V)
Figure 2. Dropout Voltage vs. IOUT2
Figure 3. VOUT1 vs. Input Voltage
12.15
60
5.030
12.10
5.020
5.010
12.00
VOUT2 (V)
VOUT1 (V)
12.05
11.95
11.90
5.000
4.990
11.85
4.980
11.80
11.75
0
20
40
60
80
4.970
100 120 140 160
−40 −20
0
20
40
60
80
100 120 140 160
Temp (°C)
Temp (°C)
Figure 4. VOUT1 vs. Temperature
Figure 5. VOUT2 vs. Temperature
100
5.0
80
4.0
IENABLE (mA)
IENABLE (µA)
−40 −20
60
40
20
3.0
2.0
1.0
0
0
1.0
2.0
3.0
4.0
0
5.0
VENABLE (V)
0
5.0
10
15
20
VENABLE (V)
Figure 6. ENABLE Current vs.
ENABLE Voltage
Figure 7. ENABLE Current vs. ENABLE
Voltage
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25
CS8156
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
10
10
0
−10
−20
3.0
2.0
1.0
0
0
10
20
30
40
50
−5.0
−10
3.0
2.0
1.0
0
60
0
20
30
40
50
60
Figure 8. Line Transient Response (VOUT1)
Figure 9. Line Transient Response (VOUT2)
150
100
100
50
0
−50
−100
Standby Load
Current (mA)
0.8
0.6
0.4
0.2
50
0
−50
−100
−150
0
20
15
10
5.0
0
0
10
20
30
40
50
60
0
10
20
30
40
50
Time (µs)
Time (µs)
Figure 10. Load Transient Response
(VOUT1)
Figure 11. Load Transient Response
(VOUT2)
20
18
Infinite Heat Sink
16
Quiescent Current (mA)
Power Dissipation (W)
10
Time (µs)
−150
Load
Current (A)
0
150
14
12
10
8.0
10°C/W Heat Sink
6.0
4.0
No Heat Sink
2.0
0
0
IOUT2 = 100 mA
5.0
Time (µs)
Standby
Output Voltage
Deviation (mV)
Output Voltage
Deviation (mV)
Output Voltage
Deviation (mV)
IOUT1 = 500 mA
Input Voltage
Chnage (V)
Input Voltage
Change (V)
Output Voltage
Deviation (mV)
20
10
20
30
40
50
60
70
80
90
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
60
No Load on 5.0 V
125°C
VIN = 14 V
25°C
−40°C
0
100
200
300
400
500
600
700
Ambient Temperature (°C)
Output Current (mA)
Figure 12. Maximum Power Dissipation
(TO−220)
Figure 13. Quiescent Current vs. Output
Current for VOUT2
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5
800
CS8156
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
22
2.0
18
16
Line Regulation (mV)
Quiescent Current (mA)
3.0
No Load on 5.0 V
20
VIN = 14 V
14
12
10
8.0
−40°C
6.0
4.0
25°C
−40°C
−1.0
125°C
−2.0
−3.0
VIN = 6.0−26 V
−4.0
−6.0
0
20
40
60
80
100
120
140
0
80
100
120
140
Figure 15. Line Regulation vs. Output
Current for VOUT2
25°C
Line Regulation (mV)
−4.0
−6.0
−8.0
−10
−12
125°C
VIN = 14 V
−18
20
40
60
80
100
120
25
20
15
10
5.0
0
−5.0
−10
−15
−20
−25
−30
−35
−40
140
125°C
25°C
VIN = 13−26V
−40°C
0
100
200
300
400
500
600
700
Output Current (mA)
Output Current (mA)
Figure 16. Load Regulation vs. Output
Current fo VOUT2
Figure 17. Line Regulation vs. Output
Current for VOUT1
0
−5.0
Load Regulation (mV)
0
60
Figure 14. Quiescent Current vs. Output
Current for VOUT1
−2.0
−16
40
Output Current (mA)
−40°C
−14
20
Output Current (mA)
0
Load Regulation (mV)
25°C
0
−5.0
125°C
2.0
0
1.0
−40°C
−10
25°C
−15
−20
125°C
−25
−30
VIN = 14 V
−35
−40
0
100
200
300
400
500
600
700
Output Current (mA)
Figure 18. Load Regulation vs. Output
Current for VOUT1
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800
800
CS8156
DEFINITION OF TERMS
Dropout Voltage − The input−output voltage differential
at which the circuit ceases to regulate against further
reduction in input voltage. Measured when the output
voltage has dropped 100 mV from the nominal value
obtained at 14 V input, dropout voltage is dependent upon
load current and junction temperature.
Input Voltage − The DC voltage applied to the input
terminals with respect to ground.
Input Output Differential − The voltage difference
between the unregulated input voltage and the regulated
output voltage for which the regulator will operate.
Line Regulation − The change in output voltage for a
change in the input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that the average chip temperature is not significantly
affected.
Load Regulation − The change in output voltage for a
change in load current at constant chip temperature.
Long Term Stability − Output voltage stability under
accelerated life−test conditions after 1000 hours with
maximum rated voltage and junction temperature.
Output Noise Voltage − The rms AC voltage at the
output, with constant load and no input ripple, measured
over a specified frequency range.
Quiescent Current − The part of the positive input
current that does not contribute to the positive load current,
i.e., the regulator ground lead current.
Ripple Rejection − The ratio of the peak−to−peak input
ripple voltage to the peak−to−peak output ripple voltage.
Temperature Stability of VOUT − The percentage
change in output voltage for a thermal variation from room
temperature to either temperature extreme.
60 V
VIN
14 V
ENABLE
2.0 V
0.8 V
34 V
26 V
14V
3.0 V
12 V
12 V
12 V
12 V
12 V
2.4 V
VOUT1
0V
0V
0V
5.0 V
VOUT2
5.0 V
2.4 V
0V
Turn
On
Load
Dump
Low VIN
Line
Noise, Etc.
VOUT1
Short
Circuit
VOUT2
Short
Circuit
VOUT1
Thermal
Shutdown
Turn
Off
Figure 19. Typical Circuit Waveform
APPLICATION NOTES
Stability Considerations
recommended value and work towards a less expensive
alternative part for each output.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor C2 will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using the
decade box and vary the load current until oscillations
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the
cheapest solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitors C2 and C3 shown in
the test and applications circuit should work for most
applications, however it is not necessarily the best solution.
To determine acceptable values for C2 and C3 for a
particular application, start with a tantalum capacitor of the
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7
CS8156
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4 with
the next smaller valued capacitor. A smaller capacitor will
usually cost less and occupy less board space. If the output
oscillates within the range of expected operating conditions,
repeat steps 3 and 4 with the next larger standard capacitor
value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found for each output, a safety factor should be added
to allow for the tolerance of the capacitor and any variations
in regulator performance. Most good quality aluminum
electrolytic capacitors have a tolerance of ±20% so the
minimum value found should be increased by at least 50%
to allow for this tolerance plus the variation which will occur
at low temperatures. The ESR of the capacitors should be
less than 50% of the maximum allowable ESR found in step
3 above.
Repeat steps 1 through 7 with C3, the capacitor on the
other output.
The value of RΘJA can be compared with those in the
package section of the data sheet. Those packages with
RΘJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
IIN
IOUT1
Smart
Regulator
VIN
VOUT1
IOUT2
Control
Features
VOUT2
IQ
Figure 20. Dual Output Regulator With Key
Performance Parameters Labeled.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RΘJA:
RQJA + RQJC ) RQCS ) RQSA
(3)
where:
RΘJC = the junction−to−case thermal resistance,
RΘCS = the case−to−heatsink thermal resistance, and
RΘSA = the heatsink−to−ambient thermal resistance.
Calculating Power Dissipation in a
Dual Output Linear Regulator
The maximum power dissipation for a dual output
regulator (Figure 20) is
RΘJC appears in the package section of the data sheet. Like
RΘJA, it too is a function of package type. RΘCS and RΘSA
are functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
PD(max) + NJVIN(max) * VOUT1(min)NjIOUT1(max) )
NJVIN(max) * VOUT2(min)NjIOUT2(max) ) VIN(max)IQ (1)
where:
VIN(max) is the maximum input voltage,
VOUT1(min) is the minimum output voltage from VOUT1,
VOUT2(min) is the minimum output voltage from VOUT2,
IOUT1(max) is the maximum output current, for the
application,
IOUT2(max) is the maximum output current, for the
application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
C1*
0.1 µF
VIN
CS8156
VOUT1
+
ENABLE
GND
VOUT2
+
C2**
22 µF
C3**
22 µF
Once the value of PD(max) is known, the maximum
permissible value of RΘJA can be calculated:
RQJA +
150°C * TA
PD
* C1 is required if the regulator is far from power supply filter.
** C2, C3 required for stability.
(2)
Figure 21. Test & Application Circuit
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8
CS8156
ORDERING INFORMATION
Package
Shipping †
CS8156YT5
TO−220 FIVE LEAD STRAIGHT
50 Units/Rail
CS8156YT5G
TO−220 FIVE LEAD STRAIGHT
(Pb−Free)
50 Units/Rail
CS8156YTVA5
TO−220 FIVE LEAD VERTICAL
50 Units/Rail
CS8156YTVA5G
TO−220 FIVE LEAD VERTICAL
(Pb−Free)
50 Units/Rail
CS8156YTHA5
TO−220 FIVE LEAD HORIZONTAL
50 Units/Rail
CS8156YTHA5G
TO−220 FIVE LEAD HORIZONTAL
(Pb−Free)
50 Units/Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
CS8156
PACKAGE DIMENSIONS
TO−220
FIVE LEAD
T SUFFIX
CASE 314D−04
ISSUE E
−T−
−Q−
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
C
B
E
A
U
L
K
J
H
G
D
DIM
A
B
C
D
E
G
H
J
K
L
Q
U
1234 5
5 PL
0.356 (0.014)
M
T Q
M
INCHES
MIN
MAX
0.572
0.613
0.390
0.415
0.170
0.180
0.025
0.038
0.048
0.055
0.067 BSC
0.087
0.112
0.015
0.025
0.990
1.045
0.320
0.365
0.140
0.153
0.105
0.117
MILLIMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318
4.572
0.635
0.965
1.219
1.397
1.702 BSC
2.210
2.845
0.381
0.635
25.146 26.543
8.128
9.271
3.556
3.886
2.667
2.972
TO−220
FIVE LEAD
TVA SUFFIX
CASE 314K−01
ISSUE O
−T−
SEATING
PLANE
C
B
−Q−
E
W
A
U
F
L
1
2
3
4
K
5
M
D
0.356 (0.014)
M
J
5 PL
T Q
M
G
S
R
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10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
DIM
A
B
C
D
E
F
G
J
K
L
M
Q
R
S
U
W
INCHES
MIN
MAX
0.560
0.590
0.385
0.415
0.160
0.190
0.027
0.037
0.045
0.055
0.530
0.545
0.067 BSC
0.014
0.022
0.785
0.800
0.321
0.337
0.063
0.078
0.146
0.156
0.271
0.321
0.146
0.196
0.460
0.475
5°
MILLIMETERS
MIN
MAX
14.22
14.99
9.78
10.54
4.06
4.83
0.69
0.94
1.14
1.40
13.46
13.84
1.70 BSC
0.36
0.56
19.94
20.32
8.15
8.56
1.60
1.98
3.71
3.96
6.88
8.15
3.71
4.98
11.68
12.07
5°
CS8156
TO−220
FIVE LEAD
THA SUFFIX
CASE 314A−03
ISSUE E
−T−
B
−P−
Q
C
E
OPTIONAL
CHAMFER
A
U
F
L
G
5X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
SEATING
PLANE
DIM
A
B
C
D
E
F
G
J
K
L
Q
S
U
K
5X
J
S
D
0.014 (0.356)
M
T P
M
INCHES
MIN
MAX
0.572
0.613
0.390
0.415
0.170
0.180
0.025
0.038
0.048
0.055
0.570
0.585
0.067 BSC
0.015
0.025
0.730
0.745
0.320
0.365
0.140
0.153
0.210
0.260
0.468
0.505
MILLIMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318
4.572
0.635
0.965
1.219
1.397
14.478 14.859
1.702 BSC
0.381
0.635
18.542 18.923
8.128
9.271
3.556
3.886
5.334
6.604
11.888 12.827
PACKAGE THERMAL DATA
Parameter
TO−220
FIVE LEAD
Unit
RΘJC
Typical
2.0
°C/W
RΘJA
Typical
50
°C/W
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