CS8312
IGBT Ignition Predriver with
Dynamic Current Regulation
The CS8312 is a bipolar microprocessor interface IC designed to
drive an IGBT (or logic level MOSFETs) powering large inductive
loads in harsh operating environments. The IC’s dynamic current
limit function lets the microprocessor adjust the current limit threshold
to the real time needs of the system.
CLI, the current limit input, sets the current limit for the IGBT high
or low as directed by the system microprocessor. CLI also raises and
lowers the threshold on the diagnostic FLAG output signal. The
FLAG output signals the microprocessor when the current level
approaches current limit on the IGBT. The CTRL input enables the
FLAG function.
Features
µP Compatible Inputs
Adjustable Current Limit Thresholds
External Sense Resistor
Flag Signal to Indicate Output Status
8
8
1
DIP–8
N SUFFIX
CASE 626
CS8312YN8
AWL
YYWW
8
8
CS831
ALYW2
1
SO–8
D SUFFIX
CASE 751
VCC
Control
Logic
MARKING
DIAGRAMS
1
•
•
•
•
CTRL
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Gate
Driver
1
A
WL, L
YY, Y
WW, W
OUT
= Assembly Location
= Wafer Lot
= Year
= Work Week
5.0 V
VT
PIN CONNECTIONS
SENSE+
FLAG
FLAG
Latch
VREF
VT
GND
CLI
1
VCC
SENSE+
CTRL
SENSE–
GND
CLI
OUT
SENSE–
ORDERING INFORMATION
Figure 1. Block Diagram
Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 4
Device
1
Package
Shipping
CS8312YN8
DIP–8
50 Units/Rail
CS8312YD8
SO–8
95 Units/Rail
CS8312YDR8
SO–8
2500 Tape & Reel
Publication Order Number:
CS8312/D
CS8312
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
–0.3 to 12
V
Digital Input Currents
2.0
mA
Internal Power Dissipation (TA = 25°C)
700
mW
Junction Temperature Range
–40 to +150
°C
Storage Temperature Range
–55 to +165
°C
2.0
kV
260 peak
230 peak
°C
°C
Supply Voltage
Electrostatic Discharge (Human Body Model)
Lead Temperature Soldering
Wave Solder (through hole styles only) Note 1.
Reflow (SMD styles only) Note 2.
1. 10 seconds max.
2. 60 seconds max above 183°C
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (7.0 V ≤ VCC ≤ 10 V, –40°C ≤ TA ≤ 125°C,
–0.2 V ≤ Differential Ground Voltage ≤ 0.8 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Power Supply Including Ripple Voltage
–
7.0
–
10
V
Supply Ripple Frequency
–
10
–
60
kHz
Differential Ground Frequency
–
10
–
60
kHz
General
Quiescent Current, IQ
Turn On
Turn Off
VCTRL = 5.5 V
VCTRL = –0.3 V
–
–
–
–
15
5.0
mA
mA
Supply Voltage Rejection
VCTRL = 5.5 V
30
–
–
dB
Differential Ground Rejection Ratio
VCTRL = 5.5 V
30
–
–
dB
Differential Ground Current Ratio
VCTRL = –0.3 V,
(VSENSE– – VGND)DC = 1.0 V
(VSENSE– – VGND)AC = 0.6 V
–
–
3.0
mA
Unity Gain Bandwidth
VCTRL = 5.5 V
400
–
–
kHz
Turn On Delay
CTRL Increasing
–
–
30
µs
Turn Off Delay
CTRL Decreasing
–
–
30
µs
Control Function
Input Voltage Range
ICTRL = 2.0 mA
–0.3
–
5.5
V
Input Threshold
Turn On
Turn Off
Hysteresis
CTRL Increasing
CTRL Decreasing
–
1.5
0.4
–
–
–
3.5
–
2.0
V
V
V
Voltage
ICTRL = 10 µA max
–
–
1.1
V
–
–
50
pF
Input Capacitance
–
Current Limit Increase Function
Input Voltage Range
ICTRL = 2.0 mA
–0.3
–
5.5
V
Input Threshold
Turn On
Turn Off
Hysteresis
CLI Increasing
CLI Decreasing
–
1.5
0.4
–
–
–
3.5
–
2.0
V
V
V
Voltage
ICLI = 10 µA max
–
–
1.1
V
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2
CS8312
ELECTRICAL CHARACTERISTICS (continued) (7.0 V ≤ VCC ≤ 10 V, –40°C ≤ TA ≤ 125°C,
–0.2 V ≤ Differential Ground Voltage ≤ 0.8 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
–
–
–
50
pF
–
–
–
5.0
mA
Current Limit Increase Function (continued)
Input Capacitance
Output Stage
IOUT
Clamp Voltage
VCTRL = 5.5 V, IOUT = 1.0 mA
4.0
–
5.5
V
Output Off Voltage
VCTRL = –0.3 V, IOUT = 10 µA
VCTRL = –0.3 V, IOUT = 200 µA
–
–
–
–
0.5
1.2
V
V
Output Low
VCTRL = 5.5 V, IFLAG = 1.5 mA
–
–
0.9
V
Leakage Current
VCTRL = –0.3 V
–
–
10
µA
–
–
50
pF
210
300
225
–
240
350
mV
mV
–
–
10
µs
Flag Function
Output Capacitance
–
Turn On (VSENSE+ – VSENSE–)
VCTRL = 5.5 V, VCLI = –0.3 V
VCTRL = 5.5 V, VCLI = 5.5 V
Turn Off Delay
CTRL Decreasing
Turn On Delay
–
–
–
10
µs
Disable Time
–
100
–
450
µs
–
–0.3
–
2.5
V
270
380
295
410
320
440
mV
mV
Sense Function
Input Voltage Range
Sense Regulation Voltage
VCTRL = 5.5 V, VCLI = –0.3 V
VCTRL = 5.5 V, VCLI = 5.5 V
Input Leakage Current
VCTRL = 5.5 V
–
–
5.0
µA
Propagation Delay
VCTRL = 5.5 V
–
–
20
µs
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
DIP–8
SO–8
PIN SYMBOL
1
1
FLAG
2
2
SENSE+
Positive input to current comparator.
3
3
SENSE–
Ground (SENSE–) for current sense resistor.
4
4
GND
Ground connection.
5
5
OUT
Output voltage to IGBT (MOSFET) gate.
6
6
CLI
Current limit input increase.
7
7
CTRL
8
8
VCC
FUNCTION
Indicates whether current through the IGBT has reached a preset level.
Control input.
Supply voltage.
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3
CS8312
CIRCUIT DESCRIPTION
Flag Function (See Figure 2)
Output Stage
The flag indicates when the voltage across the two sense
pins is approaching a current limit level that has been
determined by the value of the external sense resistor
(RSENSE) and the state of the CTRL and CLI pins. If the
voltage across the sense pins (SENSE+, SENSE–) is less
than the flag turn–on voltage, then the FLAG is off. When
the voltage between the sense pins equals the FLAG turn on
voltage, the FLAG will latch on until the CTRL pin goes
low. FLAG is disabled whenever CTRL is low. Changing the
CLI pin from low to high will increase nominal FLAG turn
on voltage by approximately 45%.
The CS8312 output (OUT) saturates and supplies voltage
to the IGBT (or MOSFET) gate once the CTRL switches
from low to high. As current through the IGBT (MOSFET)
increases and the voltage across the sense resistor passes the
flag turn on voltage, the FLAG will turn on. If the current
through the sense resistor continues to rise and the sense
resistor voltage reaches the regulation sense voltage, then
the gate voltage will fall to a level that regulates the driver
and maintains the regulation sense voltage at the sense
resistor.
Current Limit Function
Table 1. FLAG Timing Sequence
State
CONTROL
SENSE+
FLAG
0
Low
X
OFF
1
High
Below Threshold
OFF
2
High
Above Threshold
ON
3
High
X
ON
0
Low
X
OFF
Changing the CLI pin from a logic low to a logic high
increases the FLAG turn on voltage by approximately 45%
and the regulation sense voltage by approximately 39%
respectively.
VCC
VBAT
0.1 µF
LOAD
VCC
VCC
OUT
CS8312
R
FLAG
Microprocessor
CTRL
SENSE+
CLI
RSENSE
SENSE–
GND
Figure 2. Application and Test Diagram
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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