DM74LS191N

Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a LOW-to-HIGH level transition of the clock input, if the enable input is LOW. A HIGH at the enable input inhibits counting. Level changes at either the enable input or the down/up input should be made only when the clock input is HIGH. The direction of the count is determined by the level of the down/up input. When LOW, the counter counts up and when HIGH, it counts down. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. Features ■ Counts binary The counter is fully programmable; that is, the outputs may be preset to either level by placing a LOW on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. ■ Single down/up count control line The clock, down/up, and load inputs are buffered to lower the drive requirement; which significantly reduces the number of clock drivers, etc., required for long parallel words. ■ Average propagation delay 20 ns ■ Count enable control input ■ Ripple clock output for cascading ■ Asynchronously presettable with load control ■ Parallel outputs ■ Cascadable for n-bit applications ■ Typical clock frequency 25 MHz ■ Typical power dissipation 100 mW Ordering Code: Order Number Package Number Package Description DM74LS191M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body DM74LS191N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 1999 Fairchild Semiconductor Corporation DS006405.prf www.fairchildsemi.com DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control August 1986 DM74LS191 Connection Diagram Timing Diagram www.fairchildsemi.com 2 DM74LS191 Logic Diagram Pin (16) = VCC, Pin (8) = GND 3 www.fairchildsemi.com DM74LS191 Absolute Maximum Ratings(Note 1) Storage Temperature Range −65°C to +150°C Input Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V 0°C to +70°C Operating Free Air Temp. Range Supply Voltage 7V Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA 2 IOL LOW Level Output Current fCLK Clock Frequency (Note 2) tW Pulse Width Clock 25 (Note 2) Load 35 V V 0 8 mA 20 MHz ns tSU Data Setup Time (Note 2) 20 ns tH Data Hold Time (Note 2) 0 ns tEN Enable Time to Clock (Note 2) 30 TA Free Air Operating Temperature 0 ns 70 °C Max Units −1.5 V Note 2: TA = 25°C and VCC = 5V. DC Electrical Characteristics Symbol Parameter Conditions Min Typ (Note 3) VI Input Clamp Voltage VCC = Min, II = − 18 mA VOH HIGH Level Output VCC = Min, IOH = Max Mil 2.5 Voltage VIL = Max, VIH = Min Com 2.7 LOW Level Output VCC = Min, IOL = Max 0.25 0.4 VIL = Max, VIH = Min 0.35 0.5 IOL = 4 mA, VCC = Min 0.25 0.4 VOL Voltage II IIH IIL IOS ICC 3.4 3.4 V Input Current @ Max VCC = Max Enable 0.3 Input Voltage VI = 7V Others 0.1 HIGH Level Input VCC = Max Enable 60 Current VI = 2.7V Others 20 LOW Level Input VCC = Max Enable −1.08 Current VI = 0.4V Others −0.4 Short Circuit VCC = Max Output Current (Note 4) Supply Current VCC = Max (Note 5) Mil −20 −100 Com −20 −100 20 Note 3: All typicals are at VCC = 5V, TA = 25°C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all inputs grounded and all outputs open. www.fairchildsemi.com 4 35 V mA µA mA mA mA RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock CL = 50 pF Max 20 Min Units Max 20 MHz Frequency tPLH tPHL tPLH tPHL tPLH Propagation Delay Time Load to LOW-to-HIGH Level Output Any Q Propagation Delay Time Load to HIGH-to-LOW Level Output Any Q Propagation Delay Time Data to LOW-to-HIGH Level Output Any Q Propagation Delay Time Data to HIGH-to-LOW Level Output Any Q Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH tPHL tPLH tPHL tPLH tPLH Clock to Clock to Clock to HIGH-to-LOW Level Output Max/Min Propagation Delay Time Up/Down to LOW-to-HIGH Level Output Ripple Clock Propagation Delay Time Up/Down to HIGH-to-LOW Level Output Ripple Clock Propagation Delay Time Down/Up to Propagation Delay Time HIGH-to-LOW Level Output 59 ns 22 26 ns 50 62 ns 20 24 ns 24 33 ns 24 29 ns 36 45 ns 42 47 ns 52 65 ns 45 50 ns 45 54 ns 33 36 ns 33 42 ns 33 36 ns 33 42 ns Any Q Propagation Delay Time Propagation Delay Time 50 Any Q Clock to LOW-to-HIGH Level Output tPHL Clock to Max/Min HIGH-to-LOW Level Output ns Ripple Clock LOW-to-HIGH Level Output Propagation Delay Time 43 Ripple Clock Propagation Delay Time LOW-to-HIGH Level Output tPHL Clock to 33 Max/Min Down/Up to Max/Min Enable to Ripple Clock Enable to Ripple Clock 5 www.fairchildsemi.com DM74LS191 AC Electrical Characteristics DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS012, 0.150” Narrow Body Package Number M16A 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.